JPS5633742A - Arithmetic processor having debug processing function - Google Patents
Arithmetic processor having debug processing functionInfo
- Publication number
- JPS5633742A JPS5633742A JP10839879A JP10839879A JPS5633742A JP S5633742 A JPS5633742 A JP S5633742A JP 10839879 A JP10839879 A JP 10839879A JP 10839879 A JP10839879 A JP 10839879A JP S5633742 A JPS5633742 A JP S5633742A
- Authority
- JP
- Japan
- Prior art keywords
- instruction
- debug
- address
- program
- register
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Debugging And Monitoring (AREA)
Abstract
PURPOSE: To ensure a correct debug for the program having a loop, by carrying out the replacement between the debug instruction and the original instruction as well as the burying work of the debug instruction into the area of the preceding debug in the hard wear mechanism.
CONSTITUTION: The instruction fetch control part produces the instruction address based on the control signalsupplied from the decoder 2, and then assembles the instruction data read in through the instruction producing circuit 8 to set it to the instruction register 1. Then the instruction counter within the program state word register 9 is replaced via the address replacing circuit 10 and in the case of the normal instruction sequence. Here in the instruction address producing part 7, the operand address of the debug instruction is delivered in the form of the instruction address in the state under which the flag 11 is set with the instruction indicating the debug. And in case these conditions are not satisfied, the instruction address is produced based on the contents of the register 9. Thus a correct debug is possible for the program having a loop.
COPYRIGHT: (C)1981,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10839879A JPS5633742A (en) | 1979-08-25 | 1979-08-25 | Arithmetic processor having debug processing function |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10839879A JPS5633742A (en) | 1979-08-25 | 1979-08-25 | Arithmetic processor having debug processing function |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5633742A true JPS5633742A (en) | 1981-04-04 |
Family
ID=14483738
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10839879A Pending JPS5633742A (en) | 1979-08-25 | 1979-08-25 | Arithmetic processor having debug processing function |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5633742A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS584461A (en) * | 1981-06-30 | 1983-01-11 | Usac Electronics Ind Co Ltd | Program debugging control system |
JPS63223931A (en) * | 1987-03-13 | 1988-09-19 | Fujitsu Ltd | Logic diagram execution route output processing system |
JPS63223928A (en) * | 1987-03-13 | 1988-09-19 | Fujitsu Ltd | Logic diagram debug processing system |
-
1979
- 1979-08-25 JP JP10839879A patent/JPS5633742A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS584461A (en) * | 1981-06-30 | 1983-01-11 | Usac Electronics Ind Co Ltd | Program debugging control system |
JPH0232651B2 (en) * | 1981-06-30 | 1990-07-23 | Pfu Ltd | |
JPS63223931A (en) * | 1987-03-13 | 1988-09-19 | Fujitsu Ltd | Logic diagram execution route output processing system |
JPS63223928A (en) * | 1987-03-13 | 1988-09-19 | Fujitsu Ltd | Logic diagram debug processing system |
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