JPS57130147A - Computer device - Google Patents

Computer device

Info

Publication number
JPS57130147A
JPS57130147A JP1473081A JP1473081A JPS57130147A JP S57130147 A JPS57130147 A JP S57130147A JP 1473081 A JP1473081 A JP 1473081A JP 1473081 A JP1473081 A JP 1473081A JP S57130147 A JPS57130147 A JP S57130147A
Authority
JP
Japan
Prior art keywords
instruction
address
control
instructions
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1473081A
Other languages
Japanese (ja)
Inventor
Shigeru Tamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP1473081A priority Critical patent/JPS57130147A/en
Publication of JPS57130147A publication Critical patent/JPS57130147A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Devices For Executing Special Programs (AREA)

Abstract

PURPOSE:To obtain a device where the order of instructions is changed feely, by providing memories, where micro instructions and macro instructions are stored respectively, and a control generating circuit which can access these memories and determines the address an instruction to be executed next. CONSTITUTION:In respect to memories where micro instructions and macro instructions are stored respectively and a control circuit which determines the address of the next instruction, micro instructions and macro instructions are stored in a control memory 10 and a memory 12 respectively. An address control command is sent from the control memory 10 to a micro control order generating circuit 11 to designate the address of an instruction to be executed next, and this instruction is stored in an instruction register and decoder 13 and is decoded and is outputted as a branch address. Control data is sent from the memory 12 to an operating circuit ALU and a register file 14 to designate a macro instruction to be executed next through a selecting circuit 16, and this instructin is stored in a memory address register 15.
JP1473081A 1981-02-03 1981-02-03 Computer device Pending JPS57130147A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1473081A JPS57130147A (en) 1981-02-03 1981-02-03 Computer device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1473081A JPS57130147A (en) 1981-02-03 1981-02-03 Computer device

Publications (1)

Publication Number Publication Date
JPS57130147A true JPS57130147A (en) 1982-08-12

Family

ID=11869239

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1473081A Pending JPS57130147A (en) 1981-02-03 1981-02-03 Computer device

Country Status (1)

Country Link
JP (1) JPS57130147A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000017760A3 (en) * 1998-09-23 2000-05-25 Massana Research Limited A dsp coprocessor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000017760A3 (en) * 1998-09-23 2000-05-25 Massana Research Limited A dsp coprocessor

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