JPS5614350A - Microprogram control system - Google Patents

Microprogram control system

Info

Publication number
JPS5614350A
JPS5614350A JP8856779A JP8856779A JPS5614350A JP S5614350 A JPS5614350 A JP S5614350A JP 8856779 A JP8856779 A JP 8856779A JP 8856779 A JP8856779 A JP 8856779A JP S5614350 A JPS5614350 A JP S5614350A
Authority
JP
Japan
Prior art keywords
memory
instructions
control memory
control
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8856779A
Other languages
Japanese (ja)
Inventor
Norio Onodera
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP8856779A priority Critical patent/JPS5614350A/en
Publication of JPS5614350A publication Critical patent/JPS5614350A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To utilize merits of vertical instructions and horizontal instructions to perform a high-speed processing as required, by using the first control memory and the second small-capacity control memory and by entering horizontal instructions in the second control memory.
CONSTITUTION: A program dependent upon the operation code and the operand stored in the first control memory 26 is read out by multiplexer gate 23 corresponding to the vertical switching gate and is decoded by instruction register decoder 25, and instructions read on a basis of the command of decoder 25 are transmitted to prescribed circuits selectively. The memory area of memory 26 is provided with an extension instruction area, where addresses of the second control memory 27 are entered, besides the general instruction area, and plural instructions stored in the data file of memory 27 are read out by these addresses and are supplied to gate 23. Horizontal instructions stored in memory 27 are utilized as required to perform the control of the microprogram in a high speed.
COPYRIGHT: (C)1981,JPO&Japio
JP8856779A 1979-07-12 1979-07-12 Microprogram control system Pending JPS5614350A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8856779A JPS5614350A (en) 1979-07-12 1979-07-12 Microprogram control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8856779A JPS5614350A (en) 1979-07-12 1979-07-12 Microprogram control system

Publications (1)

Publication Number Publication Date
JPS5614350A true JPS5614350A (en) 1981-02-12

Family

ID=13946431

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8856779A Pending JPS5614350A (en) 1979-07-12 1979-07-12 Microprogram control system

Country Status (1)

Country Link
JP (1) JPS5614350A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61114341A (en) * 1984-10-01 1986-06-02 バロ−ス・コ−ポレ−シヨン Processing system
JPS63111534A (en) * 1986-10-29 1988-05-16 Mitsubishi Electric Corp Semiconductor integrated circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61114341A (en) * 1984-10-01 1986-06-02 バロ−ス・コ−ポレ−シヨン Processing system
JPS63111534A (en) * 1986-10-29 1988-05-16 Mitsubishi Electric Corp Semiconductor integrated circuit

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