SU849223A1 - Processor with dynamic microprogramme control - Google Patents

Description

(54) PROCESSOR WITH DYNAMIC MICRO-SOFTWARE

one

The invention relates to digital computing and can be used in the design of high-speed emulated computer processors with firmware.

Known processor with firmware control, containing the operating unit, the data block, register and address register 1.

tie}: i, processor ocraTOK - lack of flexibility and versatility, due to static microprogramming.

Also known is a processor with dynamic firmware control, which contains the command register, the operating unit and the control unit NIN 2.

The disadvantage of this processor lies in the low speed.

The closest to the proposed technical entity is a processor containing command and address registers, an operating unit, a branch node, a pulse generator, and a start-stop node C 3

A disadvantage of the known processor is low speed. , MANAGEMENT

2

The purpose of the invention is to increase the speed of the processor.

The goal is achieved by the fact that the processor containing the command register, address register, operating unit, branch unit, pulse generator, AND element, command, processor input is connected to the information input of the register

10 commands, the first bit output of which is connected to the first information input of the address register, the output of which is the output of the processor address, the input of the operands of the processor 15 is connected to the first information input of the operation unit, the first information output of which is connected to the first input of the branch unit impulses connected

20 with the first input of the AND element, the second input of which is the first control input of the processor, the input of the processor address is connected to the second information input of the register

25 addresses, the second information output of the operating unit is the output of the processor's operands, the blocks of the AND elements, the ORI element, the delay element / adders, 30 decoders, the output of the AND element are connected to the first control input of the first adder, the second control input of which connected to the output of the delay element and the first control input of the second adder; the output of the first adder is connected to the second input of the branch unit and the input of the first decoder, the output group of which is connected to the first group of inputs of the blocker ents And, from the first to the n-th, and connected to the first group of inputs of the element AND-OR the second group of inputs of which is connected to the first group of bit outputs of the command register, the second group of bit outputs of which is connected to the second group of inputs of blocks of the elements And , from the first to the n-th, the outputs of which are connected to the input of microcommands of the operation block and the output of microoperations of the processor, the output of the AND-OR element is connected to the second control input of the second adder, the output of which is connected to the input of the second decoder, the group of outputs go is connected to the first group of inputs of the block of elements I, c (p-1) -th to r-th, the second group of inputs of which is connected to the third group of bit outputs of the command register, the outputs of blocks of elements I, (p-I) -th t-th, connected to the third input of the branch unit, the fourth input of which is connected to the second bit output of the command register, the first output of the branch unit connected to the first input of the (n + m + 1) -th block of elements I, the output of which is connected to the third information the input of the address register, the second input (n + m + +1) of the block of elements And is connected to the input by The delay and the output of the 5th block of And elements, the second output of the branch unit are connected to the third control input of the first adder, the third control input of the second adder is connected to the third input of the branch unit.

. In addition, the branch unit contains AND, OR elements and an encoder whose outputs are the outputs of the block, the first input of which is connected to the first input of the encoder, the second input of which is connected to the second input of the block, the third input of which is connected to the inputs of the OR elements, the outputs of which connected to the third input of the encoder, the fourth input of the block is connected to the second inputs of the elements I.

Figure 1 shows the block diagram of the processor; Fig. 2 is a block diagram of a branch node.

The processor contains input 1 processor commands; register of 2 commands with field 3 addresses of the next command, field 4 of the microprogram feature code and field 5 of the microprogram code consisting of fields 6-bg, codes of microcommands, fields 7, -7, marks and fields 8-8 of logical condition codes; blocks of elements And; Element 10 ORI; delay element 11; 12 processor output; input 13 operands pro, processor; an operating unit 14, a second adder 15 and a decoder 16; output 17 of the processor's operands, blocks of 18 18рр И elements, branch block 19 with the first 20, second 21 and third 22 outputs; block of elements 23 AND; input

 24 processor addresses; register 25 .address, output 26 address of the processor; 27 pulse generator; processor control input 28; element 29 And, the first adder 30 and the decoder 31;

5 32 32g inputs, the second decoder and the first inputs 33 33 blocks of elements of elements.

The branch unit 19 (figure 2) contains the elements OR 34 34, the elements

0 And .f and encoder 36.

The processor works as follows.

In the initial state, all the elements of the processor memory are reset. At the entrance

5 24 the starting address is received from the RAM, which is then transferred from the register 25 of the address 25 to the output 26. At this address, the code of the first firmware command code is read from the RAM, which, through input 1, is written to the command register 2. In field 3, the address of the next command is written, which is then transmitted to register 25, in field 4, the code of the microprogram attribute, and in field 5, the microprogram itself, consisting of microinstruction code (field 6 -b), code of labels (field 7, - 7g,) and the code of logical conditions (half -8, „). At the same time, source operands can be fed to inlet 13 from the RAM, which are computed in operational block 14.

After entering the enable signal at input 28, the first clock

5, the pulse from generator 27 passes into the adder 30. As a result, the first output 32 of the decoder 31 is excited and opens the first block of elements I. A microcommand recorded in field b,

Q enters operation block 14, defining its order of operation.

At the same time, the signal from bus 32 is fed to the input of the corresponding group by the input of element 10 AND-OR, allowing information from field 7j to adder 15. If logical conditions are to be checked after the first microcommand, a unit is recorded in field 7, which passes into adder 15. 0 The decoder 16 opens the block of elements 18 And, and the code of logical conditions stored in the field 8 of the register 2, via bus 33 enters the block 19, which checks the values

Claims (3)

1. USSR author's certificate. № 525956, cl. G 06 F 15/20, G 06 F 9/14, 1976. 2, Palagin A.V. Minicomputer Principles of construction and design. Kiev, Naukova Dumka, 1975, p.71, R. 18; 3.Atovi I.O. and Berezkin E.F. Diagnostic procedure of the microprocessor processor. Engineering and mathematical methods in physics and cybernetics, M., Atomizdat, 1977, Issue 6, 0.58, Fig. 1 (prototype). Fig: 2