SU813427A1

SU813427A1 - Microprogramme-control device

Info

Publication number: SU813427A1
Application number: SU782700130A
Authority: SU
Inventors: Виктор Александрович Черепанов; Юрий Михайлович Ожиганов; Александр Иванович Кулик; Алексей Константинович Сосновский
Original assignee: Киевский Научно-Исследовательскийи Конструкторский Институт Пери-Ферийного Оборудования
Priority date: 1978-12-18
Filing date: 1978-12-18
Publication date: 1981-03-15

Description

(54) МИКРОПРОГРАММНОЕ УСТРОЙСТВО УПРАВЛЕНИЯ(54) FIRMWARE CONTROL DEVICE

II

Изобретение относитс к вычислительной технике, в частности к микропрограммным устройствам управлени .The invention relates to computing, in particular, to firmware control devices.

Известно микропрограммное устройство управлени , содержащее запоминающие блоки , регистры микрокоманд, регистры адреса, блоки проверки условий, триггеры блокировки , схемы И |1 .A firmware control device is known that contains memory blocks, microinstruction registers, address registers, condition checkers, blocking triggers, AND circuits | 1.

Наиболее близким к предлагаемому по технической сущности и достигаемому результату вл етс микропрограммное устройство управлени , содержащее блок пам ти микрокоманд, регистр микрокоманд, регистр адреса микрокоманд, узел формировани адреса и коммутатор, причем, первый вход узла формировани адреса соединен со входом устройства, первый выход узла формировани адреса соединен с первым адресным входом регистра адреса микрокоманд , выход которого соединен со входом блока пам ти микрокоманд, выход которого соединен с информационным входом регистра микрокоманд, выход которого соединен с первым входом коммутатора Е.The closest to the proposed technical essence and the achieved result is a microprogram control device containing a microinstruction memory block, a microinstruction register, an microinstruction address register, an address generation node and a switch, the first input of the address formation node being connected to the device input, the first output of the node the address generation is connected to the first address input of the micro-instruction address register, the output of which is connected to the input of the micro-instructions memory block, the output of which is connected to the information the register of microinstructions, the output of which is connected to the first input of the switch E.

Недостатком известных способов вл етс отсутствие возможности микропрограммной организации временных задержек иA disadvantage of the known methods is the inability of the firmware to organize time delays and

временного отсчета отсутстви логического услови при реализации режима ожидани . Цель изобретени - расщирение функциональных возможностей за счет осуществлени микропрограммной организацииthe time count of the absence of a logical condition when implementing the standby mode. The purpose of the invention is to extend the functionality by implementing a microprogram organization.

временных задержек.time delays.

Поставленна цель достигаетс тем, что в устройство введен счетчик, выход которого соединен со вторыми входами коммутатора и узла формировани адреса, первый вход счетчика соединен со входом устройства,The goal is achieved by introducing a counter into the device, the output of which is connected to the second inputs of the switch and the address generation node, the first input of the counter is connected to the input of the device,

второй выход узла формировани адреса соединен со вторым управл ющим входом регистра адреса микрокоманд и с управл ющим входом регистра микрокоманд, а выход коммутатора ео счетным входом регистра адреса микрокоманды, второй вход счетчика и третий вход узла формировани адреса соединены с выходом блока пам ти микрокоманд.The second output of the address generation node is connected to the second control input of the microinstruction address register and the control input of the microinstruction register, and the output of the switch is located at the counting input of the microcommand address register, the second counter input and the third input of the microinstruction memory block.

На чертеже представлена блок-схема устройства .The drawing shows the block diagram of the device.

Claims

The block diagram of the device contains a block of 1 memory of micro-commands, a register of 2 micro-commands, a register 3 of the address of the micro-command, an address generation unit 4, a switch 5, a counter 6. The device operates as follows. If a microcommand in which the standby mode is set is read in the current cycle of the firmware control device, the code in the microcommand register 2 functional selection field indicates the logical condition that is necessary to go to the next microcommand, i.e., leave the standby mode. It is fed to the input of the switch 5. When executing micro-commands, besides the micro-command of an unconditional go-go and micro-command of conditional branching under a logical condition, until the logical condition necessary for the transition to the next micro-command appears, a single signal is generated at the output of the switch 5, which allows before executing the current microcommand, forming the address of the next microcommand by increasing by one the current address of the microcommand. If the microcommand "pending" is executed, then the address changes in the absence of a logical condition does not occur, the information is blocked in the register of microinstructions, but in each microprogrammed cycle in the fourth cycle, one is added to the code 6 in the code that was previously entered before the microinstructions "Micro-wait" download counter. The entered code is used to form a time reference for the permissible absence of a logical condition when the duration of the firmware cycle is known. If during the execution of a microcommand "wait, the presence of a logical condition is detected, then the appearance of a zero signal at the output of switch 5 permits the formation of the address of the next microcommand by entering the lower-order address from the cell whose address follows the address of the microcommand" wait. In the absence of a logical condition and the occurrence of a signal, the counter overflows, the output of the counter 6 at the address generation node 4 increases the address of the next microcommand by one more time. The cell with the address increased by two with respect to the microcommand "wait" address is the initial address of the subprogram for handling the alarm situation, i.e., the device may "hang" if there is a long (more than acceptable) absence of a logical condition. If necessary, the microprogram organization of the time delay in the field of functional sampling of the microcommand "wait" is specified by the code of the signal condition and the completion of the counter. Before executing the microcommand "wait" in counter 6, the code corresponding to the required time delay is recorded by a microcommand load of the counter. When executing the microCommand "Auger", every time in the fourth cycle of the firmware cycle, one is added to the counter 6. Therefore, the appearance of the signal “overflow of the counter means the end of the time delay causes the appearance of a zero signal at the output of switch 5, which allows parallel loading of the lower address bits of the next microcommand from the cell following the microcommand wait. Using the microcommand “wait and using a counter for organizing internal and external microprogram cycles, you can create practically different lengths of time delays of greater accuracy. The present invention allows obtaining substantial gains in equipment for devices in which there is a need to form various time delays and a time reference without the logical condition. In addition, in the designed device, the counter is used to convert the serial code of information into parallel and vice versa, to form firmware cycles. This increases the accuracy of setting the time delays, reduces the size, increases reliability. Claims of Invention A firmware control device containing an address generation node. The first input of which is an input device, the first output of the address generation node is connected to the first address input of the micro-command address register, the output of which is connected to the input of the micro-command memory unit, the output of which is connected to the information input of the micro-command register, the output of which is connected to the first input of the switch, characterized in that, in order to expand the functionality due to the implementation of the microprogram organization of time delays, a counter is inserted in it, the output of which is connected to the second inputs Dami switch and node address formation, the first input of the counter is connected to the input of the device. The second output of the address generation node is connected to the second control input of the microinstructor address register and the control input of the microinstructions register, the switch output is connected to the counting input of the microinstruction address register, the second counter input and the third input of the address generation block of the microcommands, Sources information taken into account during the examination 1. USSR Author's Certificate No. 437072, cl. G 06 F 9/22, 1972.

2. USSR author's certificate No. 467350, cl. G 06 F 9/22, 1973 (prototype).

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