SU467350A1 - Firmware Control - Google Patents

Description

(54) FIRMWARE CONTROL DEVICE

one

The invention relates to computing and can be used in control devices of digital computers.

A microprogrammed control device is known that contains a microinstructions memory block, a microinstructions register, an microcommands address register, an address generation unit and a selection circuit, the first input of the address generation unit is connected to the device input, the output of the address generating unit register, the output of which connected to the input of the microinstructions memory unit, the output of which is connected to the first inputs of the register of microinstructions, the first output of which is connected to the second input of the address generation node, and The swarm output is connected to the input of the selection circuit.

A disadvantage of the known device is a slowdown in the implementation of the standby mode.

The aim of the invention is to improve the speed of the device.

The goal is achieved by the fact that the device finally contains a delay element, the input of which is connected to the output of the selection circuit, and the output to the second and third inputs of the microinstruction register and to the second input of the microinstruction address register.

A schematic of the device is shown in the drawing, where 1 is a microcommand memory block; 2 - register of microinstructions; 3 - microcommand address register; 4 - address generation node; 5 - selection scheme; 6 - the delay element. The device works as follows. If in the current cycle of the firmware control device a micro-command is read in which the standby mode is set,

then the code in the standby field of register 2 micro-instructions indicates a logical condition, and the presence of which is necessary for non-transition to the next micro-command, i.e., to exit the standby mode. It is fed to the input of the selection circuit 5. Until the logical condition necessary for the transition to the next microinstruction has appeared, the output of the selection circuit 5 produces a signal that, after a period of time determined by the element

delays 6, prohibits the receipt of 2 micro-instructions in the register and the addresses of micro-commands in register 3. The same signal arriving at the second input of register 2 sets the operation field of the latter to zero. The signal produced by the selection circuit is delayed by a delay element 6 by the time required for the current microcommand to be executed. In this case, the node 4 of the formation of the address of the micro-command produces the address of the following

microinstructions This newly formed ad, arriving at the first input of the register 3 microcommand addresses, is stored in it. After that, the signal from the output of the delay element prohibits the reception of new information.

Thus, all the time, as long as there is no logical condition for the transition to the next micro-command, the micro-command waiting field of the 3 micro-command address register remains unchanged, and the micro-command register 2 operational field is at the zero state. In each cycle, the next micro-instruction will be read from the micro-instruction memory block, whose address is stored on register 3 of the micro-instruction addresses, but this micro-instruction will not be accepted into the micro-command register 2 until the expected logical condition occurs. Since the operational field of the micro-command register is set to zero, no action is taken in devices controlled by the firmware control device.

When a logical condition occurs, the lock is removed from the register of 2 microinstructions and from the register 3 of the address of microinstructions. In register 2 of the micro-instruction memory block, the next micro-instruction is accepted, the address of which was stored in register 3. If a code in the waiting field of the micro-instruction indicates that there is no need for waiting in this micro-command (for example, all zeros), the selection circuit produces a signal permitting the reception in the register of 2 micro-instructions and

register 3 microcommand addresses. Further, in accordance with the address formed in the microcommand address generation unit 4, the next microinstruction is selected, which is stored in the register of 2 microcommands. Further operation of the firmware control unit is repeated in the described sequence.

Subject invention

A firmware control device containing a microcommand memory block. the microinstructions register, the microinstructions address register, the address generation node and the selection circuit, the first input of the address generation node is connected to the device input, the output of the address formation node is connected to the first input of the microinstruction address register,

the output of which is connected to the input of the microinstructions memory unit, the output of which is connected to the first input of the register of microinstructions, the first input of which is connected to the second input of the address generation node, and the second output is connected to the input of the selection circuit, which is designed to improve the speed of the device , it additionally contains a delay element, the input of which is connected to the output of the selection circuit, and

output - to the second and third inputs of the register of microinstructions and to the second input of the register of the address of microinstructions.