SU792252A1 - Microprogramme control system - Google Patents

Description

(54) MICROPROGRAM CONTROL SYSTEM

The invention relates to computer technology, in particular, to firmware control devices, and can be used in the construction of digital computers and controllers with firmware control. A firmware control unit l is known, which contains a memory block, registers, information receiving circuits, a pulse generator, a clock count, AND, NOT elements, decoders, a driver of addresses of microprogram words. The complexity of such a device is due to a large number of different types of equipment. The closest to the invention in technical essence and achievable result is the firmware control system 2, which contains the address and control memory of micro-instructions, the instruction memory, arithmetic logic unit, input-output interface, pulse generator, command address memory register ,. register of conditions, node laziness of logical conditions. However, such a device requires a large amount of equipment and a significant increase in the volume of the address memory of microinstructions in the event of an increase in the number of branchings of microprograms. The purpose of the invention is to reduce equipment. This goal is achieved by the fact that the firmware control system containing a pulse generator, the first output of which is connected to the command memory control inputs, the address and control microcommand memory, the first output address memory of the microcommands is connected to the address input of the address memory register microinstructions, the output of the instruction memory is connected to the information input of the microinstructions memory address register, the bit output of which is connected to the address input of the microinstructions control memory, the output of which is connected to the memory input and the input of the arithmetic unit, and the input of the pulse generator is the input of the device, contains a combinational adder and transition constants. At the same time, the output of the logical conditions of the arithmetic logic unit is connected to the input of the logical conditions of the memory of the transition constants, the control input of which is connected to the second output of the pulse generator, and the output of the memory of the transition constants to the input of the transition constants of the combinational adder, whose address input is connected the bit output of the microcommand memory address register. The output of the combinational adder is connected to the input of the address memory of micro-instructions, the second output of which is connected with the address input of the memory of transition constants,

The block diagram of the firmware is shown in the drawing,

The firmware control system contains an address memory of 1 micro-commands, a register 2 microcommand memory addresses, a control memory of 3 micro-commands, an arithmetic-logical device 4, a pulse generator 5, a memory of 6 commands, a coibination adder 7, a memory of 8 transition constants

The address memory 1 of the micro-instructions contains the address micro-instructions, the format of which includes a maximum of the micro-instructions of the control memory of 3 micro-instructions and the second group of memory addresses 8 transition constants. The micro-instruction memory address register 2 provides the micro-command address of the micro-command control memory 3 of the micro-instructions, which is also used in the combinational adder 7 to produce the next address of the micro-instruction address memory 1. The control memory of 3 micro-commands contains a set of various control micro-commands for specifying the operating modes of the memory 6 of commands and the arithmetic logic unit 4.

The logical conditions generated by the arithmetic logic unit are used as the first group of memory addresses of 8 transition constants.

The device works as follows.

In each cycle specified by the pulse generator 5, the current address microcommand is read from the address memory 1 of the micro-instructions. The address microcode part is used to address the memory of 8 transition constants. The other part is entered into register 2 of the micro-instruction memory addresses, which determines the control memory address of the 3 micro-instructions. The same address is fed to the first input of the combinational adder 7 to determine the next address of the address memory of 1 micro-instructions. A microcommand, read from the memory management of 3 microcommands, is served on. The input of the arithmetic logic unit 4, which, when performing operations, forms logical conditions, is shown by the first group of memory addresses of 8 transition constants. If there is no branch in the firmware

The address of the next microcommand of the microcommand address memory is determined by the contents of the microcommand memory address register, since the transition constant in this case is 0. The address of the next microcommand in the case of firmware branching is determined by adding the memory address register. microinstructions and transition constants ,. read from the memory of transition constants.

The presence in the composition of this device, the combinational adder and the memory of the transition constants makes it possible to exclude additional control schemes for the address memory of micro-instructions, which ensures a reduction in the number of equipment, while the exclusion of repeated micro-instructions leads to a decrease in the memory size of the micro-instructions.

Claims (2)

1. Authors certificate of the USSR (416696, class G 06 F 9/16, 1974. 2. US Patent No. 4..038.643, 45 cl. G 06 F 9/16, 1977 (prototype).