SU1259249A1 - Sequential adder of codes with irrational bases - Google Patents

Abstract

The invention relates to the field of computer technology and can be used to add and subtract multiple bits of consecutive codes with irrational bases. A sequential adder containing a block for generating additional signals and a sum signal and a register, with the purpose of distributing functionality due to the possibility of performing the operation of subtracting numbers represented by codes with irrational bases, is introduced a block for the formation of sign signals. Expansion of functionality is achieved by taking into account the signs of the operands and forming the sign of the operation in the block of forming sign signals and consists in the possibility of algebraic addition of operands, i.e. addition taking into account their signs, whereas in the known adders only arithmetic addition is made, 1 s.p. f-ly, 2 silt, 2 tab. (L с: 1C СП; о

Description

The invention relates to computing and can be used to sum and subtract multi-digit serial codes with irrational bases.

The purpose of the invention is to expand the functionality by allowing the operation to subtract numbers represented by codes with irrational bases.

FIG. 1 shows a block diagram of a sequential code adder with irrational bases j in FIG. 2 is a functional block diagram of the formation of sign signals.

The adder contains a block 1 of forming additional signals and a sum signal, a register 2, a block 3 of forming sign signals, an element NOT 3.1, elements AND 3.2 and 3.3, an element ШШ 3.4 and an element EXCLUSIVE OR 3.5, an input 4 of the setting, a clock 5, inputs 6 and 7 sign bits of the first and second terms, respectively, inputs 8 and 9 of the significant bits of the first and second terms, respectively, outputs 10–15 of the register, address inputs 16–21 of the auxiliary signal generation unit, input 22 of the sign of the auxiliary signal generation unit fishing, the first and second

five

0

five

0

outputs 23 and 4 of the block of forming sign signals, input 25 of the sign of the result of the current register operation, output 26 of the sign of the result of the sequential adder, outputs 27-32 of the block of formation of additional signals and the sum signal, information inputs 33-38 of the register, control input 39 of the block of formation of sign signals and output 40 result.

I The device works as follows.

When a single signal arrives at the device 4 input, register 2 is set to the zero state. The arrival of signals at inputs 6 and 7 characters of the operands, the block 3 of the formation of sign signals forms the sign of addition or subtraction operations.

The arrival of operands starts at the higher bits. When signals arrive at inputs 8 and 9 of operands, at inputs 16-21 of signals from outputs 10-15 of register 2, to input 22 of signal from output 23 of block 3, the formation of sign signals signals block 1 of forming additional signals depending on the code at inputs 16, 17, 18, 19, 20, 21, 22, 9 and 8 forms a code at the outputs 27, 28, 29, 30, 31, 32 and 40 in accordance with the table. one.

Table 1

Continued table. one

Continued tabl ... 1

eight

Continued table. one

1259249

TO)

Continued table.

The unit 1 for generating additional signals can be implemented by one of the limestone methods, for example, on an EPROM. The code from the outputs. 27-32 of the block 1 of forming additional signals is fed to the input 34-38 of register 2. From the output 24 of the block 3 of the formation of sign signals, the signal is fed to the input 25 of register 2, When a single signal arrives at the clock input 5 of register 2 the code is written to the register. The signal from the output 15 of the register 2 is fed to the input 39 of the block 3 of forming signal signs, where the signal of the sign of the result of the operation is formed in accordance with the table. 2. The code from the outputs 10-15 of the register 2 enters the I-do 16-2

Inputs of block 3 О О 1

block 1 forming additional signals, etc.

-Table 2

lo

ABOUT

lo

about

Bx o o

 ABOUT

 55

Inputs OO 1

ABOUT

lo

about

Note.

If the number represented by the code with an irrational basis is greater than or equal to O, then O is recorded in the sign bit of the code, otherwise - 1, If X, Y, then HB O, Zn.5 :. Zn Xi X Y, then HB 1, Zn I Zn Y. The sign of the addition operation is O, subtraction - 1.

. Thus, in each clock cycle, the signals of the operands are added (subtracted) with additional signals that are delayed by one clock. The block 1 for generating additional signals generates the result signals and additional signals for the next clock cycle.

Circuits for propagation of transfer to higher and lower bits are similar to the known device.

Claims (2)

1. A sequential code adder with irrational bases, containing a block for generating additional signals and a sum signal and a register, the first, second, third, fourth and fifth outputs of the code for additional signals of the block for generating additional signals and a sum signal are connected respectively to the first, second, third , fourth and fifth informational inputs of the register, first, second, third, fourth and fifth outputs to second, respectively, connected to the first, second, third, fourth, and fifth address inputs of the additional signal generation unit and sum signal; the register setup input is connected to the serial adder installation input; the register clock input is connected to the serial adder input, the output signal of the additional signal generation unit and the sum signal is the output of the resultant sequential adder. different In order to expand the functionality due to the possibility of performing the operation of subtracting numbers represented by codes with irrational bases, the block of formation of sign signals, the first and second information inputs of which are connected to the inputs of sign bits of the first and second the operands of the serial adder, the sixth output of the register is connected to the sixth address input of the block for generating additional signals and the sum signal and with control by the input of the block forming sign signals. The first output of which is connected to the input of the operation sign of the additional signal generation unit and the sum signal, and the second output to the input sign of the result of the current register operation, the sixth information input of which is connected to the sixth output of the additional signal code of the additional signal generation unit and the sum signal, the seventh and eighth the address inputs of which are connected to the inputs of the significant bits of the first and second operands of the sequential adder, respectively, the seventh register output is the output of a serial adder result. 2. The adder according to claim 1, characterized in that the block forming the sign signals contains two elements AND, the element OR, the element EXCLUSIVE OR, the element NOT, the control input of the block is connected to the input of the element NOT and to the first input of the first element AND the output of which is connected with the first input of the OR element, the output of which is the output of bdju21 ka, the second input of the element OR is connected to the output of the second element AND, / whose first input is connected to the output of the element NOT, and its second input is connected to the first input of the element SPARKLING OR and is the input L. Fig .. 2 Editor O. Yurkovetska Compiled by M.Esenina Tehred I.Popovich Order 5122/46 Tirak 671. Subscription VNIIPI USSR State Committee for inventions and discoveries. 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, Projecto st., 4 49 22 the sign bit of the first operand of the block, the input of the sign bit of the second operand of the block is connected to the second input of the first AND element and to the second input of the EXCLUSIVE OR element, the output of which is the output of the block. J Proofreader M. Maksimishinets