SU1298739A1 - Device for shifting operands - Google Patents

Abstract

The invention relates to computing and can be used in high-performance information processing systems. The aim of the invention is to enhance the functionality by performing arithmetic and cyclic shifts. This goal is achieved due to the fact that the device containing node I of one-sided shifts, converter 2 direct code to an additional code, switch 4 and block 5 of elements I, contain node 3 decryption with appropriate connections. 4 il. i (L s: 1/7 Figure 1

Description

The invention relates to the field of computing and can be used in high-performance information processing systems.

The aim of the invention is to enhance the functionality by performing arithmetic and cyclic shifts.

FIG. 1 shows a block diagram of a device for shifting the operand; in fig. 2 - functional diagram of the one-way shifts node with the number of bits equal to eight; in fig. 3 is a diagram of a direct code to additional code converter; in fig. 4 - a functional decoding node scheme.

The device for shifting operands (FIG. 1) contains a node 1 for one-sided shifts, a direct code-to-additional code converter 2, a decryption node 3, switch A, a block of 5 And elements, an input 6 of the device sign, information input 7 of the device, input 8 device shift, outputs 9-12 of decoding node 3, informational and mation inputs 13 and 14 of node 1 for one-sided shifts, input 15 for the device shift, input 16 for the shift for node 1 for one-side shifts for device 17.

Site 1 one-way shifts (figure 2) contains multiplexers 18.

Converter 2 direct code to

the additional code (FIG. 3) contains groups 19 and 20 of the EXCLUSIVE OR elements, a group of 21 elements I. The decryption node 3 (FIG, 4) contains the element NOT 22, the element AND-NO 23, the element OR 24,: the element NOT 25, the elements And 26.27.

The numbers above the inputs (outputs) indicate the number of bits.

The node 1 for one-way shifts is one-assigned to perform one-way shifts for the right of the codes set at input 14. The bits of the code set at input 13 are pushed into the bits to be released. At the input 16, the code for the value of the shift is transmitted to all control inputs multiplexers 18. A shifted code is generated at output 17.

Converter .2 is intended for

converting the direct code set at input 15 into an additional code when generating a single signal at output 12.

five

 About 5

20

25

35

0

g „

55

When installed at the output 12 of the logical zero, the code from the input 15 is transited to the output.

Decoding node 3 is designed to decipher the type of shift code set at input 8, taking into account the code of the shift value at input 15, and generate control signals at outputs 9-12 with the following shift type codes set at bits 0 / 2J of input 8 ; 001 - right shift logical (PL); 011 (010) - left shift logical

(LL); 00 - arithmetic right shift

(PA);

110 - cyclic left shift (LC); 100 - right shift cyclical (PC).

The switch 4 is designed to transmit to input 13 of node 1 either a code from input 7 (without taking into account the leftmost bit), or a sign code from input 6 to all output bits, or to form a zero code at input 13 of the node.

At the same time, if a logical unit is set at the output 11, then a zero code is formed at the output of the switch 4, regardless of the signal value at the output 10. If a logical zero is set at the output 11, then at the output 10 of the logical unit for all bits of the input 13, the sign code is transmitted from input 6. When the logical zero is set at output 10, the code from input 7 is transmitted to input 13.

The device for shifting the operands operates as follows.

The initial state of the device can be arbitrary. To implement the shift at the input 7 of the device, set the code of the shifted operand, at the input 6 set the sign code of the operand (for the arithmetic shift, to the right). Input 8 sets the shift type code. The device provides the following types of shifts and the corresponding codes: right shift logical (Ш1); left shift logical (LL); Arithmetic right shift (PA); left shift cyclical (LC); right shift cyclical (PC).

At input 15, the shift magnitude code is established.

At output 17, a shifted operand code is generated.

Let us consider in more detail the operation of the device for each type of shift by an amount not equal to zero, i.e with input codes of 15, other than zero. For any type of shift in node 1, one-sided shifts to the right of the code set at input 14 are performed by pushing the code set at input 13 to the bits of the code set at input 13. When the shift to the right, the code 11 is set to 11. Therefore , a zero code is formed at the input 13. The code from the input 15 is transmitted to the input 16 of node 1, since the output

12 is set to a logical zero. The code from input 7 is transited to input 1A, since a logical unit is established at output 9. In node 1, the code set at input 14 is shifted to the right by the value specified by code at input 15.

A logical zero is pushed into the bits to be released, since at the input

13 formed a zero code. At output 17, a logical right-shifted code is generated.

The arithmetic (PA) is shifted to the right in the same way, with the difference that the sign value is pushed into the discharged bits in the node 1. All digits of input 13 are set to the character from input 6 of the device, since code 10 is set at outputs 10 and 11.

The cyclic right shift is performed in the same way, with the difference that the bits of the code set at input 7 are inserted into the discharged bits in node 1. This code (without the leftmost bit) is transmitted to input 13 of node 1, so as on outputs 10 and 11, code 00 is set.

When shifting to the left logical (PL) code 00 is set at outputs 10 and 11. The code from input 7 of the device is transmitted to input 13 of node 1 (without the leftmost bit). A zero code is generated at input 14, since a logical zero is set at output 9. An additional code is established at the input 16 from the code set at the input 15, since a logical unit is established at the output 12. In node 1, the zero code set at input 14 is shifted to the right by an amount.

determined by an additional code from a given code of the shift value at input 15. The bits of the shifted code are moved into the discharged bits in node 1, starting with the rightmost bit, since this code is set at input 13 of node 1. As a result, at device 17 the operand code shifted logically to the left is generated.

Similarly, the left-hand cyclic shift is performed, with the difference that signals will be transmitted to the rightmost bits of the shifted code.

(bits) of the leftmost bits of the shifted code, as it is transmitted from input 7 to input 14. At output 9, a logical unit is set and in node 1 the value is shifted to the right by an amount equal to the additional code of the value at the input 15 of the device.

With a zero code, the magnitude of the shift at the input 15 of the device at the input 16

Node 1 also sets a zero code. Node 1 is zero offset. The output 9 of node 3 is set to a logical unit regardless of the code at input 8. As a result, the code from input 7 is transited to the output 17 of the device, which is required for zero shifts.

Claims (1)

Invention Formula A device for shifting operands containing a one-way offset node; a forward code converter & In the additional code, the switch and the block of elements AND, the information input of the device is connected to the information input of the block of elements AND, the bits, besides the senior information input of the device, are connected respectively to the bits of the first information input of the switch, the second information input of which input device sign, the switch output is connected to the first information input of the node - single The third shifts, the output of which is the output of the device, the input of the shift value of the device is connected to the information input of the direct code converter and the additional code whose output is connected to the input of the shift value of the one-way shift node, characterized in - Fully 1 and arithmetic and cyclic shifts, it contains a depthreflation unit, and the bits of the inputs of the shift type and the shift values of the device are connected respectively to the input bits of the decryption node, The first, second, third and fourth outputs of which are connected respectively to the control input of the H element block, with the first and second control inputs of the switch, with the resolution input of the direct code to additional code converter, the output of the AND block of the elements is connected to the second information input of the one-shift offset node. n: 20 IS Editor N. Egorova Order 890/51 fl uz, 4 Compiled by A. Klyuev Tehred M. Khodanych Proofreader A. Zimokoso in Circulation 673 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., d. A / 5 ABOUT Y; IN DS; W% Y ;; O: P; ™ G ;;; Y ;; SC; GP ;; SDRIAT UZHGOROD, ul. Design .4 sixteen FIG 3