JPS5599666A - 2-dimensional memory device - Google Patents

2-dimensional memory device

Info

Publication number
JPS5599666A
JPS5599666A JP780579A JP780579A JPS5599666A JP S5599666 A JPS5599666 A JP S5599666A JP 780579 A JP780579 A JP 780579A JP 780579 A JP780579 A JP 780579A JP S5599666 A JPS5599666 A JP S5599666A
Authority
JP
Japan
Prior art keywords
bit
simultaneous
memory device
address register
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP780579A
Other languages
Japanese (ja)
Inventor
Junnosuke Kutsuzawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Japan Broadcasting Corp
Original Assignee
Nippon Hoso Kyokai NHK
Japan Broadcasting Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Hoso Kyokai NHK, Japan Broadcasting Corp filed Critical Nippon Hoso Kyokai NHK
Priority to JP780579A priority Critical patent/JPS5599666A/en
Publication of JPS5599666A publication Critical patent/JPS5599666A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To simplify the circuit constitution of the 2-dimensional memory device by using the memory element which can give the simultaneous access to the S bit per word.
CONSTITUTION: Memory elements 60 composed of each word S bit of N units in all plus the R words are arrayed in the 2-dimensional way to enable the I-bit (I≥S) simultaneous access. Then the selection signal is supplied to element 60 from X address register 10, Y address register 20 via line decoder 30, row decoder 40 and intra-element address register 50 each. And if access mode 1 is designated to access mode line 3, the simultaneous and parallel input/output is given to the data of I-bit. While the J-bit data featuring S≤J≤I is supplied and delivered with designation of access mode 2. Also with installation of the j-bit serial-parallel register to recorder 40, the simultaneous and parallel input/output is possible for the data of J×J bits. Thus the circuit constitution can be simplified for the 2-dimensional memory device.
COPYRIGHT: (C)1980,JPO&Japio
JP780579A 1979-01-26 1979-01-26 2-dimensional memory device Pending JPS5599666A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP780579A JPS5599666A (en) 1979-01-26 1979-01-26 2-dimensional memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP780579A JPS5599666A (en) 1979-01-26 1979-01-26 2-dimensional memory device

Publications (1)

Publication Number Publication Date
JPS5599666A true JPS5599666A (en) 1980-07-29

Family

ID=11675829

Family Applications (1)

Application Number Title Priority Date Filing Date
JP780579A Pending JPS5599666A (en) 1979-01-26 1979-01-26 2-dimensional memory device

Country Status (1)

Country Link
JP (1) JPS5599666A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05124672A (en) * 1991-06-25 1993-05-21 Nikka Micron Kk Liquid supply apparatus

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05124672A (en) * 1991-06-25 1993-05-21 Nikka Micron Kk Liquid supply apparatus

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