JPS5658195A - 2-level rom integrated circuit - Google Patents

2-level rom integrated circuit

Info

Publication number
JPS5658195A
JPS5658195A JP13383779A JP13383779A JPS5658195A JP S5658195 A JPS5658195 A JP S5658195A JP 13383779 A JP13383779 A JP 13383779A JP 13383779 A JP13383779 A JP 13383779A JP S5658195 A JPS5658195 A JP S5658195A
Authority
JP
Japan
Prior art keywords
rom
buffer memory
segments
register
array
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13383779A
Other languages
Japanese (ja)
Inventor
Masahiro Mikami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Suwa Seikosha KK
Original Assignee
Seiko Epson Corp
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Suwa Seikosha KK filed Critical Seiko Epson Corp
Priority to JP13383779A priority Critical patent/JPS5658195A/en
Publication of JPS5658195A publication Critical patent/JPS5658195A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/18—Auxiliary circuits, e.g. for writing into memory

Landscapes

  • Read Only Memory (AREA)

Abstract

PURPOSE:To increase the bit ratio of the memory access, by forming the buffer memory into two segments in the ROM semiconductor circuit which contains both the ROM and the buffer memory on the same chip. CONSTITUTION:The buffer memory which stores temporarily the data given from the ROM array 22 consists of two segments 25 and 26. The raw of the ROM array is applied to the raw address decoder 20 from the address register 18, and the data of the array 22 is written into the segments 25 and 26 of the buffer memory. In this case, the raw address is held at the register 18. As a result, the next row address input 16 is compared with the data of the register 18 through the control circuit 36, and if a coincidence is obtained, the reading can be eliminated for the ROM array. Thus the column address input 35 receives the decoding 35 and multiplexing 29, and the data given from the segment 27 is taken into the output buffer.
JP13383779A 1979-10-17 1979-10-17 2-level rom integrated circuit Pending JPS5658195A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13383779A JPS5658195A (en) 1979-10-17 1979-10-17 2-level rom integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13383779A JPS5658195A (en) 1979-10-17 1979-10-17 2-level rom integrated circuit

Publications (1)

Publication Number Publication Date
JPS5658195A true JPS5658195A (en) 1981-05-21

Family

ID=15114193

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13383779A Pending JPS5658195A (en) 1979-10-17 1979-10-17 2-level rom integrated circuit

Country Status (1)

Country Link
JP (1) JPS5658195A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52100941A (en) * 1975-12-31 1977-08-24 Olivetti & Co Spa Device for addressing memory

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52100941A (en) * 1975-12-31 1977-08-24 Olivetti & Co Spa Device for addressing memory

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