EP0093954A3 - Image display memory unit - Google Patents

Image display memory unit Download PDF

Info

Publication number
EP0093954A3
EP0093954A3 EP83104112A EP83104112A EP0093954A3 EP 0093954 A3 EP0093954 A3 EP 0093954A3 EP 83104112 A EP83104112 A EP 83104112A EP 83104112 A EP83104112 A EP 83104112A EP 0093954 A3 EP0093954 A3 EP 0093954A3
Authority
EP
European Patent Office
Prior art keywords
display memory
memory chip
image display
memory unit
selecting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP83104112A
Other languages
German (de)
French (fr)
Other versions
EP0093954A2 (en
Inventor
Tetsuya Ikeda
Shigeru Komatsu
Shigeru Hirahata
Tokuo Koyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Publication of EP0093954A2 publication Critical patent/EP0093954A2/en
Publication of EP0093954A3 publication Critical patent/EP0093954A3/en
Withdrawn legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/02Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the way in which colour is displayed
    • G09G5/022Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the way in which colour is displayed using memory planes

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Digital Computer Display Output (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Image Generation (AREA)

Abstract

An image display memory unit having a plurality of display memories (6, 7, 8) connected to a plurality of data lines of data bus (3) one for each display memory chip and addressable for each bit of the data bus comprises a display memory chip selection circuit (13) for selecting the display memory chip for each data bit on the same address, and a write control circuit (16, 17, 18) for controlling writing for each display memory. The dot-by-dot coloring is attained only by a software processing of controlling write informa­ tion for each display memory and selecting the display memory chip.
EP83104112A 1982-04-28 1983-04-27 Image display memory unit Withdrawn EP0093954A3 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP70373/82 1982-04-28
JP57070373A JPS58187996A (en) 1982-04-28 1982-04-28 Display memory circuit

Publications (2)

Publication Number Publication Date
EP0093954A2 EP0093954A2 (en) 1983-11-16
EP0093954A3 true EP0093954A3 (en) 1984-10-03

Family

ID=13429569

Family Applications (1)

Application Number Title Priority Date Filing Date
EP83104112A Withdrawn EP0093954A3 (en) 1982-04-28 1983-04-27 Image display memory unit

Country Status (2)

Country Link
EP (1) EP0093954A3 (en)
JP (1) JPS58187996A (en)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6067989A (en) * 1983-09-26 1985-04-18 株式会社日立製作所 Image display circuit
JPS617882A (en) * 1984-06-21 1986-01-14 富士通テン株式会社 Video memory writing unit for display
US4635049A (en) * 1984-06-27 1987-01-06 Tektronix, Inc. Apparatus for presenting image information for display graphically
DE3588174T2 (en) * 1984-07-23 1998-06-10 Texas Instruments Inc Video system
JPS6142643U (en) * 1984-08-24 1986-03-19 日本電気株式会社 Multiple memory simultaneous update mechanism
JPS6162095A (en) * 1984-09-03 1986-03-29 富士通株式会社 Linear display controller
US4742474A (en) * 1985-04-05 1988-05-03 Tektronix, Inc. Variable access frame buffer memory
GB8614876D0 (en) * 1986-06-18 1986-07-23 Rca Corp Display processors
JPS6424565A (en) * 1987-07-20 1989-01-26 Sharp Kk System for storing plural kinds of picture data
US5241658A (en) * 1990-08-21 1993-08-31 Apple Computer, Inc. Apparatus for storing information in and deriving information from a frame buffer
GB2261803B (en) * 1991-10-18 1995-10-11 Quantel Ltd An image processing system

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4016544A (en) * 1974-06-20 1977-04-05 Tokyo Broadcasting System Inc. Memory write-in control system for color graphic display

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4016544A (en) * 1974-06-20 1977-04-05 Tokyo Broadcasting System Inc. Memory write-in control system for color graphic display

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
HEWLETT-PCKARD JOURNAL, vol. 31, no. 12, December 1980, pages 25-32, Amstelveen, NL; H.L. BAEVERSTAD et al.: "Display system designed for color graphics" *

Also Published As

Publication number Publication date
JPS58187996A (en) 1983-11-02
EP0093954A2 (en) 1983-11-16

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Legal Events

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Withdrawal date: 19870615

RIN1 Information on inventor provided before grant (corrected)

Inventor name: IKEDA, TETSUYA

Inventor name: KOMATSU, SHIGERU

Inventor name: HIRAHATA, SHIGERU

Inventor name: KOYAMA, TOKUO