JPS617882A - Video memory writing unit for display - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a video memory writer for writing still image information into a plurality of video memories when displaying still images on a display device such as a CRT.

2. Description of the Related Art A conventional display device using a plurality of video memories, such as a color CRT display device, uses a red video memory.

The demand video memory and the blue video memory are different.
was placed in the address space. Therefore, for example, when displaying red, green, and blue figures, it is sufficient to write still image information to only one video memory, but when displaying, for example, white figures, the flowchart in Figure 3 shows It was necessary to sequentially write still image information to the red video memory, edge video memory, and blue video memory, which had the disadvantage of requiring approximately three times the writing time compared to displaying red, green, and blue figures.・Problems to be Solved by the Invention The present invention improves these conventional problems, and its purpose is to speed up the process of writing the same still image information to multiple video memories. Every time I try to do that.

Means for Solving the Problems In order to solve the above-mentioned problems, the present invention provides a writer for writing still image information into the video memories of a display device having a plurality of video memories. video memory selection means for allocating an address space and generating chip select signals for the plurality of video memories in response to data from the CPU; and a video memory to which the selection means writes still image information to which it is desired to be written before writing still image information to the video memory. and a means for enabling only the video memory and then transmitting still image information and address information to the plurality of video memories.

Effect: Since multiple video memories are in the same address space and only the video memory to which you want to write is enabled by the video memory selection means, by enabling multiple video memories, you can write to multiple video memories in the same write cycle. The same still image information can be written, and the above purpose can be achieved.

Embodiment FIG. 1 is a block diagram of essential parts showing an example of the hardware configuration of an embodiment of the present invention. In the figure, ``■'' is a CPU that controls writing still image information into a video RAM, and has a ROM, RAM, etc. inside. 2a, 2b, and 2C are its data bus, address bus, and control line. The data bus 2a has an I/O boat 3 and a buffer 4.
Red video RAM 5 a, green video RA via a to 4c
M5b, connected to blue video RAM5C. A portion of the address bus 2b is connected to the address decoder 6, and the other portion is connected to the A input terminals of the multiplexers 7a to 7c.

The control line 2c is input to the select terminal S of the multiplexers 7a to 7c, and the CPU
5c is held at a high level (hereinafter referred to as H), and other than that, that is, the CRT controller 8
The display period is maintained at a low level (hereinafter referred to as "low level").

The CRT controller 8 generates an address (CRTC address) for cyclically reading still image information written in the video RAMs 53 to 5C and a synchronization signal to the CRT 9. The CRTC address is input to the B input terminals of multiplexers 73 to 7C via the address bus 8a,
A synchronizing signal is input to the CRT 9 via a signal line 8b. The address decoder 6 decodes the input address, sends a control signal 6a to the NOR circuits 108 to 10c when the video RAMs 5a to 5C are accessed, and sends a control signal 6a to the i
/o When port 3 is accessed, a disable signal 6b is sent to it. The control signal 6a is set to L during the period when the CPUI performs write processing to the video RAMs 5a to 5C, and set to H during other periods.

The enable signal 6b is sent by the CPU to the video RAMs 5a to 5.
It is set to L before writing to C. i
The /o port 3 is a circuit that launches data sent from the CPUI via the data bus 2a, such as a ticket selection signal 3a and a green selection signal 3b.

It has a latch circuit for latching the pre-selection signal 3C.

The ticket selection signal 3c is input to the NOR circuit 10a, and the green selection output is input to the A and input terminals of the multiplexers 7a to 7c, and serves as an enable signal for the buffers 4a to 4c. The B2 input terminals of multiplexers 7a to 7c are held at L. When the control signal 2c is, for example, H, the multiplexers 7a to 7c send the A and C triad addresses applied to the A and input terminals to the video RAMs 5a to 5c, and also select the outputs of the NOR circuits 108 to 10c applied to the A2 input terminal. It is sent to the video RAMs 5a' to 5c as input, and when the control signal 2c is, for example, L, B, CR applied to the input terminal.
The TC address is sent to the video RAMs 5a to 5c, and the signal is applied to the B2 input terminal to the video RAMs 5a to 5c.
Input to chip select terminal C of 5c. Buffer 4a
~4c holds still image information sent from the CPU 1, and when accessed from the CRT controller 8, the CPU
From the data bus 2a of U to the display data bus Ila~1
It also serves to separate 1c. Video RAM 5a is a video RAM that stores red still image information;
b is a video RAM that stores green still image information, video R;
AM5c is a video RAM that stores blue still image information and has the same address space. Video RAM5a~5
In c, when the CPU address is sent from the multiplexers 7a to 7c, a write operation is performed to write the data of the buffers 4a to 4c into the area specified by the address, and the CRTC address is sent from the multiplexers 7a to 7C. Then, the storage contents of the area at the address are displayed in the parallel-to-serial converter 1 via the display buses lla to IIC.
2a to 12c. parallel serial converter j
2a to 12c convert parallel data into serial data at a predetermined speed and send it to the CRT 9. The CRT9 outputs H and L outputs from each parallel-serial converter 12a to 12C.
A video signal of a color determined by the combination of is created and a still image is displayed on the CR7 screen.

FIG. 2 is a flowchart showing an example of the software configuration of the embodiment of the present invention, and the operation of this embodiment will be explained below with reference to each figure.

The CPU 1 determines the color of the still image to be displayed, and first executes the following process corresponding to each color.

■Display color Red From I/O port 3, 3a=L, 3b=H, 3c=H
■Display color Green From I/O port 3 3a=H, 3b-L, 3c-H
■Display color Blue Outputs 3a=H, 3b=H, 3c- from I/O port 3 ■Display color Yellow 3a=L, 3b=L, 3c- from R/O port 3
Output H ■Display color Magenta From I/O port 3, 3a=L, 3b=H, 3c=L
Output ■Display color cyan From i10 boat 3 3a=fertility 3b=L, 3c=L
■Display color White From I/O port 3 3a=L; 3b=L, 3c
=L output Next, control line 2C is set to H and multiplexer 7
Switch a to 7C to the AI and A'2 input terminals, send an address that matches the shape of the figure to be displayed to the address bus 2b, and input still image information such as H1 for the colored part and L for the non-colored part. is sent to the data bus 2a. The operating states of the video RAMs 5a to 5c correspond to the processing of the above-mentioned items 1 to 2, respectively.
5c: Disable ■ Video RAM 5b: Enable, Video RAM 5a, 5
c: Disable ■ Video RAM 5 c: Enable, video RAM 5a
, 5b: Disable ■ Video RAM 5a, 5b: Enable,
If RAM 5C: Disable ■ Video RAM 5a, 5c: Enable, Video RAM 5
b: Disable ■ Video RAM5b, 5c: Enable, video RAM5
3: disabled, video RAM 5a to 5c: enabled in the case of (2), so still image information is written only to the video RAM corresponding to the display color. Therefore, writing to multiple video RAMs is completed in a series of write cycles.

Note that when the above writing process is completed, the CPUI sets the control line 2c to L and the multiplexers 7a to 7c to B.
1 and B2 input terminal side to perform cyclic reading of the video RAMs 5a to 5c based on the CRTC address.

DETAILED DESCRIPTION OF THE INVENTION According to the present invention, when a plurality of video memories are in the same address space and only the video memory to which data is to be written is enabled by i10baud1-, it is possible to enable the plurality of video memories. By writing the same still image information to a plurality of video memories in the same write cycle, the process of writing the same still image information to a plurality of video memories can be performed at high speed. Furthermore, by making a plurality of video memories have the same address space, there is an effect that the memory space of CI) U can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of main parts showing an example of the hardware configuration of an embodiment of the present invention, FIG. 2 is a flowchart showing an example of processing of the embodiment of the invention, and FIG. 3 is a flowchart 1 showing conventional processing. It is. ■ is the CPU, 2a is the data bus, 2b is the address bus,
2C is the control line, 3 is the I/O port, 4a
〜4C is a HA sofa, 5a〜5C is a video RAM, 6 is an atres defuder, 7a〜7b is a multiplexer, 8 is a C
An RT controller, 9 is a CRT, and 10a to IOC are NOR circuits.

Claims (1)

[Claims] In a writer that writes still image information to the video memory in a display device having a plurality of video memories, the same address space is allocated to the plurality of video memories, and the chips of the plurality of video memories are configured to receive data from a CPU. A video memory selection means for generating a selection signal, and before writing still image information to the video memory, the selection means enables only the video memory to be written, and then the still image information and address information are transferred to the plurality of video memories. 1. A video memory writer for a display device, comprising means for sending data to a memory.