JPS5854381A - Display - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a display device with a multilayer memory structure having a plurality of memories corresponding to the above.

In conventional display devices of this kind, it is necessary to sequentially access a plurality of memories corresponding to the display screen to convert or detect data in the memories. Therefore,
As the number of memories increases, processing times such as access time become longer, and image processing times become slower.

SUMMARY OF THE INVENTION In order to eliminate the above-mentioned drawbacks, it is an object of the present invention to provide a display device that has a simple structure and can perform image processing at high speed.

To this end, in the present invention, a writing means is provided that can simultaneously or selectively write to a memory group corresponding to a display screen, thereby enabling high-speed image processing for color display and the like.

The present invention will be described in detail below with reference to the drawings.

An example of the configuration of the first mu display device of the present invention is shown, where:
The CPU is a central processing unit that controls the drive of each section, supplies address control signals to each section via address path B, and exchanges data with each section via data path DB. Drive control by the central processing unit CPU is executed based on control signals and the like supplied from an input section (not shown).

(3BT is the display unit, ORT (3 is the CRT control circuit that controls the drive of the display unit ORT). OKG is the clock generator that generates the basic clock, and the basic clock is the central processing unit CPU and OR'l' control circuit 0
Supplied to RTO. The control unit 0RTO supplies a horizontal synchronization signal and a vertical synchronization signal to the display unit QRTK via signal lines S/ and SJ.

ADS is an address selector, R) [, GM, BM
are red display memory, green display memory, and blue display memory, respectively, and each memory is red.

Stores data that combines green and blue image data. Central processing unit CPU and CRT control circuit 0RT
An address signal and a CRT address signal are supplied from O to this address selector ADSK via address signal M B and signal line S3, respectively, and K as described later.
to access each memory RM, GM and BM. In the address selector ADS, the CRT control circuit (3R
Based on the address switching signal supplied from 'l'O via the signal line s4I, one of the above-mentioned address signal and CRT address signal is selected, and the selected signal is displayed as a memo via the signal line S3. Supply to 9RM, GM, and BM respectively.

Here, RFF, GFF, and BFF are set/reset switching controlled by a red display memory select latch, a green display memory select latch central processing unit (3PUK), and a red display memory select latch RFP.
When RFF is set, a control signal is supplied to the red memory select gate (SR) via the signal line St. Game via signal @Sa) 1iiiI to SR
When the IIl signal is supplied, the red display memo! via the signal line $7! A JRMK signal is sent.

From this K, the red display memo IJRM can be accessed by the central processing unit. Similarly, latch GFF
and BFF are set, the signal line S
Signal is connected via l and S9) SG and SB
K is supplied. Game) SG and SB to Mori, signal @
Signals are sent to memories GM and B via StO and 3//
MK will be sent. This allows memories G) [and B
M becomes accessible.

Next, %OIF is a data interface that has an inverter function, and is connected to the data bus DB, and is connected to the central processing unit CPU and the memory IJRM, GM, and BM.
control the exchange of data between

RIF, GIF and BIF are memory interfaces 7 and 8, respectively, and the output data supplied from the central processing unit (3PU to the interface (jIF) via the data bus DB is sent to the interfaces RIIF, GIF and BIF via the signal line 812. These interfaces RIF, GIF
and BIF transmits output data supplied from the central processing unit CPU to signal lines 813, 8141 and 81.
3 to the OR gate OR and the video control circuit VC, and the signal line S/4. S/7
and memory RM, GM and BM through Sll
output towards. On the other hand, the data supplied from the memories RM, (J and BM to the interfaces RIF, GIF and BIFK via the signals 4I8/4.S/? and sn are connected to the signal lines S/3 and F3#, respectively.
and Sll to output to the OR and video control circuit To. Or game) O
The data output from R is supplied to the interface OIF via the signal line S/9, and further supplied to the central processing unit (3PUK) via the data bus DB. Here,
Each interface (3IP, RIF, GII
F and BIF Kara and Game) SR, SG and SB
, a control signal O is sent from the central processing unit CPU.
N is a sliding door, and the direction of data transfer is controlled by turning on this signal.

In the video control circuit VC, the signal 1iii
IS13. When data is received via Slf and Sts, the video signal of the red element, the video signal of the green element, and the video signal of the blue element are supplied to the display section CRT via the corresponding signal lines sx, 82/ and S22. do. Display@ORT displays images based on these video signals.

Here, in the display section (3RT), set the pixel size of the display area of the display screen to % horizontal S as shown in the US image.
Assuming that the pixels are 1λ and λj in length, the structures of the corresponding red display memory RM, # color display memory GM, and blue display memory BM are shown in FIG.

That is, in this example, the memory RM (GM, BM) is configured with l addresses and l bits, and l bits are assigned to / of the display screen.
Make it correspond to the i1 element. The addresses are arranged consecutively in the horizontal direction like A/ and Muko, and M1 is at memory area 10 and Muko is at memory area 11. 41 addresses are arranged in one horizontal line. Therefore, D is memorabilia 14
It will be number 3. In addition, in the vertical direction, the addresses are arranged in the column St, M3 is memory address 14411, Bij/≦3
This will be address 0 and address OFiI431#. here,
For each address, the details are shown in the figure below, from the most significant digit MSB to the least significant digit LSB K.
The t bits of ~bO are arranged horizontally. Further, the vertical direction corresponds to the raster of the display section CRT using the scanning line method.

Figure S shows the pixels of the display screen of the display unit ORT and the memory RM.
, GM and BM addresses. For example, the display position A (see Figure 2) consisting of one pixel on the display screen is the address of each memory R.
Corresponding to memory address 10 of M, GM, and BM, data at address O is displayed and output for seconds. Similarly, 1 display position 3 is memory address 4' of each memory.
Address 41 corresponds to this.

Also, in Figure 1, 1 red, 1 # as in this example.
This figure shows the correspondence between the mixture of the three primary colors and the expressed color in a three-primary color system in which color display is performed using each color element of blue and blue.

In the display device of the present invention configured as described above, three memories RM, , G corresponding to the display screen of the display section CRT are provided.
When converting data in M and BM, each memory RM, GM k, and BM can be accessed simultaneously by setting the memory select latches RFF'e Gyy and B1ff simultaneously. Therefore, there is no need to sequentially perform QKJ write operations to each memory RM, GM, and BM as in the prior art, and data conversion processing can be performed at high speed.

As described above, according to the present invention, it is possible to significantly improve the image processing speed in a display device with a multilayer memory structure.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of the display device of the present invention, and FIG.
The figure is a diagram showing the pixel size of the display screen, Figure 3 and Figure 3 are diagrams showing examples of the address and bit configuration of the memory, respectively, and Figure 3 is the correspondence between the display screen and memory. FIG. 4 is a diagram showing the correspondence between the mixture of the three primary colors and the expressed color when color display is performed using the three primary color system of red, il, and blue. CPU...Central processing unit, AB...Address bus, DB...Data bus, CR
T...display section, 0FLTO...OR'l' control circuit, OKG...clock generator, MUDS...address selector, RM, GM, BM...memory, RFF,
GFF, -BFF...Memory select latch, SR
, GR, BR...Gate, OIF, RIF, GIF, BIF-...Iator 7L
4th, OR...OR gate, vO...Hiteo control circuit, S/-822...Signal line. Flute II Woman I Figure 6

Claims (1)

[Claims] A display device having a memory group for storing image data and displaying an image on a display means based on the image data stored in the memory group, simultaneously or selectively transmitting image data to the memory group. The special feature is that it has a writing method that allows writing! display device.