JPH0879625A - Digital picture division display system - Google Patents

Abstract

PURPOSE: To improve the display speed of a picture by connecting plural picture display circuits and a CPU circuit by buses consisting of a data signal line, an address signal line and a control signal line and transferring digital picture data through the bus. CONSTITUTION: CPU 5 and the like of a digital picture division display device 1 are connected by the bus consisting of the data signal line, the address signal line and the control signal line. Then, a desired picture file is opened. It is checked whether the picture file is divided for multi-display or not. When it is not, a division processing is executed. The picture display circuit which is to be made active is set among the plural picture display circuits 4a-4d. Picture data equivalent to the active picture display circuit among divided picture data is transferred and is written into a picture memory. A picture signal is outputted and displayed. The processing is executed for all the picture display circuits 4a-4d, and the picture file is closed. Then, the processing is terminated. Thus, display speed when digital picture data is divisionally displayed by the processing is improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a system for dividing and displaying digital image data on a multi-screen display consisting of a plurality of core displays.

[0002]

2. Description of the Related Art In recent years, the number of cases in which a large display is used as a monitoring board of a plant is increasing, including various events such as exhibitions and exhibitions.

In particular, with the development of projection-type displays, multi-screen displays have become widely used because of the possibility of displaying uniform images with small joints.

A video signal processing device called an enlargement / distribution device is used for displaying on the multi-screen display, and the input video signal is divided in real time and output.

There are various input signals such as television signals such as NTSC and HDTV, and computer signals such as personal computers and workstations.

In the above video signal processing device, the input signal is in a so-called analog video signal format, and the resolution and the like are determined for each input signal.

Further, since the above-mentioned video signal processing device merely divides its input signal, the input / output information amounts are basically the same.

[0008]

On the other hand, the resolution and size of digital image data used in a computer or the like can be freely set, and can have a resolution or size higher than the display resolution of a display.

2000 dots × 150 as shown in FIG.
Taking 0 dot digital image data as an example, 640
When it is attempted to display the image data of FIG. 8 on a single dot × 480 dot display without lowering the resolution,
Like, can display only a small part.

On the other hand, the total of four displays is 12
If you set the display range of 80 dots x 960 dots,
As in 0, the displayable range is widened and the amount of information to be transmitted can be increased.

By the way, in the case where the above-mentioned video signal processing device performs the enlargement distribution processing to display an image on four displays, for example, a computer analog video signal having a resolution of 640 dots × 480 dots is input. In the case of 4 displays, 2000 dots x 1500
Only the range of 640 dots × 480 dots of the dots is displayed, the amount of information itself is the same as in FIG. 9, and the display is rough overall.

As shown in FIG. 10, in order to widen the displayable range and increase the amount of information to be transmitted, a divided display system of digital image data has been considered.

For example, as shown in FIG. 12, a plurality of computers are arranged for each display device, and these computers are LA.
There is a method of connecting to a computer that manages digital image data via N.

In many cases, a workstation is used as a computer and display control using the X protocol is performed.

However, since the overhead of processing such as LAN communication protocol and X protocol is large, it takes a long time to transfer the image data.
The time required to rewrite the image data, that is, to display the image becomes long. In addition, the system configuration is large and the cost is high.

[0016]

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and as shown in FIG. 1, a plurality of image display circuits and a CPU circuit are composed of a data signal line, an address signal line and a control signal line. It is connected by a bus and digital image data is transferred through this bus.

[0017]

As a result, the image data transfer time is shortened, and the connection between the image display circuit and the CPU circuit is much easier than in the case of connecting the computers shown in FIG.

[0018]

FIG. 1 shows a first embodiment of the present invention.

In the figure, 1 is a digital image division display device,
Reference numeral 2 is a digital image data storage device, and 3a to 3d are display devices. The digital image division display device 1 includes a plurality of image display circuits 4a to 4d, an image display circuit I / F6, a data storage device I / F7, and a CPU circuit 5.

Further, the respective constituent elements in the digital image divisional display device 1 are connected by a bus composed of a data signal line, an address signal line and a control signal line.

The image display circuits 4a to 4d are equipped with a memory capable of displaying an image on at least one of the display devices 3a to 3d.

FIG. 2 shows a memory map on the bus composed of the data signal lines, address signal lines, and control signal lines of the digital image divisional display device 1.

In this embodiment, there are a plurality of image display circuits 4a.
4d to 4d are allocated to the same area, and the image data are written in the memories of the image display circuits 4a to 4d while sequentially switching the image display circuits 4a to 4d.

The display processing flow is shown in FIG. First, a desired image file is opened. The image file is
It is checked that the display has been divided for multi-display, and if it is not completed, division processing is performed.

Next, one of the plurality of image display circuits 4a to 4d to be activated is set, and among the divided image data, the image data corresponding to the active image display circuit is transferred and written in the image memory. At the same time, the image signal is output and displayed.

This is applied to all the image display circuits 4a-4d.
To close the image file and exit. By the above processing, the digital image data can be divided and displayed.

FIG. 4 shows a conceptual diagram of image file division processing.

For example, the original image data is divided into a plurality of image division data by the image division processing software installed in the CPU circuit 5, and the data writing software is installed in each of the image display circuits 4a to 4d. Write to the image display memory equipped in the. The division method may be, for example, divided by address so that the original image data of 1280 dots × 960 dots is divided into two pieces in each of the horizontal and vertical directions into four pieces of data of 640 dots × 480 dots.

Further, the divided image data may be provided with color reference data for holding information regarding the color of the original image.

The color reference data is used when converting the digital image data into an analog signal, and the digital image data is converted according to the value of the color reference data.

For example, each of RGB has 8 bits, and about 16
This is used, for example, when the number of colors of original image data having data for 800,000 colors is limited to 256 colors, and as a result, image data can be compressed.

Switching of the image display circuits 4a to 4d is performed via the image display circuit I / F. Its configuration is, for example, FIG.
You can use the one shown in.

The circuit of FIG. 5 corresponds to each of the image display circuits 4a to 4d.
It manages the memory read and write signals to be distributed to, and the read and write signals of the input / output port, and the selection of the active image display circuit is to distribute this control signal to the selected image display circuit.

In the circuit of FIG. 5, the address signal of the address bus is decoded by the address decoder 21, the image display circuit I / F itself is selected, and the signal on the data bus is
The data is latched by the data latch circuit 23, and the latch output is
The memory read / write signal and the read / write signal of the input / output port are selected through the gate circuit.

The power-on preset circuit 22 is for uniquely determining the active image display circuit 4 when the power is turned on.

In this system, as described with reference to FIG. 2, since the memory area allocated for the image display circuits 4a to 4d is one image display circuit, compared with the system of FIG. 6 in which the memory area is allocated to each image display circuit. No need to expand memory space.

Therefore, a multi-screen display having an arbitrary number of screens can be accommodated without expanding the address space of the memory, and the bus structure consisting of data signal lines, address signal lines, and control signal lines becomes simple.

For the above reason, according to this method, it is possible to use an expansion bus such as an ISA bus which is frequently used in personal computers and the like, and the image display circuits 4a to 4d, for example, VG.
Since it is possible to use parts having a large amount of distribution such as A board, it is possible to keep costs low.

Of course, since image data is transferred using a bus composed of data signal lines, address signal lines, and control signal lines, it goes without saying that high-speed data transfer is possible and the display speed is high.

FIG. 7 shows an example of division processing which is characterized by the division method of original image data.

The feature is that color reference data is also held separately for each divided image data.

In this system, since the image display circuits 4a to 4d exist independently corresponding to the display devices 3a to 3d, it is necessary to set and hold the color reference data independently when dividing the original image data. You can

By doing so, 2 out of about 16.8 million colors can be obtained.
Since 56 colors can be selected for each of the display devices 3a to 3d, the number of colors to be displayed can be substantially increased and the image quality can be improved. Particularly in the case of a large screen display, image deterioration due to the limitation of the number of colors is conspicuous, so that the effect is great and effective divided display of digital image data can be realized.

In the explanatory view, the display devices 3a to 3d are 4
Although a multi-display is shown, in the present invention,
As described above, it goes without saying that the number of the display devices 3 may be any number and the layout thereof is completely free.

[0045]

According to the present invention, a plurality of image display circuits and a CPU circuit in a digital image division display device are connected by a bus composed of a data signal line, an address signal line and a control signal line, and digital image data is transferred to this bus. Image data transfer time is shortened, image display speed is improved, and a digital image division display device can be provided at low cost.

[Brief description of drawings]

FIG. 1 is a diagram showing a first embodiment of the present invention.

FIG. 2 is a diagram in which the same memory area is shared by a plurality of image display circuits.

FIG. 3 is a flowchart of divided display processing.

FIG. 4 is a diagram illustrating the concept of image data division display.

FIG. 5 is a diagram showing a configuration example of an image display circuit I / F.

FIG. 6 is a diagram showing an example of allocating a memory area for each image display circuit.

FIG. 7 is a diagram illustrating the concept of image data division display.

FIG. 8 is an explanatory diagram of digital image data.

FIG. 9 is a diagram showing a part of digital image data on one display.

FIG. 10 is a diagram showing digital image data displayed on four displays according to the present invention.

FIG. 11 is a diagram showing a part of digital image data displayed on four displays in the conventional expanding and distributing apparatus.

FIG. 12 is a diagram showing an example of digital image division display using a LAN.

[Explanation of symbols]

1 ... Digital image division display device, 2, 102 ... Data storage device, 3a-3d ... Display device, 4a-4d ... Image display circuit, 5 ... CPU circuit, 6 ... Image display circuit I / F, 7
... data storage device I / F, 10 ... computer.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Takanori Komatsu 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Ltd.

Claims (2)

[Claims] 1. A digital image division display comprising a display device including a plurality of display devices, a data storage device for storing digital images, and a digital image division display device for outputting and displaying the digital images on the display device. In the system, a digital image division display device includes a plurality of image display circuits, a CPU circuit, an image display circuit I / F that selectively controls the image display circuits, and a data storage device I / F that interfaces with a data storage device. F
And a plurality of image display circuits, the CPU circuit, the image display circuit I / F, and the data storage device I / F.
Are connected by a data signal line, an address signal line, and a control signal line, and the CPU circuit reads out a digital image stored in the data storage device I / F, and a plurality of images are displayed in the image display circuit I / F. While sequentially switching the image display circuits, the read digital image is written in each of the image display circuits, and the image is displayed on each display device by the output of each image display circuit. 2. The digital image divisional display system according to claim 1, wherein image data to be written in each of the plurality of image display circuits is of two types, color reference data and divided image data, and the color reference data is A digital image division display system characterized in that data values are different for each of a plurality of image display circuits.