JPS6079394A - Color graphic display unit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] [Technical field of invention] The present invention relates to color graphics display devices.

[Prior art and its problems]

Conventionally, in a color graphic display device, when writing color graphic data to a video RAM, color data of R (red), B (blue), and G (green) are simultaneously written to each display dot. . Therefore, when displaying graphic data or changing the display color in a designated display area, even if you want to write data only to a specific color area among R, B, and G in the video RAM, always use R. , B, and G, and the control was very troublesome.

[Purpose of the invention]

The present invention has been made in view of the above points, and allows data to be independently written to any R, B, G area of a color graphic video memory, making display control extremely easy, and color graphic video memory. An object of the present invention is to provide a color graphic display device that can enhance display functions.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the diagram, No. 1 is the key human power department, and the key human power is CP.
Sent to U 12. This CPU J 2 has A inside.
, B, . . . and output color data for display to the data rewriting control circuit 13. The above color data consists of three primary colors, R (red), G (green), and B (blue), and four bits, H (luminance). The data rewrite control circuit 13 is a 1-byte (8-bit) buffer 13a.

13b, the color data from the CPU 12 is stored in the buffer 13m, the R, G, and H color bits are sent via the dirt circuit (y7.G!', GJ), and the brightness signal H is sent directly to the video RAM 14. This video RAM 1'4 stores 2 bits of color data R, G for each byte.

B and H are all memorized. This video RAM
The color data stored in 14 is R, G, etc. when modifying display data.

B color bit is dirt circuit G4. Via G5 and G6, the luminance signal H is also directly sent to the data rewrite control circuit 13 and written into the buffer 13b. And the dirt circuit Gl.

G2, G3, G4,'G5, G6 are CPU
Plain designation circuit 1 that operates according to commands from J2
5 is f-controlled. This plane designation circuit 1
5 is constituted by, for example, a 3-bit latch circuit. Further, the CPU 12 outputs address data from the address bus AB and inputs it to the data rewrite control circuit 13 as well as to the multiplexer 16 and address decoder 17. The output of this address decoder 17 is
The signal is input to the data rewrite control circuit 13 and multiplexer 16 as a selection signal. Also, this multiplexer 16
Address data is inputted from the synchronization signal generation circuit 18 to. The multiplexer 16 selects the address data from the CPU 12 or the synchronization signal generation circuit 18 according to the selection signal from the address decoder 12. Select and supply to video RAM J4. Memory data is read from the video RAM 14 in accordance with address data sent via the multiplexer 16 and sent to the shift circuit 19. This shift circuit 19 includes a video RAM 14
The data read out from the synchronizing signal generating circuit 18 is shifted in synchronization with the clock pulse from the synchronizing signal generating circuit 18, and the color data R, G
,B.

H is converted into parallel data and output to a display section (not shown). The display section also includes the synchronization signal generation circuit 18.
Also horizontal and vertical synchronization signals are sent.

Next, the operation of the above embodiment will be explained. Normally, that is, in a state where no writing is performed to the video RAM 14, the address data from the synchronizing signal generation circuit 18 is selected by the multiplexer 16, and the data stored in the video RAM 14 is read out to the shift circuit 19. This shift circuit 1
Reference numeral 9 shifts the data read from the video RAM 14 in synchronization with the clock pulse from the synchronization signal generating circuit 18, converts the color data R, G, B, H into parallel data, and outputs the parallel data to the display section.

Therefore, when rewriting the data stored in the video RAM 14 according to the key input from the key input unit 11,
Write data is sent from the CPU 12 to the data rewrite control circuit 13, and address data is output to the address bus AB. When address data is output from the CPU 12, it is decoded by the address decoder 17, and the decoded output causes the multiplexer 16 to
It is switched to the address bus AB side of l2.

For this reason, the data rewrite control circuit 13 and the video RAM 14 are controlled by the address data output from the CPU 12.
address is specified. Also, at this time, the CPU 12 provides 3-bit grain designation data to the plane designation circuit 15 to perform dart control of the gate circuits 01-G3.04-G6.

In this case, the dirt circuits G1-G3.04 to G6 are controlled by the plane designation circuit 15 into eight states from all gates on to all gates on. However, the above C
The data output from the PU 12 is temporarily stored in the buffer 13a in the data rewriting control circuit 13, and then sent to the dart circuit G1. (Video RAM 14 via ,2,G,9
written to. In this case, the video RAM 14 is
The memory contents specified by the address data from U12 are stored in the dart circuit G4. The data is read out to the data rewrite control circuit 13 via Gs and Ge. The data read out by the data rewrite control circuit 13 is then corrected by the CPU 12, and then sent to the dirt circuits Gl, G2 . It is written to the video RAM 14 via G3.

As mentioned above, R and G for video RAM J4.

By specifying the color area, border, and plane of B, it becomes possible to synthesize color graphics as shown in FIG. FIG. 2 shows an example of combining three circles RlG and H so that some of them overlap.

First, for example, a blue plane 21 is designated in the video RAM 14, a circle is drawn at a predetermined position, and the inside of the circle is colored blue. Next, specify the red plane 22 and draw a circle at the specified position, and color the entire circle in red. Next, specify the green plane 23 and draw a circle at the specified position, and then The inside of the circle is colored green. By performing the above processing, the composite color is displayed on the display screen 24. That is, the composite color of red and blue is colored purple, and the composite part of red and green is colored yellow and green. Cyan is displayed in the composite area of and blue, and white is displayed in the composite area of red, green, and blue.

As described above, the three primary colors R, G, and H can be written individually into the video RAM 14 to display a composite color.

As described above, according to the present invention, the video RAM 14
On the other hand, since each of the three primary colors R, G, and B can be written independently, the colors can be changed freely without affecting the already drawn figures. Further, even if all the colors are changed, other color bits in the composite color part are not affected, so the figure is not divided by the boundary color line. Therefore, it is possible to provide a color graphics display device that can extremely easily control the display and improve the color graphics display function.

[Brief explanation of drawings]

The drawings show an embodiment of the present invention, and FIG. 1 is a block diagram showing a circuit configuration, and FIG. 2 is a diagram for explaining a color graphic composition operation. 1)...Key personnel department, 12...CPU, IJ.
...Data rewriting control circuit, 14...Video RAM, 7
5... Plane designation circuit, 16... Multiplexer, 17... Address decoder, 18... Synchronization signal generation circuit, 19... Shift circuit, 21.22.23...
- Plain, 24...display screen.

Claims (1)

[Claims] In a color graphic display device, a data processing device, a video memory into which color graphic display data is written by the data processing device, and a device provided on each red, blue, and green color data line from the data processing device to the video memory. 1. A color graphic display device comprising: an f-) circuit, and means for selecting and specifying each of the r-1 circuits in response to a control command from the data processing device.