JPS6048075A - Dynamic memory display circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a dynamic memory display circuit that uses part or all of a dynamic memory as a display refresh memory, and particularly relates to a dynamic memory display circuit that uses a dynamic memory refresh circuit as a display controller. The present invention relates to a shared dynamic memory display circuit.

[Background of the Invention] Hereinafter, the configuration of a video RAM type display circuit in which a refresh memory is shared in a dynamic memory circuit will be explained with reference to FIG. 1 is a line consisting of a data bus, an address bus, and a control bus.2
is a dynamic memory circuit, and address signals necessary for the operation of this dynamic memory are input from an address multiplexer 3, and control timing signals are input from a timing circuit 4. And dynamic memory circuit 2
The output is output to data buffers 5 and 6. 07 is a reference clock generation circuit, and the display control circuit (07) is a reference clock generation circuit.
Hereinafter, it will be referred to as 0RTO. This is, for example, HD46505S manufactured by Hitachi, Ltd. ) 8, the timing circuit 4, and the parallel/serial conversion circuit 9 are provided with clock signals, respectively. The 0RTO8 can be programmed into a microcomputer (-not shown) connected to the pass line 1, thereby allowing the number of characters to be displayed, cycle, etc. to be set. Reference numeral 10 indicates horizontal and vertical synchronization signals for display. Reference numeral 11 outputs a character font corresponding to the input code from a character generator, and inputs the character 7 ont to the parallel/serial conversion circuit 9. Further, 12 is an attribute circuit that provides attributes such as color designation, blinking, cursor, and masking for each character. C. Character serial data is obtained at the video output terminal 14.

Here, the character display operation within the dynamic memory circuit 2 will be explained. The CRTC 8 outputs an address signal of the display character and inputs it to the address multiplexer 3. The address multiplexer 6 receives a signal from the timing circuit 4 indicating that it is the display period, and inputs the data from the 0RTO 8 to the dynamic memory circuit 2, divides the output data into character data and attribute data, and stores the data in the data buffer 5. Take it into B. From character data,
A corresponding character font is obtained by the character generator 11, and parallel data is generated according to the display clock.
Transfer serially dot by dot, attribute circuit 12
In the case of a color display, R, G, and B outputs 14 are obtained by mixing the outputs from the input and output terminals in a mixing circuit 13.

On the other hand, when the dynamic memory circuit 2 is used as a memory for a microcomputer, it can be used as a conventional memory by switching the signal from the address multiplexer B to be applied from the path line side. In addition, in the case of dynamic memory, there is a refresh problem, but this is caused by periodic display using 0RTO8,
A refresh cycle is executed in response to this signal.

Here, let us consider the case where a graphic display is performed on a CRT (cathode ray display tube). Conventionally, a character generator 11 was used to display characters, but in order to draw arbitrary characters, symbols, figures, etc.
It becomes necessary to have a pattern similar to the state displayed on RT. That is, one bit of data is required for one dot on the CRT. Furthermore, when colorized,
One dot is displayed with three bits of RlG and B, and if attributes are included, one dot is displayed with four bits. This requires twice as much data as traditional memory access. Conventionally, it consisted of character codes and attributes, but it now consists of five types of character data and a) IJ buttes. This requires fast memory access, which causes a cost map.

[Purpose of the invention]

An object of the present invention is to provide a dynamic memory display circuit that has a simple configuration and can access a large amount of data at high speed.

[Summary of the invention]

In order to achieve the above object, the present invention shares the dynamic memory between the data memory and the display memory, and furthermore, eliminates the need for a refresh circuit by performing refresh with the display controller. It is characterized by a memory configuration that allows G, B, and attribute memories to be accessed in parallel.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIG. In addition, in this figure, the same reference numerals as in the conventional art indicate the same parts as in the conventional art. The dynamic memory circuit 2 has a 256-byte memory area using 32 64-bit dynamic RAMs (for example, HM486J manufactured by Hitachi, Ltd.), and this area may be entirely used as a display memory. The address multiplexer is a 4-person power 1-output multiplexer (for example, 74L manufactured by Hitachi, Ltd.
S153) Using signals 15, 16, 17, and 18, the CPU address signal and pRTO8 display address are switched using the two inputs A and B. Dynamic RA for A input
The RAS input signal of the input of M2 is the row of the dynamic RAM.
Give an address select signal) and use this signal to switch the address to the dynamic RAM 2 between row and column.

On the other hand, the B input switches between the display address and the CPU access address (CPU/DISP), and both the A input signal and the B input signal are generated by the timing circuit A (f).

Display data is latched from the dynamic RAM 2 into data latches 19, 20, 21, and 22. The latch timing at this time is determined by the CAS from the timing circuit 4.
-Latched on the rising edge of the DISP code. The data latch 19.2021 latches R, G, and B dot data, and is connected to a parallel/serial converter circuit (for example, 74L8+66 manufactured by Hitachi, Ltd.) 25, 2, respectively.
The data is input in parallel at 4.25 degrees, becomes serial data according to the clock, and is output bit by bit from the output Qh. On the other hand, the attribute data of the data latch 22 is input to the attribute circuit 12 as parallel data. The output Qh of the parallel/serial conversion circuit $23.21.25 and the output of the attribute circuit 12 are mixed circuit 1.
3, the signals are mixed and picked up to produce corresponding R, G, and B outputs.

On the other hand, when the CPU accesses the DRAM 2, data latches 26, 27, 28, and 29 are used.

When writing data from the data CPU to the dynamic RAM2, send the data to the data fins DATAO and DATAI, address ADDR and chip select C8O to C8.
5, and a write signal WE to perform writing. In addition, for reading, address ADDR,
By supplying any one of chip selects 080-083, the timing circuit 4's 0AS-C! The rising edge of the PU signal latches the data into the data latches 26, 27, 28, 29.

The CPU reads data through data buses DATAO and DATAI. In addition, the gate 60 is a C for display address.
The As signal and the CAs signal for CPU access are ANDed and the OA8 control circuit (for example, 7 made by Hitachi, Ltd.) is
4LS158) Input to 31. In this OAS control circuit, depending on whether the access is from the CPU or the address for display,
In addition, necessary CAs signals are applied to the corresponding dynamic RAMs 2 depending on conditions such as which chip is selected in the case of CPU access, and the power during the display period in the case of display. Further, here, the data line DATAO and the data line DATAI indicate data corresponding to even and odd data addresses, respectively. In this case, the data line DATAO and data line DATAI are separated on the data bus, so the data bus is 16 bits, but these are collectively 8 bits.
It may also be a bit data bus.

On the other hand, in dynamic RAM2, dynamic RAM
By dividing the blocks into even and odd numbers, one 0
Four RAM blocks can be accessed at once by accessing from the RTOB side.

These four blocks are respectively R (red) memory and G (
Green memory, B (By allocating to the blue memory and attribute memory, 8-bit data on the display screen can be displayed in one access, so there is no need to use a memory with a fast access speed. For example, dot clock Assuming 20 MHz (50 ne per dot), 20 MHz ÷ 8 dots = 2.5 MHz/byte. 2.5 MHz is 400 nθ, so if you use a memory with a cycle time of 400 nθ or less, it will cost 0. In the conventional method, 8 dots on the screen It used to require twice as much memory, less than 200 ns, to access the bit zone;
Requiring a memory of 00nθ or less means that the cost of the memory is low. In addition, access is divided into two times,
A complex circuit would be required to latch and synchronize the data and output it, but this method is simple and can improve functionality without increasing cost.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, it is possible to obtain a dynamic memory display circuit that can access a large amount of data at high speed with a simple configuration.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a conventional display circuit using a dynamic memory, and FIG. 2 is a block diagram showing an embodiment of the present invention. 1...Pass line, 2...Dynamitsuku memory, RO...Address multiplexer, 4...Timing circuit, 5, 6. 19. 20. 21. 22. 2
6. 27°28.29...Data latch, 7...
Reference clock generation circuit, 8...0RTO, 9, 23,
2A, 25...parallel/serial conversion circuit, 11.
...Character generator, 12...Attribute circuit, -15...Mixing circuit, 14...Output agent Patent attorney Akira Takahashi (Fig.

Claims (1)

[Claims] a dynamic memory element; a timing signal generation circuit for supplying a timing signal to the dynamic memory element; an address multiplexer for selectively supplying a plurality of sets of input address signals to the dynamic memory element; The device includes an output data buffer that temporarily stores and outputs read data, and a display controller that displays the read data on a display unit, and uses at least a portion of the dynamic memory element as a display refresh memory. Therefore, a dynamic memory display circuit is provided in which a display address signal is supplied to the dynamic memory element via the address multiplexer, and the dynamic memory element is separated into even addresses and odd addresses.