JPH0293585A - Display memory controller - Google Patents

Abstract

PURPOSE:To improve access efficiency by accessing a display memory all in synchronism with a system clock and reading a 2nd line memory only in synchronism with a display clock. CONSTITUTION:A CPU 110 accesses the display memory 200 in synchronism with the system clock to read its stored data out. Output data from a data attribute processing circuit 104 which can modify dot pattern data(DP) is transferred to the 1st line memory 105 with the system clock. Here, when display data of one horizontal display period is stored, the data is transferred to the 2nd line memory 106 at a high speed in a nondisplay period with the system clock and outputted as an R, a G, and a B signal from an RGB decoder 107 in synchronism with the display clock of a display side. Consequently, the access efficiency is improved even if the capacity of the data bus of the display memory is small.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a display memory control device used in a display in which a display memory is controlled by a microcomputer to obtain a display screen.

(Prior Art) A color display such as Videotex is provided with a display memory control device. FIG. 4 shows a conventional display memory control device. A central processing unit (hereinafter referred to as CPU) 400 is connected to a buffer circuit 402 via an 8-bit data bus 401.
is connected to a 16-bit data bus 403.

The data bus 403 is branched into 4-bit buses 404, 405, 406, and 407, and each bus 404.
05,406.407 is display memory 411.412.4
13', 414. Also, 415 is RG
B decoder and display memories 411, 412, 413
, 414 in units of 16 bits,
It is converted into R, G, and B display signals in accordance with the display cycle, that is, in synchronization with the display clock.

1, the conventional display memory control device connects the display memory with the 4-bit data bus configuration to the display memories 411 and 4.
Four such as 12,413.414 are used and accessed. An example of this is a display memory configuration called block coloring.

The block colored display memory structure can be roughly divided into a -layer dot pattern memory section and a functional block memory section.

Dot pattern data for characters and figures is stored in the dot pattern memory section, and data for each functional block, that is, coloring data (foreground color data, background color data) and display attribute data (flashing, etc.) is stored in the functional block memory section. be done. Display memory 411, 412, 413゜4
14 data is specified by the address data and read out at the scanning line period, and is converted into R, G by the RGB decoder 415.
, B signal.

The capacity of the functional block memory for foreground color and background color data is as follows: If 16 colors (8 colors and 2 gradations) are specified for both the foreground color and background color in functional block units (4 x 4 pixels), the capacity of the functional block memory for each functional block is as follows: 4 bits (2-16 colors) are required.

On the other hand, the capacity of the functional block memory for display attributes is 3 bits (2
-8 types).

FIG. 5 is a timing chart of a display memory control method called the cycle steal method. DP)
, display attribute data (CC), foreground color data (FG),
Background color data (BG) is read out in units of 16 bits and decoded by an RGB decoder 415.

Since the address bus is supplied from the CPU 400, 8
By giving the bit address data twice,
16 bit data is read.

In this way, each dot pattern data (DP), display attribute data (CC), foreground color data (FG), and background color data (BG) are read out in units of 16 bits and are input to the decoder 415. .

At this time, writing access to the display memories 411 to 414 and other processing ( This period is referred to as CPT).

Recently, as integrated circuit technology has improved, large capacity display memories have been developed. When using such a display memory (with a 4-bit data bus) and attempting to reduce the number of memory chips used to reduce the circuit size, the following problems occur. Since the data bus of a large-capacity display memory is 4 bits, only 4 bits of data can be read out with one display clock. Therefore, if data is to be obtained in units of 16 bits, four display clocks are required. As can be seen from the example in Figure 5, when four display memories were used, 16-bit data could be read out with two display clocks, but with a large-capacity display memory, it was possible to read out 16-bit data with double the number of display clocks. This means that there is no leeway in the period (CPT) during which the CPU 400 performs other processing. In the cycle steal method, most of one display cycle shown in FIG. 5 is spent reading data.

(Problems to be Solved by the Invention) As mentioned above, according to the conventional display memory control method,
If you use a large-capacity display memory (4-bit data bus) and try to reduce the number of memory chips used to reduce the circuit size, the data read period will become longer (decreased access efficiency), and the CPU will There is a problem in that there is no room for processing or writing data to the display memory.

SUMMARY OF THE INVENTION An object of the present invention is to provide a display memory control device that can improve the access efficiency even if the capacity of the data bus of the display memory is small.

[Structure of the Invention (Means for Solving the Problem) This invention includes a display memory storing display data, and a display data stored in the display memory being supplied via a data bus, and displaying data for one horizontal display period. a first line memory capable of storing display data for minutes, means for transferring read data from the display memory to the first line memory in synchronization with a system clock; a second line memory capable of storing display data read out from the memory; and a second line memory capable of storing display data read out from the memory; The device includes means for transferring data using a system clock, and a decoder that reads display data from the second line memory and decodes it into a read display signal in response to the display clock, and all accesses to the display memory are performed in synchronization with the system clock. , only reading of the second line memory is performed in synchronization with the display clock.

(Function) With the above means, direct access to the display memory is performed using the system clock of the CPU, so data can be written and read at high speed. Even when access is executed in this manner, since the first and second line memories are provided, time alignment with the display cycle and display clock on the display side can be easily obtained.

(Example) Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of the present invention. In Figure 1,
A central processing unit (hereinafter referred to as CPU) 100 is connected to a buffer circuit 102 via an 8-bit data bus 101, and this buffer circuit 102 is connected to a 4-bit data bus 103. The data bus 103 is
It is connected to a display memory 200 having a 4-bit data bus.

The display memory 200 stores, for example, dot pattern data (DP), display attribute data (CC), foreground color data (PC), and background color data (B) as explained in FIG.
G) is stored, and only the data is read by accessing in synchronization with the system clock of the CPU 100.

Further, the data bus of the display memory 200 is connected to the data attribute processing circuit 104. Data attribute processing circuit 10
4 can transform dot pattern data (DP) according to display attribute data (CC). Output data from the data attribute processing circuit 104 is transferred to the first line memory 105 by the system clock. here,
Once the display data for one horizontal display period has been accumulated, it is transferred to the second line memory 106 at high speed during a non-display period, also by the system clock, prior to the display period of the display (receiver). The display data in the second line memory 106 is then decoded by the RGB decoder 107 in synchronization with the display clock on the display side, and output as R, G, and B signals for display.

FIG. 2 is a timing chart of the circuit of the above embodiment. This display memory control device performs write and read access to the display memory 200, display attribute processing, first line memory 105. All data transfers to the second link memory 106 are performed at high speed using the system clock (FIG. 2(a)) used by the CPU 100.

Therefore, as shown in FIG. 2(b), the read data from the display memory 200 on the data bus 103 is transmitted to the CPU 100 regardless of the display clock (FIG. 2(e)).
The information is transferred to the display attribute processing circuit 104 under the initiative of .

The data period CPT and the shaded area in FIG. 2(b) are C
This is a period in which the access operation of the PU 100 has a margin,
Using this period, the CPU 100 stores the display memory 200.
You can write data to and perform other processing. The display attribute processing circuit 104 has an input bus (4-bit capacity f).
f1), dot pattern data (DP), display attribute data (CC), foreground color data (FG), and background color data (BG) are input.

Here, the display attribute processing circuit 104 processes display attribute data (
The dot pattern data (DP) can be transformed in accordance with the CC). For example, display attribute data (CC)
If the dot pattern data (DP) is indicative of flashing or flashing, the operation to output or invert the dot pattern data (DP) will be automatically switched, and if it is indicative of concealment, all the dot pattern data (DP) will be output to all “1°” or all “0”. As a result, as shown in FIG. 2(d), the data transferred to the first line memory 105 may contain less attribute data.
5 to the line memory 106 (
In FIG. 2(f), the data transfer load on the CPU 100 is also reduced, and the load on the decoding process performed in the RGB decoder 107 is also reduced. Note that if the attribute processing circuit 104 is not provided, the RGB decoder will perform attribute processing similar to the conventional one.

FIG. 3 shows the first and second line memories 105 and 10.
6 shows an example of a memory map.

This example assumes that there is a 256-bit dot pattern in one horizontal display period, and the dot pattern is 64 words x 1.
2 bits - 768 bits.

In the above embodiment, the block coloring type display memory control device has been described as an example, but the present invention is not limited to this, and can be used for various types of display memory control. Further, the present invention does not necessarily require an attribute processing circuit.

[Effects of the Invention] As explained above, the present invention can improve the access efficiency even if the capacity of the data bus of the display memory is small. This is also effective in reducing the number of memory chips used and the circuit requirements. Furthermore, since there is more leeway in CPU access, it is possible to improve the functionality of software for executing other processes.

[Brief explanation of drawings]

FIG. 1 is a configuration explanatory diagram showing one embodiment of the present invention, FIG. 2 is a timing chart shown to explain an example of the operation of the circuit in FIG. 1, and FIG. 3 is a memory map of the line memory in FIG. 1. FIG. 4 is a block diagram showing a conventional memory control circuit, and FIG. 5 is a timing chart shown to explain an example of the operation of the circuit shown in FIG. 100...Central processing unit i & (CPU), 1
02... Buffer circuit, 104... Display attribute processing circuit, 105... First line memory, 106... Second
line memory, 107...RGB decoder, 200
...display memory. Figure 1 Applicant's agent Patent attorney Takehiko Suzue 64 words x 12 bits = 768 bits

Claims (1)

[Claims] A display memory storing display data; and a first display memory to which the display data stored in the display memory is supplied via a data bus and capable of storing display data for one horizontal display period. a line memory, means for transferring read data from the display memory to the first line memory in synchronization with a system clock, and storing display data read from the first line memory. a second line memory capable of displaying data stored in the first line memory for the second line memory prior to a display period;
means for transferring data using the system clock; and a decoder that reads data from the second line memory and decodes it into a readout display signal in response to a display clock, and synchronizes all accesses to the display memory with the system clock. A display memory control device characterized in that the second line memory is read out in synchronization with a display clock.