DE3588174T2 - Video system - Google Patents

Description

The invention relates to electronic computer systems and the like, and more particularly to an improved method and apparatus for achieving high resolution video playback.

It is common to display the output of a computer as an image on the screen of a cathode ray tube or the like. The screen is actually made up of a collection of dots or "pixels" and the image is therefore created by selecting and illuminating those pixels required to form the desired image. If the image sought to be displayed is only a simple pattern of numbers or other symbols, this can be achieved with a relatively limited number of pixels. However, if a more complex image (with a higher resolution) is desired, then a screen having a much larger number of pixels must be selected.

It is understood that each pixel used to construct the image is illuminated by its own output data signal from the processing section of the computer and that an increase in resolution requires a screen with a larger number of pixels.

In US-A 4 298 931, which is the basis of the preambles of claims 1 and 7, a text character reproduction system is proposed with several RAMs connected in parallel. Each RAM is subjected in succession to the processes of data reading/writing by a CPU, reading out the reproduction data and refreshing, the phases being staggered so that a RAM is always available for reading out the reproduction data.

EP-A 0 080 043 proposes a video system in which new image data is written directly to both a line buffer and the main video memory, so that the display can be supplied with data from a line buffer while the video memory is being updated.

The invention provides a video system comprising: a data processor for manipulating image pixel data corresponding to a video image in accordance with program instructions; video system control means including a refresh address counter for storing an address for memory refresh; a multiplexer for passing addresses received from the data processor over a first address bus, addresses stored in the refresh address counter, or addresses received from a control register to the second address bus; display means for generating an operator-perceivable visual display corresponding to image pixel data stored in a video memory, the display comprising a plurality of horizontal lines corresponding to image pixel data retrieved from the video memory by addresses received from the control register; characterized in that the video system further includes: memory cycle control means for sequentially generating memory refresh requests during an active portion of the horizontal lines and display update requests during a blanking portion of the horizontal lines; wherein the multiplexer is operable to execute a memory access cycle in which addresses received from the data processor via the first address bus are switched through to the second address bus in response to a memory access request; wherein the multiplexer is further operable to execute a memory refresh cycle in which addresses stored in the refresh address counter are switched through to the second address bus in response to a memory refresh request, the addresses stored in the refresh address counter being refreshed after each memory refresh cycle; wherein the multiplexer is further operable to execute a display refresh cycle in which addresses received from the control register in response to a display refresh request are passed through to the second address bus; and an arbiter for controlling the memory cycle control means to execute only one of a memory access cycle, a memory refresh cycle and a display refresh cycle in accordance with received memory access requests, memory refresh requests and display refresh requests, the arbiter being arranged to assign the priority of the display refresh requests during the horizontal blanking interval of each line, the priority of the memory access requests during an earlier portion of the active portion of each horizontal line and the priority of the memory refresh request during a later portion of the active portion of each horizontal line.

The invention also provides a video interface comprising: means for establishing an electrical connection with a data processor for manipulating image pixel data corresponding to a video image in accordance with program instructions and with a video memory for supplying image pixel data to a display means for producing a corresponding display perceivable by an operator; a multiplexer for switching addresses received from the first data processor via a first address bus, addresses stored in a refresh address counter or addresses received from a control register to a second address bus; and characterized in that the video interface further includes: a memory cycle control means for sequentially generating memory refresh requests during an active portion of a horizontal line and display update requests during a blanking portion of the horizontal line; the multiplexer being actuated to execute a data processor memory access cycle in which addresses received from the data processor over the first address bus in response to a memory access request are passed through to the second address bus; wherein the multiplexer is further operable to execute a memory refresh cycle in which addresses stored in the refresh address counter in response to a memory refresh request are passed through to the second address bus; wherein the multiplexer is further operable to execute a display update cycle in which addresses received from the control register in response to a display update request are passed through to the second address bus; and an arbiter controlling the memory cycle control means to execute only one of a memory access cycle, a memory refresh cycle and a display update cycle in accordance with received data processor memory access requests, memory refresh requests and display update requests, the arbiter being arranged to assign priority to display update requests during the horizontal blanking interval of each line, priority to data processor memory access requests during an earlier portion of the active portion of each horizontal line and priority to memory refresh requests during a later portion of the active portion of each horizontal line.

The video memory is preferably a dynamic multiport random access memory having an X-Y addressable memory array organized into multiple color planes. The video system controller performs an automatic refresh of this dynamic random access memory.

The video system control means preferably includes a row address buffer, a column address buffer and an XY address logic. The video system control means multiplexes the various video memory access requests with a priority circuit. This is done with a first part operating synchronously with the video memory and a second part operating synchronously with the microprocessor. This allows the processor to run at a rate independent of the pixel rate of the video display. The transfer operations in the video system control means are preferably controlled by the use of a programmable state machine which manipulates inputs to a logic array.

The video system control means supports the multi-level memory arrangement. A row address override circuit allows data to be written to multiple memory levels simultaneously. An equal number of output logic circuits to the number of memory levels generates write enable signals that independently allow data to be loaded into selected memory levels. The video storage means also controls an external shift register used as a buffer between the video memory and the display device.

In addition to controlling a special VRAM, the video controller can also control standard dynamic RAM.

These and other features/advantages arise from the description in conjunction with the figures, as listed below.

BRIEF DESCRIPTION OF THE CHARACTERS

Figure 1 is a block diagram incorporating a video controller according to the invention;

Figure 2 is a functional block diagram of the video controller of Figure 1;

Figure 3 is a circuit diagram of circuit blocks used to implement the functions of Figure 2;

Figure 4 is a block diagram of the system block of Figure 3;

Figure 5 is a block diagram of the video block of Figure 3;

Figure 6 is a block diagram of the DA-ST block of Figure 3;

Figure 7 is a block diagram of the CRT block of Figure 3;

Figure 8 is a schematic diagram of the control block of Figure 4;

Figure 9 is a schematic diagram of the cycle generator of Figure 4;

Figure 10 is a schematic diagram of the RAS decoding block of Figure 4;

Figure 11 is a schematic diagram of Figure 7;

Figure 12 is a schematic diagram of the memory port block of Figure 4;

Figure 13 is a schematic diagram of the refresh block of Figure 4;

Figure 14 is a schematic diagram of the Ready/Hold block of Figure 4;

Figure 15 is a schematic diagram of the video block of Figure 7;

Figure 16 is a schematic diagram of the vertical counter of Figure 7;

Figure 17 is a schematic diagram of the horizontal counter of Figure 7;

Figure 18 is a schematic diagram of the horizontal counter of Figure 7;

Figure 19 is a schematic diagram of the base register used in Figures 16, 17 and 18;

Figure 20 is a schematic diagram of the SRDAT block of Figure 7;

Figure 21 is a schematic diagram of the FS decoding block of Figure 3;

Figures 22 to 26 are schematic diagrams of the XY register block of Figure 3;

Figures 27 to 29 are schematic diagrams of the control register block of Figure 3;

Figure 30 is a schematic diagram of the input terminal block of Figure 3;

Figure 31 is a schematic diagram of the data connector block of Figure 3;

Figure 32 is a schematic diagram of the data status block of Figure 3;

Figure 33 is a schematic diagram of the double clocks used in the video system controller;

Figure 34 is a schematic diagram of an embodiment of the playback memory;

Figure 35 is a block diagram of a microprocessor of Figure 1;

Figures 36 and 37 are alternative embodiments of a video system; and

Figure 38 is a sketch of the data transfer cycle;

DETAILED DESCRIPTION OF A PARTICULAR EMBODIMENT

Referring now to Fig. 1, there is a block diagram of an embodiment of the video system controller according to the invention. The blocks shown in Fig. 1 comprise a microprocessor 1, a video system controller 3 and a playback memory 5. As described, for example, in U.S. Application 567,040 (US-A-4 639 890), assigned to the assignee of the present invention. The output of the playback memory 5 is connected to a shift register 7 which shifts data to an optional digital-to-analog converter 9 for delivery via a bidirectional data bus 9A to a suitable monitor or television screen 11 or other output or input device. In addition, a dynamic system RAM 19 is provided for storing data and/or instructions for processing by a microprocessor 1. The microprocessor 1 receives input data from a port 15 and supplies the data to a bidirectional bus 17 which connects the microprocessor 1 to the video system controller 3, the playback memory 5 and the dynamic system RAM 19. In addition, the microprocessor supplies address information to the video system controller 3 and a second port 15A which, together with the port 15, is connected to a port device such as a keyboard as well as other peripheral devices which can be used by the system. The microprocessor 1 supplies address information to the video system controller 3 via an address bus 21. The interface between the microprocessor 1 and the video system controller 3 is operated by means of the bidirectional bus 23 via which the control signals are transferred between the microprocessor 1 and the video system controller 3. The output signal of the video system controller 3 is in the form of address information and control signals are supplied to the display memory 5 and the dynamic system RAM 19 via an address bus 25. Control of data transfer to and from the display memory 5 and the dynamic system RAM 19 is provided by the video system controller 3 via the control bus 27. In addition, the CRT monitor 11 is supplied with a synchronization and blanking signal via a synchronization line 29. The microprocessor 1 executes the program instructions which are either supplied to it via the data bus 17 or which are stored in its own internal memories. In response to these program instructions, control signals and data are transmitted in the form of commands to the video system controller 3. The video system controller 3 performs four basic functions. These functions are: (1) it allows the microprocessor 1 virtually uncontested access to the dynamic system RAM 19 and the display memory 5; (2) it automatically generates the refresh cycles required to maintain the data stored in the dynamic system RAM 19 and the playback memory 5; (3) it performs the playback update cycles required to periodically load new video data into the playback memory 5 and in particular into the shift registers contained in the playback memory 5; (4) it generates the video synchronization and blanking signals required to control the video monitor.

The display memory 5 includes a dot pattern RAM unit or chip with enough cells to accommodate each screen display intended for the CRT monitor 11, and further includes a serial shift register having a plurality of taps at locations corresponding to various preselected columns of cells in the display memory 5. In addition, provisions are made to select taps to unload only a portion of the shift register containing the bits of interest, thereby effectively eliminating unused portions of the shift register and reducing the time for transferring the bits of interest. Data to the CRT monitor 11 is reduced. The optional high-speed shift register 7 is interfaced via lines 31 with the internal shift register ports of the playback memories 5 and shifts the data to an optional digital-to-analog video signal converter 9 or other output devices and input devices. The CRT monitor 11 displays the information fed to it via the data bus 17 from the microprocessor 1 under the control of the video system controller 3, which handles the data transfer from the playback memory 5 to the CRT monitor via the optional shift register 7 and the digital-to-analog converter 9. The timing for the system is generated by the system clock 33, which provides the shift and load clocks to the system and in particular to the video system controller 3, the playback memory 5 and the shift register 7.

Referring now to Fig. 2, there is a functional block diagram of the video system controller 3 of Fig. 1, wherein a multiplexer 49 accepts addresses from both the microprocessor 1 via an address bus 21 and from a refresh address counter 45 used to refresh the memory cells of the display memory 5, from an X-Y address register 43, and the shift register address from the internal control and video register 39. The addresses are converted to a 9-bit row or column address required by the display memory 5 and/or the system DRAM 19. The address provided by the microprocessor 1 is divided into two groups, RA0-RA8, which are the row address bits applied to a row address latch 47 via a data bus 21R, and the address bits CA0-CA8, which are the column address bits applied to the column address latch 41 via a data bus 21C. Of course, the symbol CA stands for the column address bits. An arbiter/ready logic 37 also determines the source of the addresses applied to the display memory 5 via a multiplexer 49 and the data bus 25, as it provides the microprocessor 1 with a Signal READY/HOLD as part of the control signals carried over data bus 23. The control signals used to control multiplexer 49 and the subsequent multiplexing of row/column addresses as they are output on data bus 25 in the form of MA0-MA8, which stands for memory address, are generated by a memory cycle controller 35. The row and column address inputs from microprocessor 1 are latched into a row address latch 47 and a column address latch 41, respectively, by the falling edge of control signal "ALE" before being multiplexed to display memory 5.

Both the X-Y registers 43 and the control and video registers 39 are programmable registers that the microprocessor 1 can access directly.

The data bus 17 in the embodiment of Fig. 2 is only 8 bits wide, with each register of the XY address register 43 and the control and video register 39 being 16 bits wide. Thus, the microprocessor 1 accesses the high and low order bits of the registers in separate cycles. The bit value entered on the column address bit line, which is part of the address bus 21C, determines whether the high or low order byte of the register is addressed. Access to an internal register is enabled by setting the appropriate function code selection, which is indicated at the beginning of the cycle by the function selection lines FS0-FS2. Selection of one of the registers, which number 18 in the embodiment of Fig. 2, is determined by the entry of a 5-bit code on data lines CA6 through CA2, which are part of the address bus 21C, during access by the microprocessor 1. The value entered at CA1 selects the high or low bytes of the register. The state of the read and write line, input signal R/W-, must be valid before and during the time in which the low byte CEL of the column address enable, which is a control line present on data bus 23 becomes low order to determine whether the register access is a read or a write access. The control and video registers include video timing registers, display update registers and control registers. The video timing registers are programmed to generate the horizontal and vertical synchronization and blanking signals needed to control the CRT monitor 11 of Fig. 1. The values loaded into these registers are customized to meet the particular screen resolution and timing requirements of the CRT monitor 11. Both interlaced and non-interlaced scanning operation are possible. The video system controller can be programmed to latch an externally generated synchronization signal, for example for an application where the graphics image generated in display memory 5 is to be superimposed on an external video signal.

The display update registers are required because the video system controller 3 generates the display update cycles required to periodically refresh the video display. The display update registers maintain the row and tap point address output to the display memory 5 during each display update cycle. The display update cycle is a special type of access to the display memory 5 which transfers 256 bits of data between the memory cell array and the shift register within each display memory 5 in the memory system. In graphics applications, the display update cycle occurs during horizontal blanking to load the shift register with a new load of data from the memory cell array.

During the subsequent active horizontal scans, the contents of the shift registers within the playback memory 5 are clocked out of the serial output terminals and displayed on the CRT monitor 11. The Video system controller 3 can be programmed to transfer data in the opposite direction, ie from the shift register to the memory cell array, all of which are contained in the display memory 5. This mode of operation is suitable for capturing video images generated externally and then clocked into the shift register through the serial input during the preceding active horizontal scan.

The display control registers contain a start display address corresponding to the location within the display memory 5 that is displayed at the top left of the screen. The amount by which the display address is incremented between display update cycles is also programmable. These programmable features include (1) specifying the number of scan lines between successive display update cycles; (2) specifying the direction (read or write) of data transfer; (3) specifying that the horizontal sync Hsync and vertical sync Vsync lines are either inputs or outputs; and selecting either an interlaced or non-interlaced picture. These features are controlled by the values loaded into the control registers and the video timing registers. In the embodiment illustrated by the block diagram of Figure 2, there are two control registers which control the specification of a number of programmable features including the various operating modes supported by the video system controller 3, which have already been mentioned. Each active register can be both written to and read by the microprocessor 1. Also included in this block of registers are the status registers which can be read but not written to.

A status register contains three active bits. One of these bits indicates that a certain horizontal scan has been displayed on the screen. The other two Status bits indicate error conditions. One bit indicates that a pending DRAM refresh cycle request has been locked out too long, and the other bit indicates that a pending replay update cycle request has been blocked too long. When enabled, these status conditions cause interrupt requests to be sent to microprocessor 1.

The X-Y address register 43 maintains the X-Y addresses, which represent the concatenation of the X and Y coordinates of a location on the graphics screen displayed by the display monitor 5. The video system controller 3 can be configured to generate an internal 20-bit X-Y address instead of the address generated by the microprocessor 1. This feature is useful when extending the address range of some processors. Even if the microprocessor 1 has sufficient address range to directly access every pixel on the screen, hardware updating of the X-Y address between accesses is likely to be more efficient than similar functions performed in the software of the microprocessor 1. The X-Y portion of the address can be independently incremented, decremented or cleared under the control of the input signals CA4-CA1 provided by the microprocessor 1 during each access to the X-Y address register 43. The incrementing takes place following the completion of the access in preparation for the transfer of the next X-Y address to the X-Y address register 43. The X-Y addressing feature of the video system controller allows internal algorithms such as line drawing or character drawing routines to access a row of adjacent pixels on the screen at hardware-assisted speeds.

An arbiter 37 is responsible for generating requests for memory and register access cycles. If more than one request is pending, the arbiter is responsible for deciding which request to process based on based on the relative priorities of the completed requests. Since the display update and DRAM refresh cycles generated internally by the video system controller 3 typically use less than 2% of the available memory cycles, the arbiter is likely to grant a request for a memory register access from the microprocessor 1 immediately. However, if a display memory 5 refresh request has been pending for some time, its priority is increased to ensure that the refresh cycle occurs before the memory data is lost. The arbiter holds the microprocessor 1 back by means of the READY/HOLD- signal.

A memory cycle generator 35 is responsible for performing the memory cycles assigned to it by the arbiter/ready logic 37. The memory cycle generator controls the multiplexer 49 and generates the timing for control signals and addresses during a memory cycle. The memory cycle generator 35 can perform a direct microprocessor memory access, x-Y addressing, a replay update, a refresh of the replay memory 5 and the system dynamic random access memory (DRAM) 19, a shift register read cycle, and a shift register write cycle.

The video system controller may perform refresh cycles for the display memory 5 and the system DRAM 19 at regular intervals. The refresh address counter 45 generates a 9-bit row address output signal during a refresh cycle. This includes the refresh address counter 45 determining the number of refresh cycles per horizontal scan line. The timing for this transfer is shown in Fig. 38.

A refresh address register within the refresh address counter 45 is inaccessible to the microprocessor 1, maintains the current row address and is each memory refresh cycle. The enablement of the refresh cycles and the frequency of the refresh cycles are determined by three control register bits within the control register 39C.

The CRT controller 57 also includes a 4-bit scan line counter used to count the number of active horizontal scan lines output to the CRT monitor 11 between successive display update cycles. Any number of scan lines from 1 to 16 can be specified. For example, in a system in which each display update cycle transfers enough data to put the video shift register into the display memory 5 for two complete scan lines, a display update cycle is only needed at the beginning of every other scan line.

Fig. 38 shows four consecutive scan lines on the CRT monitor 11 and is used to indicate the locations at which various activities of the video system controller 3 take place. Line segments 901A through 901D represent the active portion of each horizontal scan line. Intervals 902A through 902D represent the blanked portion of each horizontal scan line. The microprocessor 1 may request a memory access at any time and the video system controller 3 will then grant the access and perform the memory cycle based on arbitration logic within the VSC (video system controller). At certain times during the raster, two types of cycles are generated by the VSC. During the interval designated 902A, 902B, 902C, 902D, the video system controller 3 performs a display update cycle, also known as a shift register reload cycle. This causes a shift register transfer to take place in the video memories 5, which consists in displaying data on the next scan line. The beginning of the intervals 901A-D represents the end of the horizontal scan interval. At this moment the video system controller begins performing refresh cycles for all memories in the system. Up to point 903A-D on each scan line, memory access cycles requested by the microprocessor 1 are given priority over internally requested refresh cycles. Halfway along the active scan line, designated by 903A-D, refresh cycles are given priority over microprocessor requested cycles. Playback update cycles are always given priority over microprocessor requested cycles.

Referring now to Fig. 3, is a circuit diagram of the circuit blocks used to implement the functional blocks of Fig. 2 on a single metal oxide silicon chip with field effect transistors.

The system 53 includes the memory cycle generator 35, registers 39A which are part of the internal control and video registers 39 of Fig. 2, the multiplexer 49, the refresh counter 45 and the arbiter/ready logic 37. A video block 57 completes the functions of both the CRT controller 51 and the internal video registers 39C. The XY logic block 43 corresponds to the XY registers 43 of Fig. 2. The FS decode logic 63 includes not only the row and column address latches 41 and 47, but also the function select decode logic which decodes the function select input signals FS (2-0). The CA decode logic 55, which is part of the internal control and video registers 39 of Fig. 2, contains the decode circuits associated with the line address latch 41. The remainder of the control registers are contained in the control register block 39C of Fig. 3, and input terminals 59 and a data status 61 contain the input logic for receiving data from the microprocessor 1 of Fig. 2 and for providing the status to the microprocessor 1 of Fig. 1 as well as providing the control signals necessary to effect bidirectional data transfer between the microprocessor 1 and the display memory 5 and the System DRAM 19 are required.

Table 1 provides a definition for the symbols used in Fig. 3 to describe the various signals shown in the figure. TABLE 1 INPUT/OUTPUT CONNECTIONS FOR THE VIDEO SYSTEM CONTROLLER 3

In Fig. 4, the system 53 contains the logic to implement the memory cycle generator 35. This is divided into several logic components that include the row address selection RAS, a decoding logic 65, the a row address select operation, and memory terminals 69 which control the loading of data through memory generated by a memory cycle generator 67; the memory cycle 67 generates the memory cycle transfers to handle the data transfer between the microprocessor 1 and the display memory 5 or the system DRAM 19; and a controller 71 generates the internal control signals used by the video system controller 3. Also included in the system block diagram is the arbiter/ready logic 37, as well as the refresh address counter 45 which is part of the system block diagram 53.

Fig. 5 is a circuit diagram of the video block 57 of Fig. 3 and includes the CRT controller 51 which includes the CRT logic 73 which generates the CRT signal such as both horizontal and vertical blanking and synchronization and supplies these signals to the video terminals 75 which convert these signals into signals whose voltage and current levels the CRT monitor 11 can accept. As previously discussed, in the preferred embodiment the display memory 5 has built in shift registers into which the microprocessor 1 can write directly. Control of the data transfer to the shift register is provided by the SR logic 79 which is part of the video block 57.

Fig. 6 is a circuit diagram of the DA-ST block 61 of Fig. 3. It contains data terminals for receiving the data and converting it into logic levels that the video system controller 3 can accept. In addition, as part of the interface connection to the microprocessor 1, the status of the playback memory 5 and the system memory 19 is generated by a status block 81 of Fig. 6.

Referring now to Fig. 7, is a circuit diagram of the CRT block 73 of Fig. 5. The CRT block includes the vertical control logic 97, the horizontal control logic 95, a horizontal counter 93, and a vertical counter 99.

In addition, there are 9 programmable registers which the microprocessor 1 can both write and read via an 8-bit data port 18 provided by the DA-ST block 61 to the video block 57. Each register in the embodiment shown in Fig. 7 is 12 bits wide. The microprocessor 1 accesses both the programmable registers within the CRT block 73 and other areas of the video system controller 3 by means of special read and write cycles. A register access cycle is selected by setting the function select input signals Fs2-FS0 to one of two 3-bit codes, either 000 or 010. If there are 18 programmable registers in the video system controller 3 and only 9 in the CRT block 73, the information described here is applicable to all 18 programmable registers. One of the 18 registers is selected by a 5-bit register address input to column address input CA6-CA2. Binary codes 00000 through 10001 are addresses of valid registers. Codes 10010 through 11111 are reserved. The high or low byte of the register is selected by the value entered at CA1. If CA1 is zero, the low byte is selected; otherwise, the high byte is selected. In Fig. 7, the logic represented by CRT block 73 generates the horizontal sync, vertical sync, and blanking output signals needed to control CRT monitor 11. These signals are output linearly to HSYNC-VSYNC-BLANK. The video system controller can be programmed to generate synchronization and blanking signals appropriate for the particular CRT monitor 11 and a screen resolution selected for the desired application. In addition, the video system controller 3 can be programmed to interrupt the microprocessor 1 at the end of any horizontal scan line by driving an interrupt signal INT- to its active-low level through control of the INTV signal present on line 23. These signals are programmed by means of the parameters entered into the 9 Registers of the CRT block 73 are loaded. These registers include the horizontal end synchronization registers 89, HESYNC; horizontal end blanking register 87, HEBLNK; horizontal start blanking register 85, HSBLNK; horizontal total 91, HTOTAL; vertical end synchronization register 109, VESYNC; vertical end blanking register 103, VEBLNK; vertical start blanking register 105, VSBLNK; vertical total 101, VTOTAL; and vertical interrupt register 107, VINT. The two additional registers, the horizontal counter 93 and the vertical counter 95, are used in the generation of the video timing signals.

The horizontal counter 93 is a counter whose contents are compared with the horizontal desync register 89, the horizontal end blanking register 85, the horizontal start blanking register 85 and the horizontal sum register 91 to determine the boundaries of the horizontal sync and blanking intervals. Similarly, the vertical counter 99 is a counter whose contents are compared with the vertical desync register 109, the vertical end blanking register 103, the vertical start blanking register 105 and the vertical sum register 101 to determine the boundaries of the vertical sync and blanking intervals. The contents of the vertical interrupt register 107 are compared with the vertical counter 99 to determine when a particular scan line is output to the CRT monitor 11. The microprocessor 1 may be interrupted when this condition is detected.

In performing a function as the controller for the playback memory 5 and the system DRAM 19, the playback update controller, and the timing controller of the CRT monitor 11, the video system controller 3 must perform several types of access cycles. Some of these types of cycles are initiated by the microprocessor 1, while others are automatically initiated by the video system controller. The memory cycle generator 35 performs most of the access cycles. And in particular, the cycle generator 67, shown in Fig. 8, performs the following cycles:

direct cycles initiated by microprocessor 1 ;

an indirect cycle of the x-Y register 43, which is also initiated by the microprocessor 1;

Refresh cycles of the playback memory 5 and the system DRAM 19, which are automatically initiated by the video system controller 3;

a playback update cycle automatically initiated by the video system controller;

and shift register transfer cycles including shift register writing and shift register reading for transferring data to and from the shift register within the playback memory 5.

The control circuit 71 handles the requests for all internal cycles including the CRT monitor display update cycles and the memories 5 and 19 refresh cycles. The horizontal blanking signal tells the control logic 71 the location of the raster on the CRT for the display update or refresh request. This request is transferred to the cycle generator 67 to execute the display update cycle or the refresh update cycle.

Fig. 8 is a schematic diagram of the control block 71 and includes two synchronization circuits 111 and 113. The synchronization circuit 111 synchronizes the horizontal blanking signal with the internal clock used to control the logic within the system block 53. The CRT monitor 11 uses a different clock system than the system 53, and as a result, the horizontal blanking signal and the horizontal stop blanking signal supplied to the system 53 from the video block 57 use a different clock which must be synchronized with the internal clock used to operate the controller 71. In addition, the controller 71 includes a Mealy model state machine consisting of a plurality of programmable logic devices 115 and an OR gate 117 and a latch circuit 119. Each output of each stage in the embodiment of Fig. 9, in which there are four stages 121, 123, 125 and 127, is supplied to column lines A, B, C and D, the complements of which are supplied to column lines XA, XB, XC and XD. Additional controls are provided to the programmable logic devices 115 in the row lines on data lines 129. The Mealy state machine also includes a PLA 133 and decode logic 135 at point 131. The output of the control circuit is provided to cycle generator 67 via data bus 137, to ready/hold logic via data line 139, and to data status block 61 via data bus 141. A unique feature of the control logic is that the state machine is designed for "N" channel metal oxide silicon field effect transistor logic circuits which use a standard cell which is repeated many times and which is programmed using a transistor 143 which determines the operation of the state machine used to implement control block 71.

The logic gates 117 are implemented with a plurality of input conductors 217. These conductors may be connected to a large number of outputs from the programmable logic device 115, shown at 219, or to a minimum number of inputs to the NOR gate 117, as shown at 221, or to just a single line with all of the inputs of the NOR gate connected together, as shown at 223, to enable the implementation of a standard cell NOR gate.

The arbiter and ready/hold logic 37 is operatively based on the cycle generator 67 in which logic circuits 151 of Fig. 8 determine the priority of operation as to whether it is internal or external to the video system controller 3. EXT signals and complementary XEXT signals based on the ALE signal represent a request from the microprocessor 1 for a memory access cycle. ALE is latched up to the cycle generator by latch 153. In addition, circuit 155 provides buffering for the internal cycle request XINT. The cycle generator 67 includes a Moore model state machine consisting of a first stage 161, a second stage 165, a third stage 167, a fourth stage 169, a fifth stage 171, a sixth stage 173, and a seventh stage 175. Each stage includes a PLA 115, an OR gate 117 and a latch circuit 119, with the output of each stage being applied to row lines A through G and the complementary signal being applied to lines XA through XG. The output signals are also decoded by logic 177 which includes a PLA 179 and decode logic 181. Logic 177 provides an indication on data bus 183 that an external cycle is in progress and at 185 that an internal cycle is in progress. The W conductor indicates a write operation in which TRQE provides the enable to the shift register and the output enable of memories 5 and 19. REFINC provides the increment refresh to refresh logic 45 and REF2HR provides a transfer from the refresh counter to the refresh hold register included in the refresh logic of refresh block 45 of Figure 4. Data lines or outputs 185 are the controls for the address selects of the multiplexer 49 and generate SRRASEL which is a playback update row address selection. RACASEL are the row address, column address select lines used for playback update and refresh cycles. XYRASEL are the XY row address select lines, XYCASEL are the XY column address select lines and EXTCASEL are the external column address select lines. If none of these are active, then row address (RA) 21d is selected. Lines 187 provide the internal column address enable ICASEN and the external column address enable ECASEN. A row address enable RASEN is provided on data line 189. Data lines 191 select the source for the RAS decode logic 65 which includes the XY cycle XYCCL, the shift register cycle SRCCL and the refresh cycle REFCCL. In addition, line 193 is the completion line which indicates that an internal operation cycle has ended and the signal XYGO is the set enable for the XY register 43 and is present on data line 195.

Referring now to Fig. 10, there is shown a block diagram of the row address select decode circuitry represented by block 65 entitled "RAS Decode." The row address select override circuitry creates a mode of operation that allows data to be written to memory N times faster than without this mode. N is the number of memory planes within the system. For example, the playback memory 5 of Fig. 2 is configured in one embodiment to have four memory planes. For the video system control circuitry 3, four row address select planes are supported in the embodiment of Fig. 10. One embodiment is to label each of the four planes shown in Fig. 10 in areas 177, 179, 181 and 183. Writing to one plane produces an image in a primary color. Writing the same data to two planes produces a mixed color. Using the load address selection override feature allows one to write to both planes simultaneously. To do this, the RAS override bits in the control grid included in block 39C of Figure 3 are loaded with the binary value of the color. When one plane is written to using this feature, the other planes are also selected. The override feature Row address selection is also applied to shift register transfers. These shift registers are of course located within the display memory 5. This feature allows the screen of the CRT monitor 11 to be cleared four times faster since all four row address selection levels can be transferred in a single cycle. Prior to this invention, data was written to a memory bank or level in a single memory cycle. Drawing an object requires writing to each code or level individually.

The row address override logic is controlled by four bits programmed and stored in control register 39C by microprocessor 1 which selects which row address select output bit is forced active during the memory access cycle. These four bits are RASOR(3-0). These four bits are linked to the function decode and R/W- signals to prevent memory read collisions. The row address override feature is enabled only for the following types of memory cycles: a microprocessor 1 random access write cycle, a microprocessor 1 requested shift register to memory transfer, and a microprocessor 1 requested memory to shift register transfer. The four linked bits are then linked to the row select zero and row select one bits to establish the row address select output selection. In Fig. 10, the row address select enable bit is brought from the cycle generator 67 to the row select decode logic and is represented by RASEN. This bit enables the four bits from the control registers previously counted by the OR logic 164 to the XRAS(3-0) outputs. In addition, NOR gates 162 and 163 decode the function being performed, be it the row address select from the function select decode circuit represented by RSA, the XXY from the XY register 43 indicating where the data is being written into memory, a shift register row address select SSRRAS from video block 47 and the extended control register row address select bits generated by control register 39C and represented by signal CRRAS. These signals are multiplexed by logic 161 and NOR gates 162 and 163 in conjunction with the appropriate cycle being performed, with their shift register cycle represented by signal SRCCL, a refresh cycle represented by signal REFCCL and an XY cycle represented by signal XYCCL. These signals, of course, originate from cycle generator 67 of Fig. 4 and are combined by logic gates 186, in addition to signal EHAE brought by control register block 39C. Decode block 63 generates the function select shift register signal represented by symbol FSSR and the RWB signal in which the four row select output bits are combined by logic gates 187. The function selection and read/W- signals are combined using the NOR gate 189.

11a and 11b are schematic diagrams of the multiplexer 49 which outputs the memory address to the memories 5 and 19. As discussed in connection with FIG. 2, the multiplexer 49 selects either the output from the row address latch 47, the refresh address counter 45, the XY address register 43 or the column address latch 61. These input signals are brought into the multiplexer 49 as signals XCAB which is the input from the column address latch 41 and XRAB which is the input from the row address latch 47, both of which are part of the FS decode block 63 of Fig. 3, the XXY signal which is the input from the XY register 43 of Fig. 3, the XSRRA which is the shift register row address which is part of the video block 47, and the XRACA which is the output of the refresh block 45 and the video block 57. The multiplexer in the embodiment shown includes 7 stages 250 in which the aforementioned signals are selected via pass transistors 251. and the output terminals 253. The cycle generator 67 provides the selection for each of the functions. EXTCASEL provides the column select, XYRASEL provides the XY row select function, XYCASEL is the column select of the XY register 43, SRRASEL is the shift register row address output select enable, and RACASEL is the refresh row address and shift register column address select enable. The OR combination of all of these functions provides a signal designated EXTRASEL which connects the RA address bus 21d to the output of the multiplexer 49 at the output terminal 25. The output terminal is a 9-bit terminal and the remaining two bits are represented in Fig. 11b by circuits 255 and 257. In addition, test logic for testing the VSC 3 is provided in area 261 and is enabled by the SCANOUTS signal which is brought into the multiplexer 49 from the cycle generator 67 at location 263 and by the video blanking signal SCANOUTV which is the output of the video block 57 which is fed to the multiplexer at 265. These two signals are the circuit of a scan path which serially connects everything else in accessible storage nodes within the VSC 3 and which is used during a test of the device.

The memory terminals 69, as shown in Fig. 12, provide the control signals for writing to the playback memory 5, whose outputs are the write command XW, the TRQE command and the two column address strobe signals XCASHI and XCASLO. The high and low column address enable signals provided by the input terminals 59 are combined by ICASEN and ECASEN, both of which are generated by the cycle generator 67 at outputs XCASHI and XCASLO.

The video system controller 3 is configured to perform refresh cycles for the playback memory 5 at regular intervals. The refresh counters (Fig. 13) contained in the refresh address counter 45 generate a 9-bit row address output during refresh cycles. A refresh data block counter, which is not accessible to microprocessor 1, determines the number of refresh cycles per horizontal scan line. A refresh address register, also not accessible to microprocessor 1, maintains the current row address and is incremented following each refresh cycle. The enabling of refresh cycles and the frequency of refresh cycles are determined by three control register bits within video system controller 3. Eight of the nine-bit row addresses are provided by circuit 237 of Fig. 13A, which includes a refresh counter block 270 and a holding register 271. Upon command from the cycle generator via the SRCCL signal, counter 270 is enabled to multiplexer 49 via bus XRACA, which connects refresh address counter 45 to the multiplexer. Fig. 13B provides the remaining counter status 279 associated with counter 270. A Mealy model state machine shown at 275 in Fig. 13C, which as previously mentioned is not accessible to the host computer, determines the number of refresh cycles per horizontal scan line that will be performed. Its output signal REFRQ is provided to control logic 71 and indicates that additional refresh cycles must be performed during the current scan line.

The refresh address register 270 maintains the current row address and is incremented following each refresh cycle for the playback memory 5 and the system memory 19. The cycle generator 67 performs the arbitration to determine the priorities of the memory cycles to be established.

The Ready/Hold logic 37 (Fig. 14) provides the READY/HOLD signal which informs the microprocessor of the current status of the cycle generator 67. Several operating modes are available, programmed using the control register bits RHMODE (1-0) and RH(2-0). These Modes are READY, WAIT and HOLDMODE. In the ready mode, microprocessor 1 programs a certain number of wait states desired during a microprocessor-initiated cycle by loading RH(2-0). When the cycle requested by microprocessor 1 begins, circuits 293 provide a timing sequence which, when complete, informs the host that the cycle is complete by asserting the READY/HOLD output signal. If an internal cycle is in progress or a cycle previously requested by the microprocessor is still in progress when microprocessor 1 requests another cycle, then the previous cycle must complete. The wait mode does not include a programmable wait state, but simply informs the microprocessor that its cycle has been started by asserting the READY/HOLD output signal. When the ready/hold logic is programmed to be in the hold mode, the VSC 3 must issue a request for the microprocessor 1 to "hold" because it is time for the VSC 3 to perform a refresh cycle or a shift register reload cycle. The microprocessor acknowledges the hold request by producing a logic zero level at the XHOLDBACK input. When programmed to be in either the ready or hold mode, the active logic level of the READY/HOLD output signal during a reset is programmable by the state of the XHOLDBACK input signal. This concludes the discussion of the system block of Fig. 3 and the associated circuits shown in Figs. 4 through 14.

The video block 57 (Fig. 15) is used to generate the horizontal synchronization HSYNC, vertical synchronization VSYNC and blanking signals used in a dot pattern graphics system to drive the CRT monitor 11. These signals are synchronous to the video input clock VIDCLK.

The signals output at the HSYNC-, VSYNC- and VLANK- connectors are transmitted through eight Video timing registers. The illustrated vertical control logic 97 includes several state machine cells 301 which are a PLA 115, a logic gate 117 and a latch 119. The standard cells 301 of the state machine are connected in a counter figure configuration as shown in Figure 15 and provide a sequence of logic signals which select the vertical counter. When the counter reaches the value in the selected timing register, the vertical control state machine advances to the next timing register. The vertical counter register 99 counts the horizontal lines in the video displays and serves as a timing basis for setting the boundaries of the vertical sync and blanking intervals. The contents of the vertical counters are compared with the values in the vertical timing registers to separate the vertical sync and blanking intervals. The count is incremented at the beginning of each horizontal sync interval, with one exception.

This exception is that during the vertical front porch and sync intervals of an old field in an interlaced field, the vertical counter increment occurs in the middle where the count and horizontal counter 95 are equal to half the value in horizontal total register 91. Vertical counter 97 is reset to zero upon reaching the value in vertical total register 101 on the next edge of Vid 1k after a high-low transition on an active reset signal forces the vertical counter to zero. This interval can be read by microprocessor 1 during the intervals between increments, but it cannot be written to it. Normally, multiple read cycles are used to access vertical counter 97. Two consecutive reads returning the same data information indicate that microprocessor 1's access is in an interval between increments.

Fig. 16 is a schematic diagram of the vertical counter 99 and provides two counter stages 303 and 305. The first counter stage 305 provides 8 bits of data and is repeated eight times, and the second stage 303 provides 4 bits of data so that there is a maximum of 12 bits stored in the vertical counter.

Fig. 17 is a schematic diagram of the horizontal control circuit 95 in which the control signals for controlling the horizontal registers 85, 87, 89, 91 and 93 are generated.

Fig. 18 is a schematic diagram of the horizontal counter 93. The horizontal counter is a 12-bit counter divided into two stages 307 and 309, with 307 providing the first eight bits 0-7 and 309 providing the remaining four bits 8-11. The horizontal counter 93 is incremented on the falling edge of VIDCLK and serves as a timing basis for setting the boundaries of the horizontal sync and blanking intervals. The value of the horizontal counter is compared with the value of the four other horizontal timing registers to produce the HYSYNC- and BLANK- output signals. When the horizontal counter 93 reaches the value in the horizontal total registers 91, it is reset to zero by circuit 311. When the video system controller is configured in the external sync mode, HYSNC- is an input signal and the horizontal counter is forced to zero as a delay from the falling edge of HYNC-. The vertical counter is reset in a similar manner to activate the YSYNC- input signal. The external sync mode allows the VSC 3 to "sync up" to an external video source. This allows multiple video sources to be displayed simultaneously on the same monitor. The external sync mode is enabled by writing the EXTSYNCEN bit to control register 39C. Fig. 38 shows the latching and sync circuits that process the incoming sync pulses. An active signal RESET- forces the horizontal counter 93 to zero. Microprocessor 1 cannot access this counter either.

The remaining registers of Fig. 7 are shown in Fig. 19, which is a schematic diagram of the base register block 313.

Another function of the video block 57 includes the data block SR. SR stands for shift registers contained in the display memory 5. A shift register read or write cycle is an access initiated by the microprocessor 1. Shift register cycles are specifically enabled for the purpose of transferring data between the cell arrays of the display memory 5 and the shift registers within the display memory 5. Display update cycles are automatically initiated in the video system controller 3. Shift register cycles may also be initiated under the express control of the microprocessor 1. Fig. 20 is a schematic diagram of the SR data control circuit contained in the video block 57. The direction of data transfer is determined by the status of the control bit SRW in the control register 1. A shift register transfer cycle can be initiated either by the VSC 3 (play update) or by the microprocessor, the type of cycle desired being determined by the function selection code entered on lines FS0-FS2. The function selection code of binary zero indicates a register access cycle, binary #1 an indirect XY cycle, binary 2 a register access cycle, binary 3 a direct microprocessor cycle, binary 4 a shift register to memory cycle, and binary 5 a shift register from memory to shift register; 6 and 7 are unused or reserved for special functions such as a test mode. A shift register write cycle transfers the contents of the shift register within the play memory 5 to the particular specified row within the single chip memory cell array, and a shift register read cycle transfers the contents of a specified row within the memory cell arrangement to the shift register.

Figure 20A shows the generation of the shift register address control logic that provides the memory address to the display memory 5 during display update cycles requested by the VSC 3. Figure 20B is a 4-bit control that counts up to the value specified by the control bits PLC(3-0) of the control register 381. The status of this count determines the period of the shift register reload (display update) cycles and can vary from once per horizontal scan line to once every sixteen scan lines. Figures 20C, 20D and 20E show the logic of the 12-bit shift register address counter. The least significant four bits shown in Figure 20C comprise a full adder that allows the shift register address to be incremented. In normal operation, by 1, 2, 4, or 8. The least significant two bits of this address specify the tap point that is selected on the external playback memory 5. The next most significant eight bits are passed to the memory address output terminals and represent the row address select bits. The last two most significant bits of this counter represent the row address select control bits. These bits are decoded to one of four active row address selects (RAS (3-0)) during a shift register update cycle when the VSC 3 is in the extended host address enable mode, which is programmed by setting the EHAE bit in control register 381. If this bit is inactive, then all RAS output signals become active during a shift register update cycle.

As previously discussed, the FS decode circuit decodes the functions to be performed by the video system controller based on the binary value of the three function select decode signals applied thereto. The schematic diagram of the FS decode block 63 is provided in Fig. 21. The FS decode logic 63 is shown in Fig. 21 and receives from the microprocessor 1, both the control signals FSO-2, the row select signal RSO-1 plus the column address on data bus 21C and the row address on data bus 21R, and the CS signal which is fed into the FS decode circuit. In addition, a reset signal is provided from the input terminal block 59, as well as the ALE signal and the NOLATCH (no latch) signal coming from the control registers. It provides the row address, the column address and the complements thereof as well as decoding the function select input signals. The various functions are decoded by the PLA 331 and correspond to the functions previously identified. For any function select decoding to be active, the chip select input signal (XCS) must be active. In addition, circuitry 333 and 335 provides scan and test mode generation. Line drivers 334 are used to drive the row address signals and the column address signals.

Column address decoder 55 receives the read/write command in the form of RWB, the low order byte of the column address enable in the form of XCEL, the column addresses in the form of CAB, and the internal register access function select signal in the form of FSINT. The output of the column address decode circuit is a clear command which is decoded by decode circuit 341, which is used as an input to status block 61 and is used to clear the four most significant bits of the data bus when a 12-bit internal register is read. Figures 22B through 22E show the logic that completes the decoding of the column address during internal register accesses. These outputs select which of the internal registers is accessed or loaded.

Fig. 22 is a schematic diagram of the XY register 43. The XY register 43 is used during an indirect cycle in which the microprocessor 1 indirectly accesses a word in the display memory 5, the preferred embodiment of which is DRAM, dynamic random access memory. The contents of XY register 341 represent the concatenation of the XY coordinates of a word containing one or more pixels on the screen. The X coordinate is represented by the least significant bits of the address, and the Y coordinate is represented by the most significant bits of the word address. The location of the boundary between the X and Y coordinates of the address is programmable. Both X and Y increase as they shift from the least significant bit to the most significant bit in register 341. The X and Y displacements at the origin, which is generally located in the upper left corner of the screen of CRT monitor 11, are both 0 only in the special case that the pixels displayed in the upper left corner of the screen are in the word location at memory address 0. When manipulating the X and Y addresses by the video system controller 3, the non-zero distance of the upper left corner of the screen from the start of the memory must be compensated.

The capability of the X-Y register 43 is particularly useful in applications where the linear addressing range of the microprocessor 1 is limited to allow easy access to all pixels within the active display area. A read or write cycle using the contents of the X-Y register 43 is referred to as an indirect X-Y cycle.

During an indirect XY cycle, the contents of the X and Y registers 43 are used in place of the row and column address present on the RA8-RA0 data bus 21R and the CA8-CA0 data bus 21C. The 4-bit code entered on CA4-CA1 during an indirect XY cycle determines the manner in which the contents of the XY address register 43 are updated following the completion of the indirect XY cycle. If the binary value of these four bits is equal to 0, there is no adjustment, equal to 1: increment X; equal to 2: decrement X; equal to 3: delete X; equal to 4: increase Y; equal to 5: increase X, increase Y; equal to 6: decrement X, increase Y; equal to 7: delete X, increase Y; equal to 8: decrement Y; equal to 9: increase X, decrement Y; equal to 10: decrement X, decrement Y; equal to 11: delete X, decrement Y; equal to 12: delete Y; equal to 13: increase X, delete Y; equal to 14: decrement X, delete Y; equal to 15: delete X, delete Y.

The address adjustments discussed above are performed automatically by the X-Y register 43 during the execution of each indirect X-Y cycle. This mechanism allows convenient access to any sequence of adjacent pixels without the hassle of loading new values into the X-Y address register before each access. As a result, the video system controller is able to perform step-by-step graphics operations, such as drawing lines, filling polygons, and generating utility characters, at hardware-assisted speeds.

The XY address register 341 is a 20-bit register consisting of two parts. The register includes the XY address register 341 and parts of an offset register 342 shown in Fig. 22B. The offset register 342 contains two accessible bits accessible to the microprocessor 1 designated as bit 11 and bit 10. These two bits are not affected by the XY set code entered at data bit CR4-CR1. The second part consists of the remaining 18 bits consisting of 16 bits contained in the XY register 43 accessible to the microprocessor 1 and two groups of 2-bit registers concatenated therewith as two most significant or least significant bits depending on the status at B7 of the control register 39C. One of these two-bit registers is enabled. The 16 bits contained in address register 341 are divided into two sections. The Y coordinates are the most significant bit portion of register 341, and the least significant portion forms part of the X coordinate. The boundary between the X and Y portions is programmable. The XYLRAS signal is provided by control register 39C and when it is at a logic 1, a 2-bit register is chained to the XY register at the MSB. This occurs at 351. These two additional most significant bits and the Y portion of 353 of the XY address register 341 form the Y coordinates. Similarly, a logic 0 on XYLRAS, which comes from control register 39C, enables the two least significant bits 355. The two least significant bits 355 and the X portion 357 of the XY address register form the X coordinates. These 18 bits in the XY register 341 are linked so that its carries or borrows from the most significant bit of the X coordinate are transferred to the least significant bit of the Y coordinate only when the Y coordinate itself is not explicitly set. Upon resetting the contents of the control register 39C, the XYLRAS signal returns to or is forced as a logic zero. Either the X or Y section of the X address register 341 then transfers the contents of bits 8 and 9 of the XY offset register 342 to either the least significant bits 355 of the X coordinate or the most significant bits 351 of the Y coordinate of the XY address register 341, regardless of the status of the XYLRAS signal. A read in the XY offset register 342 always returns the current value of the X or Y enable extension bits, bits 8 and 9 of the offset register 342, in data bits D₁-D₀, but not the value stored in bits 8 and 9.

To ensure correct operation, the XY offset register 342 is always loaded before loading the XY address register. This is necessary to allow the two extension bits, bits 8 and 9, to be loaded correctly. These extension bits are used to determine which of the four row address strobe signals REAS3-REAS0 is active during the indirect XY cycle. Bits 8 and 9 are used to provide the four active strobe signals, which is used in the RAS decode logic 5 is carried out.

The XY register 341 contains 16 bits accessible to the microprocessor 1 that become part of the 20-bit XY address register output. The boundary between the XY portion of this register is programmable to accommodate the needs of various graphics memory configurations. The X portion is determinable to occupy any of 2 to 9 of the least significant bits of the register. The remaining bits form part of the Y portion. The eight possible boundary conditions between the X and Y positions of this register are shown in Fig. 26A and B.

The XY offset register 342 determines the boundaries between the X and Y portions of the XY address register 341 and contains initial values of the 2 RAS select bits and bits 8 and 9 located at 357 and 359. The eight least significant bits of the XY offset registers located at 361 and 363 specify the boundaries between the X and Y portions of the address contained in the X and Y register 341, as indicated in Figures 26A and B.

Bits 8 and 9 of the two offset registers store the initial values that are loaded into the X and Y address extension bits by microprocessor 1 during an initiated write cycle to either the X portion 353 or the Y portion 357 of the XY register 341. These two bits are not affected by the setup code entered to CA4-CA1 during an indirect XY cycle. Accordingly, only the XY address transfer and extension bits are changed. A read of the XY offset register 342 returns the current value of the XY address extension bits to the XY offset register 342 instead of the initial value of the two bits 8 and 9.

A bit 11 at 363 is the MA8 output during the row address times, and bit 10 located at 365 is the MA8 output during the column address times.

These two bits are also not affected by increments or decrements of the XY address pointer. Any bit in the X-Y address register shown as unused in Figure 26A is read as a 0.

Microprocessor 1 initiates an indirect XY cycle by setting inputs FS2-FS0 to function code 001. Replay memory 5 is then either read or written as specified by line R/W-. The contents of XY address register 341 can be set after each indirect XY cycle to point to the adjacent word to be accessed during the next indirect XY cycles. Fifteen different settings are possible for XY address register 43. These settings are selected by the inputs to CA4-CA1 during an indirect XY cycle, as discussed earlier. This specified setting is made during the current XY cycle in anticipation of the next indirect X-Y cycle.

The 20-bit XY address consists of the sixteen bits of the XY address register 341 accessible to the microprocessor 1, and the two RAS select bits plus the two MA8 bits located in the XY offset register 342. The two RAS select bits cannot be directly accessed by the microprocessor 1; however, it can cause them to be loaded from bits 8 and 9 of the XY offset register. The 20-bit X-Y address points to a word within the display memory 5 containing one or more pixels, the number of pixels being determined by the width of the microprocessor 1 data path and the number of bits per pixel. The boundary between the X and Y portions of the address is programmable to accommodate a variety of memory configurations, as will be discussed later.

During an XY access of the playback memory 5, the video system controller uses the address contained in the address register 341 instead of the Address supplied externally to the RA8-RA0 data bus 21R and the CA8-CA0 data bus 21C. The eight most significant bits of the sixteen bits contained in the XY address register are output as MA0 through MA7 as the row address on data bus 25, and the eight least significant bits are output on data bus 25 as MA0 through MA7 as a column address. Bits 10 and 11 of the XY offset register 342 are also multiplexed on MA8 as row and column addresses. The two RAS select bits, which are not accessible to microprocessor 1, are used in place of the RS1-RS0 input signals to determine which of the four row address strobe signals RAS3-RAS0 becomes active during the cycle.

The XY addressing is flexible to allow the programmer to customize the X and Y screen dimensions to suit his application. The X portion of the address can occupy the lower two to nine bits of the XY address register, while the Y portion occupies the remainder of the XY address register. The RAS select bits are chained to either the X or Y portion according to the state of the XYLRAS signal.

Fig. 27A is a schematic background of the control registers 39C. The video system controller includes two directly accessible control registers 371 and 373. The functions controlled by these registers include the behavior of the interface signals between the microprocessor 1 and the video system controller 3, the timing of the playback update cycles, the enablement of interrupt refreshes, the frequency of DRAM refresh cycles, and the generation of video timing functions. The control registers 371 and 372 are both 16-bit registers. Each can be read and written by the microprocessor 1. The individual bits within these registers have associated functions shown in Table 2. Fig. 27A shows the logic of three synchronization circuits 375, 377, and 379. The three synchronization circuits are used to contents of control register 381 to output holding register 383 of control register 371. The reason for this is that microprocessor 1 writes to the control registers during execution of a function by the video system controller. To avoid glitches and interruptions, data is loaded into control registers 381 and then transferred to output holding registers 383 via transfer signals TRAN 1, TRAN 2 and TRAN 3. Two reset signals are used to initialize the transfer signals which include VRESET and SRESET. The horizontal start blanking signal is applied to synchronization circuit 375 to generate signal TRAN 1. When microprocessor 1 writes to control register 381, TRAN 1 prevents VSC 3 from changing mode of operation until the horizontal start blanking signal becomes valid. This occurs halfway across the horizontal scan line. Fig. 27C shows the control register 373 and the functions associated with it. Figs. 28 and 29 are schematic diagrams of the CRB registers used to set up the control registers 381 and 373.

Fig. 30 is a schematic diagram of the INPUT/PORTS block 59 and provides the logic for receiving the control signals from the microprocessor 1 on the data bus 23 and buffering the signals for supply to the video system controller 3. A circuit 400 synchronizes the system reset and video reset signals so that they are synchronized with the correct clocks. This is of course done by using delay circuits 401, 403 and 405 to ensure that the video reset is synchronized with this clock, which are phase 3 and phase 1 signals or sub-multiples of the video clock, and that the system reset is synchronized with this clock by synchronizers 407, 408 and 409. The remaining circuits are essentially buffered and amplified for connection to the video system controller.

The data status block 61 contains the status registers 81 and the data ports 83.

Fig. 31 is a schematic diagram of the data terminals 83 in which buffering and amplification are provided to drive the signals present on the data bus 17 to the XY register 43, the column address register 49, 41 and the internal control registers 39.

Fig. 32 is a schematic diagram of the status register 81 in which there are three bits, each representing a particular internal condition. A bit value of one indicates that the corresponding condition has been detected. These conditions include a vertical interrupt on a logic circuit 411. A display error indicates that the video system controller 3 was unable to perform a display update cycle requested during the horizontal blanking interval. The display error is stored in circuit 413. The refresh error latch 415 indicates that the video system controller 3 was unable to perform the designated number of DRAM refresh cycles before the start of the next horizontal blanking interval. These three signals are combined by an And/Or logic 417 and provided to the interrupt conductor 23. A specific reason for the interrupt is provided on the status lines 419. Again, there is a synchronizing circuit 421 which synchronizes the interrupt from the video clock 27 with the system clock. The interrupt is first synchronized with the video clock by a circuit 423 which includes three driven transistors 425, 427 and 429 which are driven by phase three, phase one and phase three signals. Between the phase three driven and phase one driven gates and between the phase one and phase three driven gates are inverting amplifiers 435 and 437 respectively. The output of the circuit 433 is fed to the system clock synchronizers which include a driven latch 441, 443 and the pulse shaping circuit 445 which synchronizes the interrupt to the vertical interrupt circuit 411. Fig. 33 provides the clock circuits used to generate the phase one and phase three signals on the video clock at circuit 451; circuit 453 generates system clock signals used to provide clocks to the video system controller 3. The dual clocks and synchronizing circuits shown in Figs. 32, 9, 30 and 36 are needed because the video clock VIDCLK, which is harmonically related to the monitor dot clock, may be different from the clock SYSCLK of the microprocessor 1. SYSCLK is specified to run faster than VIDCLK and allows memory cycles to be performed at a convenient rate. VIDCLK is specified to run slower than SYSCLK. However, the architecture allows to control monitors whose dot clock frequency can exceed 100 MHz.

An example of a memory device 5 that may be suitable for use in the system shown in Fig. 1 and shown in Fig. 34 is a 64K-bit MOS dynamic read/write memory using single transistor cells as shown in U.S. Patent No. 4,239,993 and also including a serial shift register with several additional taps. For this example, the random access may be one bit wide. Other suitable examples (not shown) may be memory devices as previously described herein that have 256K-bits of memory or even more.

If, as will be explained below, the memory is partitioned to use, for example, eight chips, then the individual storage devices may be X1, i.e. one bit, wide, and eight of these memories may be connected in parallel for access by a typical 8-bit microcomputer. Another partition, such as X4 or X16, could also be used, as will become clear below.

The storage device 5 shown in Fig. 34 is typically manufactured by an N-channel, self-aligned silicon gate, dual-level polysilicon MOS process, with the entire device contained in a silicon chip approximately 1/30 of a square inch in size, which would normally be mounted in a standard dual in-line package with twenty pins or terminals. For a 256K-bit device, this package may be provided with as many as twenty-two pins or terminals. Similarly, the number of pins would increase for larger volume devices. The device in this example includes an array 10 split into two halves 10a and 10b, each containing 32,768 cells, in a regular pattern of 256 rows and 256 columns. Of the 256 rows or X-lines, 128 are in half 10a and 128 in half 10b of the array. The 256 columns or Y-lines are each halved, with half in each of the halves 10a and 10b. In the center of the array there are 256 sense amplifiers 511; these are differential type bistable circuits made in accordance with the invention described and claimed in Patent 4,239,993 or U.S. Patent 4,081,701. Each sense amplifier is connected in the middle of a column line so that 128 memory cells are connected to each side of each sense amplifier by means of a column line half. The chip requires only a single 5V supply voltage Vdd together with a ground connection Vss.

A row or X address decoder 12 split in half is connected by sixteen lines 513 to eight address buffers or latches 14. The buffers 14 are made in accordance with the invention described in U.S. Patent No. 4,288,706. An eight-bit X address is applied to the inputs of the address buffer 14 via eight address input terminals 525. The X decoder 12 functions to select one of the 256 row lines as determined by an eight-bit address on the input terminals 15 received from the microcomputer via a data bus 507.

For more than 256 row lines, i.e. a 256K-bit memory with 512 row lines, a larger than eight-bit X-address and eight-bit buffer must be used.

Further, a column address is received at input terminals 25 and latched in column address latches 16. For bit-wide random access data input/output, eight column address bits are required, but for byte-wide access, i.e. eight bits, only five address bits are required, and the microcomputer can output additional column address bits to select between multiple cascaded chips; these additional column address bits can be used by chip select decoders of conventional design. The outputs of column address latches 16 are connected by lines 517 to a decoder 18 in the center of the array which selects one of 256 columns to produce a bit-wide input/output on a random access input/output line 17/31; separate input lines 17 and output lines 31 may be used as shown in Fig. 1, or the lines 17/31 may be multiplexed as shown in Fig. 34. Rows of dummy cells (not shown) are included on each side of the sense amplifiers, as is common practice in devices of this type. As with the X address, for larger devices the number of bits and latches required to identify a column increases.

The memory device is thus similar to a standard dynamic RAM with a bit-wide or other bit-format random access and also with a serial input/output. Referring further to Fig. 34, the serial access is provided with a 256-bit serial shift register 20 which is divided into two identical halves, the halves being arranged on opposite sides of the arrangement 10. The The same result can be achieved by placing both halves on the same side of the array, but superimposed on one another. However, placing the halves on opposite sides of the array balances the operation of the sense amplifiers.

The shift register 20 can be loaded from the column lines of the array 10 for a read cycle or loaded into the column lines for a write cycle through 128 transfer gates 21a on one side of the device and an equal number of transfer gates 21b on the other side of the array.

The data is input into the device for serial writing via a data input connection 22, which is connected to inputs 24a and 24b of the shift register halves by a multiplex circuit 523. The data is read serially from the register halves via outputs 525a and 525b, a data output multiplex and buffer circuit 26 and a data output connection 527.

The shift register 20 is operated with a clock 0 which is used to shift the bits through the stages of the register at two stages per clock cycle. For read operations, only 128 cycles of the clock 0 are needed to output 256 bits from the 256 bit positions of the split shift register. A control signal TR applied to the transfer gates 21a and 21b connects each of the 256 bit positions of the shift register 20 to its corresponding column line in the 10a and 10b halves of the array.

In a serial write operation, the sense amplifiers 511 are operated by a write command W appearing after TR/QE to set the column lines to a full logic level, after which a row line is selected by the address in the latches 14 and the data is forced into the memory cells of that row.

A serial read cycle starts with an address at the input 15 which is decoded to activate one of the 256 X or row address lines (and a dummy cell on the opposite side). The sense amplifiers 11 are then actuated by a control signal from the clock generator and control circuit section 30 to force the column lines to a full logic level and then the transfer gates 21a and 21b are actuated by the control signal TR/QE to transport the 256 bits from the selected row into the corresponding halves of the shift register 20. The shift clock signal 0 is then applied and can transport 256 bits via the multiplexing circuit 26 in serial format to the output terminal 527 at two stages or bits per clock cycle, requiring 128 clock cycles for the entire register. The output terminal 527 is connected to the shift register 7 of Fig. 1.

As described so far, the memory device is similar to a standard bit-wide or other bit-format random access dynamic RAM with serial input and output; however, according to the invention, the 256-bit serial shift register 20, which provides serial input and output, is organized as four 64-bit shift registers. One, two, three, or four 64-bit shift registers may be accessed, depending on which of the four "tap" along the 256-bit shift register is selected. Since the 256-bit shift register is divided into two "halves," each 64-bit shift register is also divided into halves. As shown in Fig. 34, a 64-bit shift register is an upper half 20a and a lower half 20b, a second 64-bit shift register is an upper half 20c and a lower half 20d, a third 64-bit shift register is an upper half 20e and a lower half 20f, and a fourth 64-bit shift register is an upper half 20g and a lower half 20h.

The selected tap determines whether the first, second, third or fourth 64-bit shift register is accessed. The selected tap is determined by a two-bit code, which is fed to the two most significant column address inputs. The figure in Fig. 34 is thus formed of lines 517 from the column address latch 16 which also go into the shift register 20 to select the desired particular tap via a binary code.

Referring to Fig. 35, a microcomputer 1 which can be used with the system of the invention may include a single-chip microcomputer device 1 of conventional construction together with additional off-chip program or data memory 80 (if required) and various peripheral input/output devices 81, all interconnected by an address/data bus 607, and a control bus 9.

A single bidirectional multiplexed address/data bus 7 is shown, but separate address and data buses may be used instead, as in Fig. 1, and the program addresses and data or the input and output addresses on the external buses may be separate; the microcomputer may be of the Von Neumann architecture or of the Harvard type, or a combination of the two.

The microprocessor 1 could, for example, be one of the devices sold by Texas Instruments under the part number TMS 7000 or TMS 99000, or one of the devices commercially available under the part numbers Motorola 68000 or 6805, Zilog Z8000 or Intel 8086 or 8051 or the like. Although these devices differ in details of internal construction, they generally include an on-chip ROM or read-only memory 82 for program storage and may also have program addresses available off-chip, but in any event they provide off-chip data access for playback memory. 5. The VSC 3 is designed to interface with all microprocessors and microcomputers, giving system designers flexibility.

A typical microcomputer 1, as shown in Fig. 35, may include a RAM or random access read/write memory 583 for storing data and addresses, an ALU 84 for performing arithmetic or logical operations, and an internal data and program bus arrangement 585 for transferring data and program addresses from one location to another, usually consisting of several separate buses. Instructions stored in the ROM 82 are individually loaded into an instruction register 587, from which an instruction is decoded in the control circuit portion 88 to generate control bits in control lines 589 to determine the operation of the microcomputer.

The ROM 82 is addressed by a program counter 90, which may be self-incrementing or may be incremented by passing its contents through the ALU 84. A stack 591 is included to store the contents of the program counter upon an interrupt or subroutine operation. The ALU 84 has two inputs 92 and 93, one of which has one or more temporary storage registers 94, which are loaded from the data bus 585.

An accumulator 595 receives the ALU output signal and the output of the accumulator is connected by bus 85 to its final destination, such as RAM 583 or data input/output register and buffer 96. Interrupts are handled by an interrupt controller 597, which has one or more off-chip connections via control bus 23 for an interrupt request, interrupt acknowledge, interrupt priority code, and the like, depending on the complexity of the microcomputer device and system.

A reset input can also be considered an interrupt. A status register 98 associated with the ALU 84 and the interrupt controller 597 is included for temporarily storing status bits such as zero, carry, overflow, etc. of ALU operations; upon an interrupt, the status bits are saved in RAM 583 or in a designated stack.

Depending on the particular system and its complexity, the memory addresses are coupled from off-chip through buffers 96 connected to external bus 607. This path can be used to address off-chip data or program memory 80 and input/output 81 in addition to off-chip video memory 5. These addresses to bus 7 can originate in RAM 83, accumulator 95, or instruction register 87, as well as program counter 90. A memory control circuit 99 generates (in response to control bits 89) or responds to the appropriate commands to or from control bus 9 for an address point, memory enable, write enable, hold, chip select, etc.

In operation, the microcomputer device 1 executes a program instruction in one or a sequence of machine cycles or state times. A machine cycle may be, for example, 200 ns long, provided by an output signal from a 5 MHz crystal clock supplied to the microcomputer chip. Thus, in successive machine cycles or state times, the program counter 90 is incremented to generate a new address. This address is supplied to the ROM 82 to generate an output signal to the instruction register 587, which is then decoded in the control circuit section 88 to generate a sequence of settings of the microcode control bits 589 to perform the various steps required to load the bus 85 and the various registers 94, 595, 96, 98, etc.

For example, a typical ALU arithmetic or logic operation would involve loading addresses (fields of the instruction word) from instruction register 87 over bus 585 to the addressing circuitry for RAM 583 (this may include only source addresses or both source and destination addresses). Such an operation may also involve transferring the addressed data words from RAM 583 to a temporary register 94 and/or to the ALU input 92. Microcode bits 89 would define the ALU operation as one of the types available in the instruction set, such as add, subtract, compare, AND, OR, exclusive-OR, etc. Status register 98 is set depending on the data and ALU operation, and the ALU result is loaded into accumulator 595.

As another example, a data output instruction may include transferring a RAM address from a field in the instruction to RAM 583 via bus 585, with this addressed data being transferred from RAM 583 via bus 585 to output buffer 96 and thus out to external address/data bus 7. Some control output signals may be generated by memory controller 99 on lines of control bus 9, such as write enable, etc. The address for this data output could be an address on bus 607 via buffer 96 in a previous cycle, being latched into memory 80 or memory 5 by means of an address strobe signal issued by memory controller 99 to control bus 23.

An external memory controller may be used to generate the RAS and CAS strobe signals. A two-byte address for memory 5 would be applied to bus 607 in two machine cycles if bus 607 is an 8-bit bus, or in one cycle if the bus is a 16-bit bus.

The microcomputer instruction set includes instructions for reading from or writing to the video memory 5, the additional memory 19, or the input/output ports of the peripheral device 581, where the internal source or destination is the RAM 583, the program counter 90, the temporary registers 94, the instruction register 587, etc. In a microcoded processor, each such operation includes a state sequence during which addresses and data are transferred on the internal bus 585 and the external bus 7.

Alternatively, the invention may use a microcomputer 1 of the non-microcoded type in which an instruction is executed in one machine state time. In selecting the microcomputer 1, it is necessary that the data and addresses and various memory controls are available off-chip and that the data processing speed is adequate to generate and update video data within the time constraints of the particular video application.

The video memory arrangement of the invention is described in terms of single-bit data paths for the bus 7, although the microcomputer system and memory technology is of course useful in any 8-bit or 16-bit system or other architectures, such as 24-bit or 32-bit. One benefit in a small system of the type with 8-bit data paths and 12-bit to 16-bit addressing is that no external memory 80 is required and the peripheral circuitry 81 consists only of a keyboard or similar interface plus possibly a disk drive. For example, a bus interface chip, such as an IEEE 488 type device, could be included in the peripheral circuitry 81.

Fig. 36 is a block diagram of the video system according to the invention, in which the video system 805 is a 512x512 pixel, 16-color graphics system. The display memory 5 has been expanded by means of X4 from a single multiport memory device to four groups of memory devices 5A, 5B, 5C, 5D. The outputs of the multiport memory 5A-5D are fed to the 4-bit shift registers 7A-7D and the CRT monitor 11 via the digital-to-analog converter 9 and an optional color palette register 801. The color palette register naturally contains the coded information for generating the program colors which the microprocessor addresses in it.

Fig. 37 is a block diagram of a color graphics system with a resolution of 1024x1024 pixels. The display memory 5 has been replaced by four groups of multi-port memories 5E, 5F, 5G, 5H which are 16 bits deep. The shift register 17 has been extended to contain four shift registers 7E-7H which are 16 bits wide. The rest of the circuits of Figs. 36 and 37 are the same as those shown in Fig. 1.

Although the present invention has been described with respect to the illustrated embodiments, this description is not intended to be construed in a limiting sense. Numerous modifications to the illustrated embodiments, as well as other embodiments of the invention, will become apparent to those skilled in the art upon reference to this description. It is therefore intended that the appended claims will cover any variation of embodiments that fall within the scope of the invention.

Claims (7)

1. A video system comprising: a data processor (1) for manipulating image pixel data corresponding to a video image in accordance with program instructions; a video system control means (3) including a refresh address counter (45) for storing an address for memory refresh; a multiplexer (49) for connecting addresses received from the data processor (1) via a first address bus (21), addresses stored in the refresh address counter (45), or addresses received from a control register to the second address bus (25); display means (11) for generating a visual display perceivable by an operator which corresponds to the image pixel data stored in a video memory (5), the display (11) comprising a plurality of horizontal lines which correspond to the image pixel data retrieved from the video memory (5) by the addresses received from the control register; characterized in that the video system further includes: memory cycle control means (35) for sequentially generating memory refresh requests during an active portion (901, 903) of the horizontal lines and display update requests during a blanking portion (902) of the horizontal lines; wherein the multiplexer (49) is operable to execute a memory access cycle in which addresses received from the data processor (1) via the first address bus (21) in response to a memory access request are passed through to the second address bus (25); wherein the multiplexer (49) is further operable to execute a memory refresh cycle in which addresses stored in the refresh address counter (45) in response to a memory refresh request are passed through to the second address bus (25), the addresses stored in the refresh address counter (45) being incremented after each memory refresh cycle; wherein the multiplexer (49) is further operable to execute a display update cycle in which addresses received from the control register in response to a display update request are passed through to the second address bus (25); and an arbiter (37) for controlling the memory cycle control means (35) to execute only one of a memory access cycle, a memory refresh cycle and a display update cycle in accordance with received memory access requests, memory refresh requests and display update requests, the arbiter being arranged to assign the priority of the display update requests during the horizontal blanking interval (902) of each line, the priority of the memory access requests during an earlier portion (901) of the active portion of each horizontal line and the priority of the memory refresh requests during a later portion (903) of the active portion of each horizontal line. 2. Video system according to claim 1, wherein the video memory (5) includes: a multiport memory unit having a matrix of rows and columns of storage locations, the multiport memory unit being arranged to receive a row address and a column address which are multiplexed on the second address bus (25); and a serial shift register (7) having a serial output port for shifting the rows in all columns of a row corresponding to a received row address to the display device (11) upon receipt of a shift register transfer signal. 3. A video system according to claim 2, wherein the video system control means (3) includes: a row address buffer (47) for storing a row address received from the data processor (1) via the first address bus (21); and a column address buffer (41) for storing a column address received from the data processor (1) via the first Column address received via the address bus (21). 4. A video system according to claim 3, wherein the data processor (1) is arranged to generate shift register access requests and a read/write control signal (R/W-) for indicating a write or read operation; the memory cycle control means (35) is operable to control the shift register access cycle by applying a row address blanking signal and a shift register access request to the video memory (5) and to cause the multiplexer (49) to pass a row address through to the second address bus (25) during the shift register access cycle; such that, depending on a read/write signal (W-), data stored in a specific row of the memory matrix are transferred to the shift register (7) during a shift register access cycle or data stored in the shift register (7) are transferred to a specific row of the memory matrix during a shift register access cycle. 5. A video interface comprising: means for establishing an electrical connection with a data processor (1) for manipulating image pixel data corresponding to a video image in accordance with program instructions and with a video memory (5) for supplying image pixel data to a display means (11) for producing a corresponding display perceivable by an operator; a multiplexer (49) for switching addresses received from the first data processor (1) via a first address bus (21), addresses stored in a refresh address counter (45) or addresses received from a control register to a second address bus (25); and characterized in that the video interface further includes: a memory cycle control means (35) for sequentially generating memory refresh requests during an active portion of a horizontal line and display update requests during a blanking portion the horizontal line; wherein the multiplexer (49) is operable to execute a data processor memory access cycle in which addresses received from the data processor (1) via the first address bus (21) in response to a memory access request are passed through to the second address bus (25); wherein the multiplexer (49) is further operable to execute a memory refresh cycle in which addresses stored in the refresh address counter (45) in response to a memory refresh request are passed through to the second address bus (25); wherein the multiplexer (49) is further operable to execute a display update cycle in which addresses received from the control register in response to a display update request are passed through to the second address bus (25); and an arbiter (37) controlling the memory cycle control means (35) to execute only one of a memory access cycle, a memory refresh cycle and a display update cycle in accordance with received data processor memory access requests, memory refresh requests and display update requests, the arbiter (37) being arranged to assign priority to display update requests during the horizontal blanking interval of each line, priority to data processor memory access requests during an earlier portion of the active portion of each horizontal line and priority to memory refresh requests during a later portion of the active portion of each horizontal line. 6. A video interface according to claim 5, wherein: the memory cycle control means (35) is arranged to control the shift register access cycles by applying a row address blanking signal and a shift register access request to the means for establishing an electrical connection to the video memory (5) while controlling the multiplexer (49) to Receiving a shift register access request switches a row address to the second address bus (25). 7. A video interface according to claim 5 or claim 6, in which: the memory cycle control means (35) is arranged to produce a predetermined number of memory refresh cycles during each horizontal line.