JPH1091136A - Electronic computer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable performing high speed picture data processing inexpensively by using a DRAM array as a system memory (system dynamic RAM) and a display memory and coping with overlapping of memory cycles of two memories by controlling change of priority of a cycle. SOLUTION: This system is provided with a system dynamic RAM 19 having a DRAM array for storing data, and a display memory 5 having a DRAM array storing bit map data for display. And a video system controller 3 generates automatically a refresh cycle required for maintaining data stored inside of the system dynamic RAM 19 and the display memory 5, while changes priority between a cycle of access request of a microprocessor 1 for the system dynamic RAM 19 and the display memory 5 and a cycle of DRAM refresh.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to electronic computer systems and the like, and more particularly to an improved data processing apparatus for providing high resolution video display.

[0002]

2. Description of the Related Art Output from a computer as an image on a screen of a cathode ray tube or the like has been conventionally performed. This screen is effectively composed of a collection of dots (pixels), so that an image is formed by selecting and illuminating those pixels necessary to form the desired image. If the image sought is only a simple pattern of numbers or other symbols, the image can be implemented with a relatively small number of pixels. However, if one wants to obtain a more complex image (with higher resolution), one must choose a screen with a fairly large number of pixels.

Here, each pixel used to form an image is illuminated by a separate output signal from a processing unit of a computer, and a screen having a larger number of pixels is required to increase the resolution. It should be understood that. That is, since each video data signal must also be stored before being transferred to the screen, in order to increase the resolution of the image, the data storage unit needs a number of memory cells for receiving and holding all these data signals. Must be correspondingly increased.

If another screen having a large number of pixels is used in order to increase the resolution of an image displayed on the screen, the cost of the entire apparatus does not increase disproportionately. However, the size (capacity) of the memory elements (circuits) is a significant factor in the cost of the device, and as the resolution of the images provided increases, the completeness of all data signals between the storage and video sections increases. The time interval available to make the transfer actually decreases.

[0005] Many plans and proposals have been made to avoid or reduce these disadvantages. In particular, mass storage devices can be used to accommodate a large number of input signals, but, as mentioned above, such devices are inherently expensive and can be used in home computer (microcomputer) devices (systems). The cost of such a computer system will increase significantly. Techniques can be used to provide custom storage that can be accessed fast for high data rates, but such devices are even more expensive than slow access storage.

The data storage capacity can be increased simply by adding another storage device (memory unit). But,
This not only increases the overall system cost, but also tends to increase the time required to transfer the video data to the pixels since each storage device is a separate storage component.

Part of the problem that arises when a data storage device is comprised of a plurality of separate RAM devices (chips) is that the RAM devices are interconnected in parallel with shift registers and all of these RAM devices are unloaded. It has been proposed that the contents be transferred to the shift register at the same time and be mitigated. Next, the data in the shift register is sequentially clocked into the pixels at the appropriate video data rate. While this technique has been extremely beneficial in reducing data transfer cycles to those corresponding to a single memory chip, it does not address the problem of increased cost. Furthermore, since the storage circuit is composed of standard-structured memory units, the storage device originally has more cells than the pixels on the screen, and the image is stored whenever the storage device is unloaded to the video unit. It is necessary to unload more cells than is actually needed to form

[0008] The control circuit for the conventional device (system) is 3
Two separate controllers were required, one dealing with system memory, one dealing with textual information and one dealing with graphical information. These conventional systems often suffered from video memory failure.

A text subsystem is only required if the performance of the bitmapped controller subsystem is sufficient to handle the text in a reasonable amount of time. Today, many products combine text and graphics into one subsystem. However, these systems have the disadvantage that they must have a data bus that is physically separated between a small portion of the system memory and the display memory. In one example where part of the main system memory has a common memory space with the display data, there is another separate data bus connected to the high speed OM used to contain performance critical routines.

Due to the fact that display devices must often be refreshed with display data at all times, it is necessary to perform a relatively constant "background" task of continuously transferring the contents of the display memory to the display device. is there. This background task using normal RAM can monopolize the data bus to and from that RAM by as much as 85%. In a multiport video RAM type device (eg, TMS4161 from Texas Instruments),
The required amount of data bus required for the display refresh task can be reduced to 3% or less. Other types of RA
The use of M causes the above-mentioned obstacles.

In systems using conventional memories for holding display data, it is imperative that a significant portion of the main system memory of the processing unit not be on the same physical data bus as the display data bus, or otherwise. System performance will be greatly reduced. For example, if a processing unit is connected to a bus where 80% of the bus cycles are allocated for display refresh, then the overall system performance will be (only 20% access or 1 / 5th access).
Will be reduced to 1/5.

The solution to date using conventional memory for display data has been to isolate the main system memory bus of the CPU from the display memory data bus, at least to a large extent (if not all). Was. This isolation allows the processing unit to operate at a much higher speed on a more isolated system memory bus outside the display memory bus. N manufactured by NEC Corporation
In some cases, such as a system using EC7220, the isolation of the display memory only makes the access of the processing unit there very limited.

[0013]

SUMMARY OF THE INVENTION The present invention overcomes some of the problems of the prior art described above and provides an electronic computer system that enables high speed data processing at low cost. That is, the present invention provides a memory having a DRAM array for storing data, a display memory having a DRAM array for storing display bitmap data, and processing data stored in the system memory. To the display memory, and a DRAM refresh control for the system memory and the display memory, and a cycle of an access request of the host processor to the system memory and the display memory, and the DR.
An electronic computer system including a display control device that changes the priority of the AM refresh cycle. With this configuration, the priority of the cycles is changed by using a low-cost DRAM array as both the system memory and the display memory, and by duplicating memory cycles that may occur when the two memories are connected to a common data bus. It responds by control and enables high-speed image data processing at low cost.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIG. FIG. 1 is a block diagram showing an embodiment of a video system controller according to the present invention. The blocks shown in FIG. 1 include a microprocessor 1, a video system controller 3, and a display memory (display multiport memory) 5 (which is assigned to the assignee of the present invention and is incorporated herein by reference. As disclosed in U.S. Patent Application No. 567,040). The output of the display memory 5 is connected to the shift register 7. The shift register 7 transmits the data to an appropriate monitor (television) display device (CRT monitor) 11 or another output device or input device via a bidirectional data bus 9A.
-A) Shift to converter 9. Further, a system dynamic RAM 19 is provided for storing data and instructions for processing by the microprocessor 1. Microprocessor 1 includes a data input from terminal 15, video system controller 3, display memory 5
The data is supplied to a bidirectional data bus 17 connecting the microprocessor 1 to the system dynamic RAM 19. Further, the microprocessor 1 provides address information to the video system controller 3 and the second terminal 19, which are connected with the terminal 15 to a port device such as a keyboard and other peripheral devices that can be used by the system. The microprocessor 1 supplies address information to the video system controller 3 via the address bus 21. The processing of the interface between the microprocessor 1 and the video system controller 3 is performed by a bidirectional bus 23, through which control signals are transferred between the two. The output of the video system controller 3 is provided to the display memory 5 and the system dynamic RAM 19 via the address bus 25 in the form of address information and control signals. The control of data transfer between the display memory 5 and the system dynamic RAM 19 is performed by the video system controller 3 via the control bus 27. Furthermore, the sync / return erase signal is
9 to the CRT monitor 11. Microprocessor 1 executes program instructions provided thereon by data bus 17 or stored in its own internal memory. Control signals and data in the form of commands are sent to video system controller 3 in response to these program instructions. The video system controller 3 performs four basic functions. These four actions are:
(1) The microprocessor 1 has a system dynamic RA
To provide virtually contention-free access to M19 and display memory 5; (2) the refresh cycle required to maintain data stored inside system dynamic RAM 19 and display memory 5; Automatically occurring; (3) performing the display update cycle necessary to periodically load new video data into the display memory 5, especially the shift register contained therein; (4) CRT monitor 11 to generate a video synchronizing signal and a blanking signal necessary to control the signal.

The display memory 5 includes a bitmap RAM unit (chip) having enough cells to accommodate any screen display for the CRT monitor 11, and further includes a separate preselected column of cells in the display memory 5. , A serial shift register having a plurality of taps at positions corresponding to.
In addition, provisions are made for selecting taps to unload only the portion of the shift register that contains the bit in question, thereby effectively eliminating unused portions of the shift register, thus creating a problem. The time required to transfer existing data to the CRT monitor 11 is reduced. The optional high speed shift register 7 is interfaced via a conductor 31 to the internal shift register port of the display memory 5 and includes an optional DA video converter 9 or other output device
Shift data to input device. The CRT monitor 11
Video system controller 3 (which processes data transfer from display memory 5 to CRT monitor 11 via optional shift register 7 and DA video converter 9)
The information provided from the microprocessor 1 via the data bus 17 is displayed under the control of. The timing for the system is given by the system clock 33,
It is the system, especially the video system controller 3,
A shift and load clock are applied to the display memory 5 and the shift register 7.

Referring to FIG. FIG. 2 shows a functional block diagram of the video system controller 3 of FIG. In FIG. 2, multiplexer 49 includes a shift register address from a refresh address counter used to refresh the memory cells of display memory 5, from an XY address register 43, and from a control video internal register 39. , Receives an address from the microprocessor 1 via the address bus 21. These addresses are converted into 9-bit rows of column addresses necessary for the display memory 5 and the system DRAM 19. The addresses provided by the microprocessor 1 are divided into two groups. That is, RA0 to RA8 are row address bits applied to row address latch 47 via data bus 21R, and CA0 to CA8 are column address bits applied to column address latch 41 via data bus 21C. Of course, the abbreviation CA indicates a column address bit. The arbiter enable logic 37 provides an enable / hold signal to the microprocessor 1 as part of the control signal carried over the data bus 23, and also provides an address source provided to the display memory 5 by the multiplexer 49 and the data bus 25. decide. The control signal used to control the multiplexing of the multiplexer 49 and the associated matrix address is output from the data bus 25 in the form of MA0-MA8 representing the memory address.
Generated by Each of the row address input and the column address input from the microprocessor 1 is controlled by the control signal “AL” before being multiplexed into the display memory 5.
The falling edge of E "is held in row address latch 47 and column address latch 41. XY address register 43 and control and video internal register 39 are programmable registers that can be directly accessed by microprocessor 1.

The data bus 17 of the embodiment of FIG.
Each register of the XY address register 43 and the control / video register 39 has a bit width of 16 bits. As a result, the microprocessor 1 accesses the upper and lower bits of the register in separate cycles. The bit value input to the column address bit line, which is part of the address bus 21C, determines whether the upper byte or the lower byte of the register is addressed. Access to the internal register is performed at the beginning of the cycle by selecting
This is possible by setting an appropriate function code selection specified by S2. Selecting one of the registers (up to a total of 18 in the embodiment of FIG. 2)
It is determined by a 5-bit code input on data lines CA6 to CA2 which are part of access bus 21C during access by microprocessor 1. The input value on CA1 selects the upper byte or the lower byte of the register.
The state of the read / write line, that is, the column address usable lower byte which is a control line existing on the data bus 23,
The R / W input, which must be valid before and during the low of CEL, determines whether the register access is a read or a write. The control / video internal registers include a video timing register, a display update register, and a control register. The video timing register is programmed to generate the horizontal and vertical synchronization signals and the blanking signal required to control the CRT monitor 11 of FIG. The values loaded into these registers are customized to meet the particular display resolution and timing requirements of CRT monitor 11. Both the interlaced scanning mode and the non-interlaced scanning mode can be used. The video system controller can be programmed to limit the application decomposition in which the graphic image generated in the display memory 5 must be superimposed on the external video signal to the externally generated synchronization signal.

The display update register is required because the video system controller 3 generates the display update cycle necessary to periodically refresh the video display. The display update register holds the row to the display memory 5 and the tap point address during each display update cycle. The display update cycle is a special type of display memory 5 access for transferring 256 bits of data between the memory cell array and the shift register in each display memory 5 of the memory system. In a graphical display application, the display update cycle occurs during horizontal blanking and loads the shift register with a new data load from the memory cell array.

During the next active horizontal scanning, the contents of the shift register in the display memory 5 are displayed on the CRT monitor 11 by supplying a clock signal from an external pad in series. The video system controller 3 can be programmed to transfer data in the opposite direction, ie from the shift register to the memory cell array (the memory cell array is entirely contained in the display memory 5). This mode of operation is convenient for capturing images generated externally and then clocked into the shift register via the serial input during the preceding active horizontal scan.

The display control register contains a starting display address corresponding to a position in the display memory 5 displayed at the upper left of the screen. The amount by which the display address is increased during the display update cycle is also programmable. These programmable features include (1) specify the number of scan lines between successive display update cycles, (2) specify the direction of data transfer (read or write), (3) input or output And (4) selecting either interlaced video or non-interlaced video to identify a horizontal sync (Hsync) line and a vertical sync (Vsync) line to be performed. These characteristics are controlled by values loaded into the control register and the video timing register. In the embodiment shown in the block diagram of FIG. 2, there are two control registers which control the identification of a number of programmable characteristics, including the various operating modes supported by the video system controller 3 described above. I do. Each active register can be read and written by the microprocessor 1. This block of registers also includes a status register that can be read but not written.

The status register contains three active bits. One shows when a particular horizontal scan on the screen was displayed. The other two status bits indicate an error condition. That is, one shows how long the pending request for the DRAM refresh cycle has been locked out, and the other shows how long the pending request for the display update cycle has been blocked. When enabled, these state conditions cause an interrupt request to be sent to the microprocessor 1.

The XY address register 43 maintains an XY address representing the connection of the X and Y coordinates at a certain position on the graphic screen displayed by the display monitor 11.
The video system controller 3 is a microprocessor 1
Can be designed to provide an internal 20-bit XY address instead of the address given by This feature helps to increase the address range of a particular processor. Even if the microprocessor 1 has a sufficient address range to directly access any pixel on the screen, the hardware update of the XY address between accesses is less than the same effect performed by the microprocessor 1 software. It seems to be effective. The XY part of the address is provided by the input CA4 provided by the microprocessor 1 during each access of the XY address 43.
Under control of ~ CA1, it can be independently increased, decreased or cleared. An increase occurs, followed by the next XY
The access for preparing the transfer of the address to the XY address register 43 is completed. The XY addressing mechanism of the video system controller allows internal algorithms, such as line drawings and custom character drawing routines, to access a series of adjacent pixels on the screen at hardware-assisted speed.

The arbiter 37 is responsible for generating requests for memory and register access cycles. 1
If more than one request is outstanding, the arbiter can determine which request should be raised next based on the relative priority of completed requests. Since the display update cycle and the DRAM refresh cycle are internally generated by the video system controller 3 typically using less than 2% of the available memory cycle (cycle time), the arbiter requests the memory register access from the microprocessor. Is likely to be granted immediately. However, if the refresh request for the display memory 5 has been outstanding for some time, its priority is increased so that a refresh cycle occurs before the memory data is lost. Arbiter is RDY / HO
The microprocessor 1 is kept in a check state by an LD (ready / hold) signal.

The memory cycle generator 35 can perform the memory cycle assigned thereto by the arbiter / ready logic 37. The memory cycle generator controls the multiplexer 49 to generate timing for control signals and addresses during the memory cycle. Further, the memory cycle generator 35 can execute microprocessor-direct memory access, XY addressing, display update, refresh of the display memory 5 and the system dynamic RAM 19, shift register read cycle, and shift register write cycle. it can.

The video system controller 3 can execute refresh cycles on the display memory 5 and the system DRAM at regular intervals. Refresh address counter 4
5 generates a 9-bit row address during a refresh cycle. It is included in the refresh counter 45 to determine the number of refresh cycles per scan line. The timing of this transfer is shown in FIG.

The refresh address register in refresh address counter 45 has no access to microprocessor 1, maintains the current row address, and is incremented following each memory refresh cycle.

The enabling of the refresh cycle and the refresh cycle frequency are determined by three control register bits in control register 39C.

CRT controller 51 includes a 4-bit scan line counter, which is used to count the number of active horizontal lines output to CRT monitor 11 during successive display update cycles. Any number of scan lines from 1 to 16 can be specified. For example, in a system where each display update cycle transfers enough data to operate the video shift register of display memory 5 for two complete scan lines, the display update cycle may be at the beginning of every other scan line. Only required.

FIG. 105 shows four consecutive scan lines on the CRT monitor 11, which are used to refer to the locations where various video system controller 3 operations occur. Line segments 901A-901D represent the active portion of each horizontal scan line. Sections 902A to 902D indicate the erasing units of each horizontal scanning line. The microprocessor 1 can request a memory access at any time, but the video system controller 3 grants the access and performs a memory cycle based on its internal arbitration logic. At certain times during the raster, two types of cycles are generated by the video system controller. In FIG.
During the intervals labeled A, 902B, 902C, 902D, video system controller 3 performs a display update cycle, also known as a shift register reload cycle. This causes a shift register transfer to occur in the video memory 5, which is the data to be displayed on the next scan line. Sections 901A to 901
The beginning of D represents the end of the horizontal blanking interval. At this point, video system controller 3 initiates a refresh cycle for all memories in the system. Until the time points 903A to 903D of each scanning line, the memory access cycle requested by the microprocessor 1 is given priority over the refresh cycle requested internally. In the middle of the active scan lines 903A-903D, refresh cycles are given priority over cycles requested by the microprocessor. The display update cycle is always given priority over the cycle requested by the microprocessor.

3 to 9 will be described. 3 to 9 show FIG.
FIG. 3 is a wiring diagram of a circuit block used to implement the functional block on a single metal oxide silicon chip having a plurality of field effect transistors.

The system 53 includes the memory cycle generator 3
5, including register 39A which is part of control and video internal register 39 of FIG. 2, multiplexer 49, refresh counter 45 and arbiter / enable logic 37.
The video block 57 operates as a CRT controller together with the video internal register 39C. The XY logic block 43 corresponds to the XY register 43 in FIG. The FS decode logic 63 not only includes the row address latch 41 and the column address latch 47, but also includes a function selection input signal FS (2
−0) is included. CA- which is a part of the control / video internal register 39 shown in FIG.
Decode logic 55 includes a decode circuit coupled to column address latch 41. The remaining control registers are included in the control register block 39C of FIGS. Input pin 5
9 and data state 61 include input logic, microprocessor 1, display memory 5 and system DRAM 1
Control signals necessary for realizing bidirectional transfer between the microprocessor 9 and the microprocessor 1 shown in FIG.

Table 1 shows the definitions of the abbreviations used to represent the separate signals shown in FIGS.

[0033]

[Table 1]

Referring to FIGS. 10-15, system 53 includes logic to implement memory cycle generator 35. It is divided into several logical components. This includes: That is, row address select (RAS) decode logic 6 for decoding a row address select operation
5, memory pins 69 for controlling data loading through memory provided by cycle generator 67, microprocessor 1 and display memory 5 or system DR.
A cycle generator 67 for generating a memory cycle for processing data transfer between the AM 19, and a controller 71 for generating internal control signals used by the video system controller 3. In addition, the arbiter enable logic 37 is used for refresh address counter 45.
Are included in this system block diagram.

FIG. 16 shows the video block 57 of FIGS.
And a CRT controller 51 including a CRT logic 73. CRT logic 73 generates CRT signals such as blanking and horizontal and vertical synchronization signals,
These signals can be received by the CRT monitor 11 at a voltage
The signal is supplied to a video pin 75 which converts the signal into a current level signal.
As described above, the display memory 5 in the preferred embodiment incorporates a shift register that the microprocessor 1 can write directly to. The control of the data transfer to the shift register is controlled by the SR logic 7 which is a part of the video block 57.
3 done.

FIG. 17 is a wiring diagram of the DA-ST block 61 shown in FIGS. This DA-ST block 61 receives the data and sends it to the video system controller 3.
And a data pin 83 for converting to a logic level acceptable to In addition, states are provided as state blocks 81 as part of the interface to the microprocessor 1, the display memory 5 and the system memory 19.

FIGS. 18 to 24 show wiring diagrams of the CRT block 73 of FIG. CRT block 73 includes vertical birth logic 97, horizontal control logic 95, horizontal counter 93, and vertical counter 99. Further, DA-ST block 6
There are nine programmable registers 313 that can be written and read by the microprocessor 1 via the 8-bit data pad 18 provided to the video block 57 by 1.

In the embodiment shown in FIGS. 18 to 24, each register has a 12-bit width. The microprocessor 1 accesses the programmable registers in the CRT block 73 as well as other areas of the video system controller 3 by special read and write cycles. The register access cycle consists of the function selection inputs FS2 to FS0
Is set to one of two 3-bit codes, 000 or 010. Although the video system controller 3 has 18 programmable registers and the CRT block has only 9 of them, the information described here is applicable to all 18 programmable registers. One of the 18 registers is selected by the 5-bit register address of column address inputs CA6-CA2. Binary code 00000-1
0001 is a valid register address. Code 10
010 to 11111 are reserved. The upper byte or lower byte of the selected register is selected by the value input of CA1. If CA1 is zero, the lower byte is selected; if it is 1, the upper byte is selected.

In FIGS. 18-24, the logic represented by CRT block 73 generates the horizontal sync, vertical sync, and blanking outputs required to control CRT monitor 11. These signals are HSYNC-VSYNC-BL
Output in ANK series. The video system controller can be programmed to provide the appropriate CRT monitor 11 and the appropriate sync, blanking signal of the screen resolution selected for the desired application. Further, the video system controller 3 determines that the INT
By controlling the V signal, an interrupt can be programmed to interrupt the microprocessor 1 at the end of any of the horizontal scan lines by driving INT- to its active low level. These signals are programmed by the parameters loaded by microprocessor 1 into the nine registers of CRT block 73.

These registers are a horizontal end synchronization register 89 (HESYNC), a horizontal end blanking register 87
(HEBLNK), horizontal start blanking erase register 85 (H
SBLNK), horizontal sum register 91 (HTOTA
L), vertical end synchronization register 109 (VESYNC),
It comprises a vertical end blanking register 103 (VEBLNK), a vertical start blanking register 105 (VSBLNK), a vertical sum register 101 (VTOTAL), and a vertical interrupt register 107 (VINT). Two additional registers, horizontal counter 93 and vertical counter 99, are used in generating the video timing signal.

The horizontal counter 93 has a horizontal end synchronization register 89, a horizontal end blanking register 87, a horizontal start blanking register 85, and a horizontal total register 9.
A counter which is compared with 1 to determine the limits of the horizontal synchronization period and the horizontal blanking period. Similarly, the contents of the vertical counter 99 are compared with those of the vertical end synchronization register 109, the vertical end blanking register 103, the vertical start blanking register 105, and the vertical total register 101 to determine the vertical synchronization period and the vertical blanking period. Is a counter that determines the limit of. The contents of the vertical interrupt register are compared to a vertical counter 99 to determine when a particular scan line is being output to CRT monitor 11. The microprocessor 1 can interrupt when this state is detected.

Display memory 5 and system DRAM 19
Controller, display update controller and C
To serve as a timing controller for the RT monitor 11, the video system controller 3 must perform various types of access cycles. Some of these types are started by the microprocessor 1 and others are
Automatically started by Memory cycle generator 3
5 performs most of the access cycle. And FIG.
The cycle generator 67 shown in FIGS. 7 to 31 performs the next cycle. That is,

A direct cycle initiated by the microprocessor 1, also an indirect cycle of the XY register initiated by the microprocessor 1, a refresh of the display memory 5 and the system DRAM 19 automatically initiated by the video system controller 3. A cycle, a display update cycle automatically initiated by the video system controller 3, and a shift register transfer cycle including a shift register write and a shift register read for transferring data to and from the shift register in the display memory 5. It is.

The control circuit 71 processes requests for all internal cycles including the CRT monitor display update cycle and the refresh cycle of the memories 5 and 19. The horizontal blanking signal informs the control circuit 71 of the location of the raster on the CRT for a display update or refresh request. This request is transferred to the cycle generator 67 to realize a display update cycle or a refresh update cycle.

FIGS. 25 and 26 are schematic diagrams of a control circuit 71, which includes two synchronization circuits 111 and 113. FIG. The synchronization circuit 111 synchronizes the internal clock used to control the logic in the system block 53 with the horizontal blanking signal. The CRT monitor 11 uses a clock system different from that of the system 53. Therefore, the horizontal blanking signal and the horizontal stop blanking signal supplied from the video block 57 to the system 53 are controlled by an internal clock (which operates the control circuit 71). And another clock that needs to be synchronized. Further, the control circuit 71 includes a Mealy type state machine including a plurality of programmable logic arrays 115, an OR gate 117, and a latch circuit 119. 4 stages 121, 123,
Each output of each stage in FIGS. 25 to 26 having 125 and 127 is given to column lines A, B, C, and D, and its complement is the column line XA,
XB, XC, XD. Another control is data line 1
At 29, the row line is provided to the programmable logic array 115. Further, the Mealy state machine at point 131 PLA1
33 and decode logic 135. The output of the control circuit 71 is supplied to the cycle generator 67 via a data bus 137.
To data ready block logic via data line 139 and to data status block 61 via data line 141. The government of control logic 71 is that the state machine is placed on N-channel MOSFET logic using standard cells (the cell is
Is repeated and programmed multiple times by the arrangement of transistors 143 used to implement the state machine operation.

The logic gate 117 includes a plurality of input leads 2
17. These leads may be combined with a number of outputs from a programmable logic array (PLA) 115 (shown at 219) or may be followed by a minimum number of inputs of NOR gate 117 (shown at 221). Or
Only one line is connected to all inputs of the combined NOR gate (shown at 223), thus preparing for the implementation of a standard cell NOR gate.

The arbiter-enabled pending logic 37 is based on operation by the cycle generator 67. In this cycle generator, the logic circuit 151 of FIG. 27, whether inside or outside the video system controller 3, determines the priority of the above operation. The EXT signal based on the ALE signal and its complement signal XEXT represent a request from microprocessor 1 during a memory access cycle. ALE is latched by cycle generator 67 by latch 153.
Further, circuit 155 provides buffering for internal cycle request XINT. The cycle generator 67 includes a first stage 161, a second stage 162, a third stage 163, a fourth stage 16
4, including a Moorish state machine consisting of a fifth stage 165, a sixth stage 166 and a seventh stage 167. Each stage is a PLA115,
OR gate 117 and the output of each stage are applied to row lines A to G, and the complement circuit is applied to lines XA to X9.
9 inclusive. The output is further decoded by 177 including PLA 179 and decode logic 181. Logic 177 provides an indication on data bus 183 for external cycles and an indication on data bus 185 while an internal cycle is in progress. The W conductor indicates a write operation in which the TRQE provides shift register enablement and memory 5, 19 output enablement. REFINC is the refresh logic 45
Is given an increment refresh, and REFSHR
Prepares the transfer from the refresh counter to the refresh pending register included in the refresh logic of the refresh block 45 of FIGS. The data line (output) 185 controls the address selection of the microprocessor 49, and prepares an SRRASEL representing the selection of the display update row address. RACASEL is a row address / column address selection line used for a display update cycle and a refresh cycle. XYRA
SEL is an XY row address selection line.
Is an XY column address selection line, and EXTCASE is an external column address selection line. If none of these are active, row address (RA) 21d is selected. Line 187 is the internal column address enable ICAS
Prepare for EN and external column address enable ECASEN. Row address enable RASEN is connected to data line 189
Given above. The data line 191 is connected to the XY cycle (X
YCCL), shift register cycle (SRCCL),
And R including refresh cycle (REFCCL)
Select source for AS decode logic 65. Further, a line 193 is a completion line indicating that the internal cycle operation is completed, and the XYGO signal is present on the data line with the adjustment enable to the XY register 43.

Referring to FIGS. 32 and 33, FIG. FIG. 32 and FIG. 33 are block diagrams of the row address selection decoding circuit represented by the block 65 which is RAS-decoded. The row address selection invalidation circuit provides an operating mode that allows data to be written to memory N times faster than a modeless circuit. When N is the number of memory planes in the system, for example, the display memory 5 of FIG. 2 in one embodiment is configured to have four memory planes. For the video system controller 3, four row address selection planes are held in the embodiments of FIGS. The example is shown in FIGS. 32 and 33 in regions 177, 179, 181, 183.
That is, each plane is designated. When writing is performed on one plane, an image of one primary color is generated.
When the same data is written to two planes, a mixed color is generated. When the load address selection invalidating mechanism is used, it is possible to write to both planes simultaneously. To do this, the row address select (RAS) override bit of the control register contained in block 39c of FIGS. 3-9 is loaded with the binary value of that color. When writing to one plane of memory using this mechanism, the other plane is also selected. The RAS invalidation mechanism also applies to shift register transfers. These shift registers are, of course, display memories 5
Is placed within. This mechanism is 4 times faster since all four row address selection planes can be transferred in one cycle.
Clearing the screen of the T monitor 11 is permitted. Prior to the present invention, data was written to one bank of memory (plane) in one memory cycle. To draw an object, it is necessary to write each code (plane) separately.

The row address invalidation logic is programmed by microprocessor 1 into control restor 39c,
Controlled by the four bits stored (microprocessor 1 selects which row address select output bit is activated during a memory access cycle).
These four bits are RASOR (3-0). These four bits are gated with functional decode and R / W signals to prevent memory read conflicts. The row address invalidator operates in the following types of memory cycles: random access write cycle of microprocessor 1, transfer of microprocessor 1 request from shift register to memory, and transfer of microprocessor 1 request from memory to shift register. Only available for a while. The four gate bits are ORed with the row select zero and row select 1 bits
Are taken to form a selection for the row access selection output. 32 and 33, the row address select enable bit is sent from the cycle generator 67 to the row select decode logic and is represented by RASEN. This bit is previously set by the OR logic 164 to XRAS (3 to
0) Enable 4 bits from control register counted in output. Further, NOR gates 162 and 16
3 decodes the implemented function. Note that this function is performed by selecting a row address from a function selection decode circuit represented by RSA, XX from an XY register 43 indicating where data is written in a memory or shift register
Y, the SSRRAS from the video block 57, and the extended control register row address select bit provided by the control register 39c and represented by the signal CRRAS. These signals are multiplexed at logic 161 for the appropriate cycle being implemented and NORed at NOR gates 162,163. The shift register is represented by signal SRCCL, the refresh cycle is represented by signal REFCCL, and the XY cycle is represented by signal XYCCL. These signals are of course sent from the cycle generators of FIGS. 10-15 and combined by logic gate 185 with the signal EHAE brought in from control register 39. Decode block 63 provides a function select register signal, represented by the FSSR, and an RWB signal, where the four row select output bits are driven by logic 187. Function selection signal and R /
The W signal is combined by NOR gate 189.

FIGS. 34 and 35 show a multiplexer 49.
Is a schematic diagram, and the multiplexer 49 outputs a memory address to the memories 5 and 19. As described with reference to FIG. 2, the multiplexer 49 selects one of the outputs of the row address latch 47, the refresh address counter 45, the XY address register 43, and the column address latch 41. These inputs are XCAB which is an input from the column address latch 41, a signal XRAB which is an input from the row address latch 47 (both signals are part of the function selection decoding block 63 in FIGS. 3 to 9), and FIG. 3 to XY in FIG.
XXY signal which is a register or still input, XSR which is a shift register address which is a part of video block 57
The multiplexer 49 is used as an XRACA which is an output of the RA and refresh block 45 and the video block 57.
Will be introduced. The multiplexer of the illustrated embodiment comprises:
The signal is selected via the pass transistor 251,
It includes seven stages 250 provided to output terminal 253. Cycle generator 67 provides a selection for each function. EX
TCASEL provides a column select, XYRASEL provides an XY row select function, SRRASEL is a shift register row address output select enable, and RACASEL is a refresh row address and shift register column address select enable. The OR combination of all of these functions provides a signal, denoted EXTRASEL, that connects RA address bus 21d to the output of multiplexer 49 at output terminal 25. The output terminal is a 9-bit terminal.
The bits are indicated by circuits 255 and 257 in FIG. In addition, test logic is provided for testing the video system controller 3 in area 261 and the scanout signal introduced from the cycle generator 67 to the multiplexer 49 at point 263 and the output of the video block 57 provided to the multiplexer at point 265. Enabled by the video scanout signal. These two signals are all connected in series in separate ways at accessible storage nodes in the video system controller 3 and are the circuitry of the scan path used during device testing.

The memory pin 69 shown in FIG. 36 provides a control signal for writing to the display memory 5. Display memory 5
Are the write command XW, TRQE command, and two column address strobes XCASHI, XCAS
LO. The column address enable high and low signals provided from input pin 59 are ICASEN and ECASE.
N (both are generated by cycle generator 67)
Is gated to XCASHI and XCASLO.

The video system controller 3 is configured to perform a refresh cycle of the display memory 5 at regular intervals. The refresh counter (FIGS. 37-40) included in refresh address counter 45 generates a 9-bit row address during a refresh cycle.
A refresh burst counter that cannot access the microprocessor 1 determines the number of refresh cycles for each horizontal scanning line. Again, the refresh address register, which is inaccessible to the microprocessor, maintains the current row address and is incremented with each refresh cycle. The enabling of the refresh cycle and the frequency of the refresh cycle are determined by three control register bits in the video system controller 3. Eight of the 9-bit row addresses are provided by circuit 273 of FIG. 37 including refresh counter block 270 and hold register 271. SRCC
When there is a command from the cycle generator via the L signal,
The counter 270 is a refresh address counter 45
Is enabled for multiplexer 49 through bus XRACA connecting it to the multiplexer. FIG. 38 shows the remaining counter states 279 associated with the counter 270.
As described above, the Mealy type state machine shown at 275 in FIG. 39, which has no access to the host computer, determines the number of refresh cycles per horizontal scan line to be implemented. Its output REFRQ is output to control logic 71 indicating that another refresh cycle needs to be performed during the current scan line. Refresh address register 270 maintains the current row address and is incremented to follow each refresh cycle for display memory 5 and system memory 19. The cycle generator 67
Perform arbitration to prioritize memory cycles to be generated.

Ready Hold Logic 37 (FIGS. 10-15)
Provides an enable / hold signal to the microprocessor 1 informing the current state of the cycle generator 67. Several modes of operation are possible and the control register bit RHMO
Programmed by DE (1-0) and RH (2-0). These modes are Ready, Standby and Hold modes. In the ready mode, the microprocessor 1 sets RH (2-0) during microprocessor start.
Program the specific number of wait states desired by loading. When the cycle requested by microprocessor 1 begins, circuit 293 provides a timing sequence at the end of which informs the host computer by activating the ready / hold output that the cycle is over. If an internal cycle is in progress or a cycle of a previously requested microprocessor request is still in progress when microprocessor 1 requests another cycle, the previous cycle must be completed. Since the wait mode does not include a programmable wait state, it simply signals the microprocessor that its cycle has begun by activating the ready / hold output.
If the ready-hold logic is programmed to be in the hold mode, the video system controller 3 must issue a request to the microprocessor 1 to hold because it is time to perform a refresh cycle or a shift register reload cycle. . The microprocessor responds to the pending request by providing a logic zero level to the inhibit input. When the ready mode is programmed to any of the standby modes, the ready / pending output active logic level is programmable during reset by the state of the inhibit input. Here, the description of the system blocks of FIGS. 3 to 9 and the corresponding circuits shown in FIGS.

Video block 57 (FIGS. 45 to 46)
Is a CRT monitor 1 in a bitmap graphic system.
1 are used to generate the horizontal sync HSYNC-, vertical sync VSYNC-, and blanking BLANK- signals used to drive the SYNC. These signals are synchronized with the video input clock VIDCLK. HSYNC-, V
The signals output on the SYNC- and VLANK- pins are programmed via video timing registers accessible by the eight microprocessors 1. The illustrated vertical control logic 97 comprises a PLA 115, a logic gate 117.
And a plurality of state machine cells 301 that are latches. The state machine standard cell 301 is connected as shown in FIGS. 45 and 46 and provides an ordering of the gate signals to select any of the vertical counters. When the counter reaches the value of the selected timing register, the vertical control state machine cycles to the next timing register. The vertical counter register 99 counts the horizontal lines of the video display and serves as a timing reference for determining vertical sync, blanking interval limits. The contents of the vertical count are compared with the value of the vertical timing register to indicate the completion of the vertical synchronization and blanking period. The count is incremented by one at the beginning of each horizontal sync period with one exception.

The exception is that between the vertical front porch and the synchronization of the old field of the interlaced frame, the vertical count increase is such that the count of the horizontal counter 95 is equal to one half the value of the horizontal sum register 91. Occurs at an intermediate point. The vertical counter 97 is reset to zero when it reaches the vertical sum register 101 at the next falling edge of VIDCLK after the high-to-low transition of the active signal has zeroed the vertical counter. This period can be read by the microprocessor 1 during the increased period, but cannot be written there. Typically, multiple read cycles are used to access the vertical counter 97. Two consecutive reads responding to the same data information indicate that microprocessor 1 access is during the period between increases.
47 and 48 are schematic diagrams of a vertical counter 99, which has two counter stages 303 and 305.
The first counter stage 305 is for 8-bit data and is repeated eight times. Since the second counter stage 303 is for 4-bit data, the vertical counter stores a maximum of 12 bits.

FIGS. 51 and 52 are schematic diagrams of a horizontal control circuit 95 in which control signals are generated to control the horizontal registers 85, 87, 89, 91 and 93. FIG.
52 is a schematic diagram of the horizontal counter 93. The horizontal counter is a 12-bit counter divided into two stages 307 and 309. 307 gives the first 8 bits 0 to 7, and 309 gives the remaining 4 bits 8 to 11. The horizontal counter 93 increases with the falling width of VIDCLK and serves as a timing reference for determining the limits of the horizontal synchronization period and the blanking period. The horizontal counter value is signal output H
It is compared to the values of four other horizontal timing registers to generate YSYNC- and BLANK-. When the horizontal counter 93 reaches the value of the horizontal sum register 91,
It is reset to zero by circuit 311. When the video system controller 3 is configured in the external synchronization mode, the HSYNC- signal is input and the horizontal counter is set to H level.
SYNC-Zero as delay from falling edge. The vertical counter resets in the same manner as activating the XSYNC- input. In the external synchronization mode, the video system controller 3 synchronizes with the external video source (sy
nc-up). This allows multiple video sources to be displayed simultaneously on the same display monitor. The external synchronization mode is enabled by writing the EXTSYNEN bit to the control register 39c. FIG. 105 shows a latch for processing incoming sync pulses.
3 shows a synchronous circuit. Active reset-pulse is applied to the horizontal counter 93. This counter cannot access the microprocessor 1.

The remaining registers in FIGS. 18 to 24 are schematic diagrams of the basic register block 313. FIGS.
It is shown in FIG. Another function of the video block 57 is S
R data block. SR represents a shift register included in the display memory 5. A shift register read or write cycle is an access initiated by the microprocessor 1. The shift register cycle is specifically moved to transfer data between the cell array of the display memory 5 and the shift register in the display memory 5. The display update cycle is automatically started in the video system controller 3. The shift register cycle can also be started under the control of the microprocessor 1 of Meiji. FIG.
57 are schematic diagrams of the SR data control circuit included in the video block 57. The direction of the data transfer is determined by the state of the control bit SRW in the control register 39C. The shift register transfer cycle can be initiated by either the video system controller 3 (display update) or the microprocessor 1 so that the type of cycle desired is determined by the function selection code input on lines FS0-FS2. A binary function selection code of zero indicates a register access cycle, binary No. 1 indicates an XY indirect cycle, binary No. 2 indicates a register access cycle, and binary No. 3 indicates a microprocessor direct cycle. No. 4 indicates a shift register cycle from the shift register to the memory, binary No. 5 indicates a shift register cycle from the memory to the shift register, and Nos. 6 and 7
Is not used or used for special functions like test mode. A shift register write cycle transfers the contents of the shift register in the display memory 5 to a particular row in the on-chip memory cell array, and a shift register read cycle transfers the contents of a particular row in the memory cell array to the shift register.

FIG. 55 shows the generation of control logic for the shift register address that provides the memory address to the display memory during the display update cycle of the video system controller request. FIG. 56 shows control bits PLC (3
-4) count up to the value specified by
Indicates bit control. The state of the count determines the period of the shift register reload (display update) cycle, and can change from each horizontal scanning line to 16 scanning lines. The least significant four bits shown in FIG. 57 include a full adder that allows the shift register address to be increased. In normal operation, they are denoted by 1,2,4,8. The least significant two bits of this address specify the tap point selected by the external display memory 5. The next eight significant bits are routed to the memory address output pin and represent the row address bits.
The two most significant bits of this counter represent the row address select control bits. Video system controller 3 is EHA
When in the extended host address enable mode, programmed by setting the E bit in the control register 381, the bit will be set to one of four row address selections (RAS (3-0)) during the shift register update cycle.
Is decoded. If this bit is inactive, the RAS output is active during all shift register cycles.

As described above, the FS decode circuit decodes a function to be realized by the video system controller based on the binary values of the three function selection decode signals supplied thereto. FS decode block 63
Are schematically shown in FIGS. 64 and 65. The FS decode logic 63 receives a control signal FSO-2, a row selection signal, a column address on the data bus 21C, and a row address on the data bus 21R together with the CS signal introduced thereto from the microprocessor 1. Furthermore, A
The reset signal as well as the LE signal and the no-latch signal (which comes from the control register) are input pin block 5
Given from 9. Input pin block 59 decodes the function selection input and provides a row address, a column address and its complement. Separate functions are PLA
331, which correspond to the functions described above. The chip select input (XCS) must be active for any function select decode to be active. Further, the circuits 333 and 335 are for generating the scan / test mode. Line driver 33
4 is used to drive a row address signal and a column address signal.

The column address decoder 55 includes a read / write command in the form of RWB, a column address enable lower byte in the form of XCEL, a column address in the form of CAB, and FS.
Receive an internal register access function select signal in the form of INT. The output of the column address decoder 55 is
A clear command decoded by 41 and used as an input to the status block 61 and used to clear the four F high-order bits of the data bus when the 12-bit internal register is read. FIGS. 64 to 73 show the logic for completing the decoding of the column address during the access of the internal register. These outputs select which of the internal registers are accessed or loaded.

FIGS. 64 to 73 are schematic diagrams of the XY address register 43. FIG. This XY register address 43
Indicates that the microprocessor 1 indirectly accesses or writes words in the display memory 5 (in the preferred embodiment, DRAM or dynamic random access memory) via the 20-bit XY address register 341. Used during the cycle. The contents of the XY address register 341 represent the concatenation of the XY coordinates of words containing one or more pixels on the screen. The X coordinate is represented by the least significant bit of the address word, and the Y coordinate is represented by the most significant bit of the address word. The location of the boundary between the X and Y coordinates of the address word is programmable. Both X and Y move from the least significant bit of register 341 to the most significant bit. The X and Y displacements at the origin normally located at the upper left corner of the screen of the CRT monitor 11 are both zero in the special case where the pixel displayed at the upper left corner of the screen exists at the word position of the memory address 0. . Video system controller 3
, The non-zero offset of the upper left corner of the screen must be compensated from the start of memory.

The function of the XY address register 43 is particularly useful in fields where the linear addressing area of the microprocessor 1 is too limited to easily access all the pixels in the active display area. XY register 43
A read or write cycle using the contents of is denoted as an XY indirect cycle.

During the XY indirect cycle, the contents of the XY address register 43 are stored in the RA8 to RA0 data bus 21.
R and CA8 to CA0 are used in place of the row address and column address applied to the data bus 23. The 4-bit code input to CA4 to CA1 during the XY indirect cycle determines the manner in which the contents of the XY address register 43 are updated and the XY indirect cycle is completed. If these 4-bit binary values are equal to zero, there is no adjustment; if equal to 1, increase X; if equal to 2, decrease X; if equal to 3, clear X; , Increase Y if equal to 5, increase X, increase Y, equal to 6, decrease X, increase Y, equal to 7, clear X, Y Increase, decrease Y if equal to 8, increase X if equal to 9, decrease Y, decrease X if equal to 10, decrease Y, equal to 11 if equal to 11 Clear X, decrease Y, clear Y if equal to 12, decrease X if equal to 13, clear Y, reduce X if equal to 14, decrease Y Clear, if equal to 15, clear X and clear Y.

The above address adjustment is made automatically by the XY address register 43 during the execution of each XY indirect cycle. This mechanism allows convenient access to any order of adjacent pixels without incurring the overhead of having to load a new value into the XY address register before each access. As a result, the video system controller can perform incremental graphic operations such as line drawing, polygon filling, and custom character generation at hardware-assisted speeds.

The XY address register 341 is a 20-bit register composed of two parts. The XY register 43 includes the XY address register 341 and the offset register 342 shown in FIGS. 72 and 73. The offset register 342 is a microprocessor 1
And two accessible bits designated as bits 11 and 10. These two bits are C
It is not implemented by inputting the XY adjustment code on the A4 to CA1 data bits. The second part is included in the XY address register 43, and has 16 bits accessible by the microprocessor 1 and the B bit of the control register 39C.
7 as two most significant or least significant bits depending on the state at 7
The remaining 18 bits consisting of a bit register. One of these two bit registers is enabled. The 16 bits contained in the address register 341 are divided into two parts. The Y coordinate is the most significant bit of the register 341, and the least significant bit is the X coordinate. The X parts, the boundaries between the X parts, are programmable. The signal XYLRAS is provided by control register 39C, and when it is a logic one, a two bit register is coupled to the XY register with the MSB. This occurs at 351. These two additional most significant bits and 353 of the XY address register 341
Form the Y coordinate. Similarly, control register 39
A logic 0 on XYRAS provided by C is the two least significant bits 355 and the X part 357 of the XY address register.
Is the X coordinate. These 18 bits of the XY register 341 are carried or borrowed from the most significant bit of the X coordinate which propagates to the least significant bit of the Y coordinate only if the Y coordinate itself is not explicitly adjusted. When the contents of the control register 39C are reset, the signal XYRAS returns to logic 0 or takes the default value. Either the X part or the Y part of the XY address register 341 sets the contents of bits 8 and 9 of the XY offset register 342 to XYLRAS.
Regardless of the state of the signal, the signal is transferred to the least significant bit of the X coordinate of the XY address register or the most significant bit 351 of the Y coordinate.
Whenever the XY offset register 342 is read, the enable X or extension bit (ie, offset register 3
The current value of bits 8 and 9) of D.42 is data bits D _{1 to}
It returns to ₀ , but does not return to the value stored in bits 8 and 9.

The XY offset register 342 is always loaded before the loading of the XY address register 341 to ensure correct operation. This is necessary for the two extension bits, bits 8, 9 to load properly. These extension bits are used to determine which of the four row address strobes are active during the XY indirect cycle. Bits 8 and 9 are encoded to provide four active strobes, which are implemented in RAS decode logic 5.

The XY address register 341 includes bits that can be accessed by 16 microprocessors that are part of the output of the 20-bit XY address register. The boundaries between the X and Y portions of these registers are programmable to meet the requirements of various graphic memory configurations. The X part can be defined to occupy any of the least significant bits 2-9 of the register. The remaining bits become part of the Y part. The eight possible boundary states between the X and Y positions of this register are shown in FIGS.

The XY offset register 342 determines the boundary between the X and Y parts of the XY address register 341,
Includes the 2RAS select bits located at 57 and 359 and the initial values of bits 8,9. The eight least significant bits of the XY offset registers located at 361 and 363 specify the boundary between the X and Y parts of the address contained in the X address register 341 as shown in FIGS. I do. Bit 8 of the two offset registers,
9 stores an initial value to be loaded into the extension bits of the X and Y addresses during a write cycle started from the microprocessor 1 to either the X section 353 or the Y section 357 of the XY register 351. These two bits are unaffected by the adjustment code applied to CA4-CA1 during the XY indirect cycle. Only the transfer and extension bits of the XY address end up. XY offset register 3
By reading 42, the current value of the extension bit of the XY address is fed back to the XY offset register 342 instead of the initial value of the two bits 8 and 9.

Bit 1 of 363 is MA8 output during the row addressing time, and bit 10 of 365 is MA8 output during the column addressing time. These two
One bit is not affected by the increment or decrement of the XY address pointer. Any bit of the XY address register shown as unused in FIG. 77 is read as zero.

The microprocessor 1 starts the XY indirect cycle by setting the FS0 to FS0 inputs to the function code 001. Then, the display memory 5 is read out and written as specified by the R / W line. X
The contents of the Y address register 341 contain the value of each X to indicate the adjacent word to be accessed during the next XY indirect cycle.
It can be adjusted after the Y indirect cycle. Fifteen different adjustments are available for the XY register 43. These adjustments are performed during CA4 to CA1 during the XY indirect cycle described above.
Selected by the above input. This specified adjustment occurs during the current XY cycle in anticipation of the next indirect cycle.

The 20-bit XY access is performed by using the 16-bit and XY offset registers 34 accessible by the microprocessor 1 in the XY access register 341.
2, two RAS selection bits and two MA8 bits. The two RAS select bits are not directly accessible to microprocessor 1 which causes these bits to be loaded from bits 8 and 9 of XY offset register 342. This 20
The X-Y address of the bit corresponds to the display memory 5 including one or more pixels whose number is determined by the decoding path width of the microprocessor 1 and the number of bits per pixel.
Refers to a word in The boundaries between the X and Y portions of the address are programmable to accommodate the various memory configurations described below.

During the XY access of the display memory 5, the video system controller 3 includes in the address register 341 instead of the address externally supplied to the RA8 to RA0 data bus 21R and the CA8 to CA0 data bus 21C. Address is used. Of the 16 bits included in the XY address register 341, eight most significant bits are output to the data bus 25 as MA0 to MA7 as row addresses, and eight least significant bits are data to MA0 to MA7 as column addresses. 25. Bit 10 of the XY offset register 342,
11 is also multiplexed into MA8 as a row and column address. The two RAS select bits that cannot access the microprocessor 1 have four row address strobes RAS3-R
Used in place of RS1-RS0 to determine which of AS0 becomes active during the XY indirect cycle.

The XY addressing is freely selectable so that the programmer can adapt the X, Y screen dimensions to his application. The X part of the address is the XY address register 341
Occupy the lower 2 to 9 bits. The RAS selection bit is connected to either the X part or the Y part depending on the state of the XYLRAS signal.

FIG. 79 is a schematic diagram of the control register 39C. Video system controller 3 includes two evaluable control registers 371,373. The functions controlled by these registers include the behavior of the interface signals between the microprocessor 1 and the video system controller 3, the timing of the display update cycle, the enabling of the interrupt refresh, the frequency of the DRAM refresh cycle, and the generation of the video timing function. including. The control registers 371 and 373 are both 16-bit registers. Each is read and written by the microprocessor 1. The functions assigned to the individual bits in these registers will now be described. FIG. 79 shows the logic of the three synchronization circuits 375, 377, 379. These three
One synchronous circuit is used to transfer the contents of the control register 381 to the output holding register 383 of the control register 371. This is because the control register is written during the execution of the function by the microprocessor 1 video system controller 3. Data is loaded into control register 381 to avoid glitches and interrupts.
Next, transfer signals TRAN1, TRAN2 and TRAN3
Is transferred to the output holding register 383 via the. Two reset signals are used to initialize transfer signals including VRESENT and SRESET. The horizontal start blanking signal is provided to the synchronization circuit 375 to realize the TRAN1 signal. The microprocessor 1 controls the control register 3
When writing to 81, the TRAN1 signal prevents the video system controller 3 from changing operating modes until the horizontal start blanking signal is enabled. This occurs in the middle of a horizontal scan line. FIG. 81 shows the control register 373 and its associated functions. FIG. 82 and FIG. 83
Is a schematic diagram of a CRB register used to configure the control registers 381 and 373.

FIG. 84 is a schematic diagram of the input pin block 59, showing logic for receiving a signal from the microprocessor 1, buffering the signal, and supplying the buffer to the video system controller 3. Circuit 400 synchronizes the system reset signal and the video reset signal to synchronize with the appropriate clock. This is of course done by the delay circuits 401, 403 and 405, whereby the video reset is synchronized with this clock (the phase 1 and phase 3 signals are a submultiple of this video clock) and the system reset is made with the synchronization stages 407, 408. , 409 to synchronize with this clock. The remaining circuitry is buffered and amplified for use by the video system controller.

Data status block 61 contains status register 8
1 and data pin 83. FIGS. 85 to 87 are schematic diagrams of data pins 83 which are buffered and amplified to drive signals on the data bus 17 to the XY register 43, the column addresses 49 and 41, and the control / internal register 39.

FIGS. 88 to 97 are schematic diagrams of status register 81 in which there are three bits each representing a particular internal state. Bit value 1 indicates that the corresponding state has been detected.
These states include a vertical interrupt in logic circuit 411. A display error indicates that the video system controller 3 was unable to perform the required display update cycle during the horizontal blanking interval. This display error is stored in the circuit 413. Refresh error latch 415 indicates that video system controller 3 was unable to perform the specified number of DRAM refresh cycles before the beginning of the next horizontal blanking interval. These three signals are A
Combined by ND / OR logic 417, providing interrupt conductor 23, the correct cause of the interrupt is provided on status line 419.
Further, there is a synchronization circuit 421 for synchronizing an interrupt from the video block 27 with the system block. Circuit 4 including three gate transistors 425, 427 and 429 gated by phase 3, phase 1 and phase 3
By 23, the interrupt is first synchronized with the video clock. It is the code converter 43 that separates phase 1 and phase 3
5, 437. The output of circuit 433 is provided to a system clock synchronizer that includes gate latches 441, 443 and a pulse shaping circuit 445 that provides interrupts to the vertical interrupt circuit. FIGS. 98-100 show a clock circuit 451 used to generate phase 1 and phase 3 on the video clock and a circuit 453 used to clock the video system controller 3. FIG.
The dual clock and synchronization circuit shown in FIGS. 8 to 97, 27 to 31, 84 and 103 uses a video clock VIDCLK (which is associated with monitor dot clock and harmonic testing) with a microprocessor. It is required because it may be different from one clock SYSCLK. SYSCLK is specified to run slower than SYSCLK, but its architecture allows to control monitors whose dot clock frequency can exceed 100 MHz.

Suitable for the system shown in FIG.
One example of the memory device 5 shown in FIG.
As shown in US Pat. No. 9,993, this is a 64 Kbit MOS dynamic read / write memory using one transistor cell and further including a serial shift register having a plurality of taps. For this example, the random access may be one bit wide. Another suitable example (not shown) may be the following memory device having a storage capacity of 256 Kbits or more.

As described below, if the memory is, for example, 8
When partitioned to provide one chip, the individual storage devices can be X1 or 1 bit wide, and these eight storage devices can be connected in parallel for access by a typical 8-bit microcomputer 8 . X4
Alternatively, a partition such as X16 can be used as will become apparent next.

The memory device 5 shown in FIG. 101 is typically an N-channel self-aligned silicon gate 2
Through a heavy-level polycrystalline MOS process, the entire device is mounted on a 1-inch (2.54 cm) square, approximately 1/30 silicon chip (typically mounted in a standard dual in-line package with 20 pins or terminals). )
It is made to be included in. For a 256 Kbit device, this package has as many as 22 pins or terminals. Similarly, for high capacity devices, the number of pins will increase. In this example, the device consists of two halves 1 of 12768 cells each in a 256 row, 256 column rule pattern.
It includes an array 10 divided into Oa and 10b. 25
Of the six rows (X-rays), there are 128 in half array 10a and 128 in half array 10b. The 256 columns (Y lines) are split into half halves of the array halves 10a, 10b. In the center of the array 10 are 256 sense amplifiers 511, which are differential bistable circuits constructed in accordance with the invention disclosed and claimed in the aforementioned patent or U.S. Pat. No. 4,081,701. Since each sense amplifier is connected at the center of the column line, 128 memory cells are connected on each side of each sense amplifier. The chip has a ground terminal Vs
Only a single 5V power supply Vdd with s is required.

The row (X) address decoder 12 divided into two halves is connected to eight address buffers (latches) 14 by 16 lines 513. Buffer 1
No. 4 is constituted by the invention disclosed in U.S. Pat. No. 4,288,706. The 8-bit X address is provided to the input of the address buffer 14 by eight address input terminals 525. The X address decoder 12 has an input terminal 15 received from the microcomputer 8 via the switch 507.
To select one of the 256 row lines defined by the 8-bit address. For a 256Kbit memory with more than 256, ie 512 row lines, more than an 8 bit x address and an 8 bit latch must be used. The column address is also received at input pin 25 and latched in column address latch 16. For a 1-bit wide random access I / O, all eight column address bits are needed, but for a byte-wide or eight-bit wide access, only five bits are needed, and the microcomputer has several cascade connections. Additional column address bits can be output for selection within the chip. These additional column address bits can be used by a conventional chip select decoder. The output of the column address random 16 is supplied by a line 517 to a decoder 18 at the center of the array which selects one of the 256 columns and produces a one bit wide output on the random access I / O line 17/31. Connected. Separate input lines 17 and output lines 31 can be used as shown in FIG. 1 or can be multiplexed as shown in FIG. Rows of dummy cells (not shown) are included on either side of the sense amplifier as is usual in devices of this type. For X addresses, the number of bits and latches required to identify a column also increases for high capacity devices.

Thus, the memory device is similar to a standard dynamic RAM with random access of one bit width or other bit width and serial I / O. Still referring to FIG. 101, serial access is
This is provided by a 256-bit serial shift register 20 divided into two equal halves located on opposite sides of the zero. The same result can be achieved by placing both halves on the same side. However, by arranging these halves on opposite sides, the operation of the sense amplifier is balanced.

Whether shift register 20 can be loaded from a column line of array 10 for a read cycle by 128 transfer gates 521a on one side of the array and an equal number of transfer gates 521b on the other side, The column line can be loaded in a write cycle.

Data input to the device for serial writing is provided by the data in terminal 22 which is connected by the multiplex circuit 523 to the halves 24a and 24b of the shift register half. Data is read serially from the register half via outputs 525a, 525b, data output / multiplex buffer circuit 26 and data out terminal 257.

The shift register 20 is operated by a clock 0 which is used to shift bits through the register stages by two stages for each clock cycle.
For a read operation, outputting 128 bits from the 256 bit position of the split shift register only requires 128 cycles of clock 0. Transfer gate 2
Control signals TR29 applied to 1a and 21b store each of the 256 bit positions of shift register 20 in array half 1
0a and 10b are connected to the corresponding column lines.

In a serial write operation, the sense amplifier 511 is operated by a write command generated after TR / QE to set the column lines to all logic levels and thereafter
One row line is selected by the address of latch 14 and data is placed in the memory cells of this row. The serial read cycle starts at the address on input 15 which is decoded to activate one of the 256X (row address) lines (and the dummy cell on the other side). Sense amplifier 511 is then activated by a control signal from clock generation / control circuit 30 to bring the column lines to all logic levels, and then transfer gates 21a and 21b are activated and selected by control signal TR / QE. Move to half from line. At this time, the given shift clock signal 0 can move 256 bits in a serial format to the output pin 527 by two stages (bits) per clock through the multiplex circuit 26, and the entire register requires 128 clock cycles. It is.

As mentioned above, the memory device is the same as a standard dynamic RAM with a serial input / output 1-bit or other bit-sized random address. However, in the present invention, 2 which provides a serial input / output
The 56-bit serial shift register 20 is organized as four 64-bit shift registers. One, two, three or four 64-bit shift registers can be accessed depending on which of the four taps along the 256-bit shift register is selected. Since the 256-bit shift register is divided into two halves,
Each 64-bit shift register is also divided into two halves. As shown in FIG. 101, the first 64-bit shift register comprises an upper half 20a and a lower half 20b, the second 64-bit shift register comprises an upper half 20c and a lower half 20d, and a third 64-bit shift register. The register consists of an upper half 20e and a lower half 20f, and the fourth 64
The bit shift register has an upper half 20g and a lower half 20h.

The selected tap determines which of the first, second, third, and fourth 64-bit shift registers is accessed. The tap selected is determined by the 2-bit code provided to the two most significant column address inputs. FIG. 101 shows a line 517 from the column address latch 16 which also enters the shift register 20 to select the desired particular tap via a binary code.

In FIG. 102, the microcomputer 1 that can be used with the system of the present invention is a single microcomputer of a conventional structure, an additional off-chip program or data memory 80 (if necessary), and various peripherals. I / O device 81 (all of these are address / data bus 607 and control bus 23
Interconnected by a).

Although a single bidirectional multiplex address / data bus is shown, separate address and data buses may be used as shown in FIG. 1, or a program bus and data (input / output) may be used. 2.) Addresses can also be separated by external buses. The microcomputer may be configured with a Neumann-type architecture or a hardware type or a combination of both.

The microprocessor 1 includes, for example, parts
No. One of the devices sold by Texas Instruments as TMS7000 or TMS99000
Or part No. Motorola 68000, 680
5, Zirog Z8000, Intel 8086, 8051
It may be one of the devices sold as. These devices, although differing in the details of their internal structure, generally include an on-chip ROM 82 for program storage, but may also have a program address available off-chip, and in any case, an off-chip to the display memory 5. It can also have chip data access. The video system controller 3 is designed to interface with all microprocessors and microcomputers, thereby increasing the flexibility of the system designer.

A typical microcomputer 1 shown in FIG. 102 includes a RAM (random access read / write memory) 583 for storing data and addresses, an ALU 84 for executing arithmetic or logical operations, and a data and program address (usually). Consisting of several separate buses)
For transferring data from one location to another. RO
The instructions stored in M82 are stored in the instruction register 587 one by one.
From which instructions are decoded in control circuit 588 to generate control signals to define microcomputer operation.

The ROM 82 is addressed to a program counter 90, which can increment itself or can be incremented by passing its contents through an ALU 84. The stack 591 stores the contents of the program counter by an interrupt or a subroutine. The ALU has two inputs 92, 93, one of which has one or more temporary storage registers 94 loaded from the data bus 585.

The accumulator 595 receives the ALU output, and is connected to the accumulator output bus 85 via the RAM 58.
3 and data input / output register / buffer 96. Interrupts are handled by an interrupt controller 597 having one or more off-chip connections via control bus 23 such as interrupt requests, interrupt responses, interrupt priority codes, etc., depending on the complexity of the microcomputer device and system. Is done.

The reset input can also be handled as an interrupt. A status register 98 coupled to ALU 84 and interrupt control 597 is provided to temporarily store status bits, such as zero, carry, overflow, etc., from ALU operation. If there is an interrupt, the status bits are saved to RAM 583 or stack 591 for this purpose.

The memory addresses are coupled off-chip via a buffer 96 connected to an external bus 607, depending on the particular system and its complexity. This route is
It can be used to address the off-chip data program memory 80 and the input / output 581 in addition to the off-chip video memory 5. These addresses for bus 607 along with program counter 90
It can be issued by M83, accumulator 95 or instruction register 87. The memory control circuit 99 includes an address strobe, a memory enable, a hold,
Generates (or responds to) control bus 9 (in response to control bit 89) or responds to it for chip selection or the like.

In operation, microcomputer 1 executes a program instruction within one or a series of machine cycles (state time). The machine cycle may be, for example, 200 nanoseconds, depending on the output from the 5 MHz crystal clock provided to the microcomputer chip. Thus, in successive machine cycles (states), program counter 90 is incremented to generate a new address, which is applied to ROM 82 to generate an output to instruction register 587, which is decoded by control circuit 88 and Of the bus 85 and various registers 94, 595, 9
Implement the various steps required to load 6, 98, etc.

[0098] For example, a typical ALU operation would be to transfer an address (from the instruction register 587) via bus 585 to an addressing circuit for a RAM 583 (which can include only the source address or both the source and destination addresses). Command field). This operation translates the addressed data word from RAM 583 into temporary register 94 or ALU input 92.
Transfer to the server. Microbit 5
89 is A as one of the types obtained in the instruction set, such as addition, subtraction, OR, exclusive OR, etc.
Will specify LU operation. The status register 98 is set depending on the data ALU operation, and the ALU result is loaded into the accumulator 595.

As another example, a data output instruction may transfer a RAM address from the field of the instruction to RAM 583 via bus 58.
5, and transfers the addressed data from RAM 583 via bus 585 to output bus 96.
And thus to the external address / data bus 7. Certain control outputs can be written to control bus 2 such as writable by memory control 99.
3 can occur on the line. The address of this data output is the buffer 96 of the cycle before it is latched into memory 80 or memory 5 by the address strobe output from memory control 99 to control bus 9.
Via the buffer 607.

An external memory controller can be used to generate RAS and CAS strobes. A two byte address for memory 5 will be provided on bus 607 in two machine cycles if bus 607 is eight bits and one machine cycle if bus 607 is sixteen bits.

The instruction set of the microcomputer 8 is as follows.
A command to read from or write to the display memory 5, the additional memory 19 or the input / output port of the peripheral device 581,
Its internal source or destination is RAM 583, program counter 90, temporary register 94, instruction register 587.
And so on. In a microcode processor, each of these operations involves the transfer of addresses and data between internal buses 5.
85 and a series of states transferred to the external bus 7.

Alternatively, the present invention can use a non-microcode type microcomputer 1 in which instructions are executed within one machine state time. When selecting a microcomputer 1, all that is required is that data, addresses and various memory controls be obtained off-chip, and that the data processing speed is to generate and update the video data within the time limits of the particular video application. It is suitable for

Although it is understood that microcomputer systems and memory technologies are useful in either 8-bit or 16-bit systems, or other architectures such as 24-bit or 32-bit, the display memory of the present invention is A one-bit data path for bus 7 will be described. Its usefulness is that no external memory 80 is required and the peripheral circuit 81 is simply a keyboard or similar interface plus possibly a disk drive. Exhibited in small systems of the type having 8 bit data paths and 12 to 16 bit addressing. A bus interface chip such as an IEEE 488 type device could be included in the peripheral circuit 81, for example.

FIG. 103 shows that the video system 805 has 16
FIG. 1 is a block diagram of a video system according to the present invention, which is a 512 × 512 pixel graphics system with colors. Display memory 5 is 4 by 40 from a single multiport memory device.
It has been expanded to three groups of memory devices 5A, 5B, 5C and 5D. Outputs of the multi-port memories 5A to 5D are supplied to 4-bit shift registers 7A to 7D, and supplied to the CRT monitor 11 via the DA converter 9 and an arbitrary color palette register 801. The color palette register, of course, contains the code information for generating the program colors addressed there by the microprocessor.

FIG. 104 is a block diagram of a 1024 × 1024 pixel resolution color graphic system. The display memory 5 has four groups of 16-bit multi-port memories 5E,
Replaced with 5F, 5G, 5H. Shift register 7 is 1
Expanded to include four 6-bit wide shift registers. 103 and 104 are the same as those in FIG.

Although the present invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reading the description herein.

[Brief description of the drawings]

FIG. 1 is a block diagram including a video controller according to the present invention.

FIG. 2 is a functional block diagram of the video controller of FIG.

FIG. 3 is a wiring diagram of a circuit diagram used to realize the function of FIG. 2;

FIG. 4 is a wiring diagram of a circuit diagram used to realize the function of FIG. 2;

FIG. 5 is a wiring diagram of a circuit diagram used to realize the function of FIG. 2;

FIG. 6 is a wiring diagram of a circuit diagram used to realize the function of FIG. 2;

FIG. 7 is a wiring diagram of a circuit diagram used to realize the function of FIG. 2;

FIG. 8 is a wiring diagram of a circuit diagram used to realize the function of FIG. 2;

FIG. 9 is a wiring diagram of a circuit diagram used to realize the function of FIG. 2;

FIG. 10 is a block diagram of the video block of FIGS. 3 to 9;

FIG. 11 is a block diagram of the video block of FIGS. 3 to 9;

FIG. 12 is a block diagram of the video block of FIGS. 3 to 9;

FIG. 13 is a block diagram of the video block of FIGS. 3 to 9;

FIG. 14 is a block diagram of the video blocks of FIGS. 3 to 9;

FIG. 15 is a block diagram of the video blocks of FIGS. 3 to 9;

FIG. 16 is a block diagram of the video blocks of FIGS. 3 to 9;

FIG. 17 is a block diagram of a DA-ST block shown in FIGS. 3 to 9;

FIG. 18 is a block diagram of the CRT block shown in FIGS. 3 to 9;

FIG. 19 is a block diagram of the CRT block shown in FIGS. 3 to 9;

FIG. 20 is a block diagram of the CRT block of FIGS. 3 to 9;

FIG. 21 is a block diagram of the CRT block shown in FIGS. 3 to 9;

FIG. 22 is a block diagram of the CRT block shown in FIGS. 3 to 9;

FIG. 23 is a block diagram of the CRT block shown in FIGS. 3 to 9;

FIG. 24 is a block diagram of the CRT block shown in FIGS. 3 to 9;

FIG. 25 is a schematic diagram of the control blocks of FIGS. 10 to 15;

FIG. 26 is a schematic diagram of the control blocks of FIGS. 10 to 15;

FIG. 27 is a schematic diagram of the cycle generator of FIGS. 10 to 15;

FIG. 28 is a schematic diagram of the cycle generator of FIGS. 10 to 15;

FIG. 29 is a schematic diagram of the cycle generator of FIGS. 10 to 15;

FIG. 30 is a schematic diagram of the cycle generator of FIGS. 10 to 15;

FIG. 31 is a schematic diagram of the cycle generator of FIGS. 10 to 15;

FIG. 32 is a schematic diagram of the RAS decode block of FIGS. 10 to 15;

FIG. 33 is a schematic diagram of the RAS decode block of FIGS. 10 to 15;

FIG. 34 is a schematic diagram of FIGS. 18 to 24;

FIG. 35 is a schematic diagram of FIGS. 18 to 24;

FIG. 36 is a schematic diagram of the memory pin block of FIGS. 10 to 15;

FIG. 37 is a schematic diagram of the refresh block of FIGS. 10 to 15;

FIG. 38 is a schematic diagram of the refresh block of FIGS. 10 to 15;

FIG. 39 is a schematic diagram of the refresh block of FIGS. 10 to 15;

FIG. 40 is a schematic diagram of the refresh block of FIGS. 10 to 15;

FIG. 41 is a schematic diagram of the ready / reserved block of FIGS. 10 to 15;

FIG. 42 is a schematic diagram of the ready / reserve block of FIGS. 10-15.

FIG. 43 is a schematic diagram of the ready / reserved block of FIGS. 10 to 15;

FIG. 44 is a schematic diagram of the ready / reserve block of FIGS. 10-15.

FIG. 45 is a schematic diagram of the video blocks of FIGS. 18 to 24;

FIG. 46 is a schematic diagram of the video blocks of FIGS. 18 to 24;

FIG. 47 is a schematic diagram of the vertical counter of FIGS. 18 to 24;

FIG. 48 is a schematic diagram of the vertical counter of FIGS. 18 to 24;

FIG. 49 is a schematic diagram of the horizontal counter of FIGS. 18 to 24;

FIG. 50 is a schematic diagram of the horizontal counter of FIGS. 18 to 24;

FIG. 51 is a schematic diagram of another horizontal counter of FIGS. 18 to 24;

FIG. 52 is a schematic diagram of another horizontal counter of FIGS. 18 to 24;

FIG. 53 is a schematic diagram of a basic register used in FIGS. 47 to 52;

FIG. 54 is a schematic diagram of a basic register used in FIGS. 47 to 52;

FIG. 55 is a schematic diagram of the SRDAT block of FIGS. 18 to 24;

FIG. 56 is a schematic diagram of the SRDAT block of FIGS. 18 to 24;

FIG. 57 is a schematic diagram of the SRDAT block of FIGS. 18 to 24;

FIG. 58 is a schematic diagram of the SRDAT block of FIGS. 18 to 24;

FIG. 59 is a schematic diagram of the SRDAT block of FIGS. 18 to 24;

FIG. 60 is a schematic diagram of the SRDAT block of FIGS. 18 to 24;

FIG. 61 is a schematic diagram of the SRDAT block of FIGS. 18 to 24;

FIG. 62 is a schematic diagram of the SRDAT block of FIGS. 18 to 24;

FIG. 63 is a schematic diagram of the SRDAT block of FIGS. 18 to 24;

FIG. 64 is a schematic diagram of the FS decode block of FIGS. 3 to 9;

FIG. 65 is a schematic diagram of the FS decode block of FIGS. 3 to 9;

FIG. 66 is a schematic diagram of the XY register block of FIGS. 3 to 9;

FIG. 67 is a schematic diagram of the XY register block of FIGS. 3 to 9;

FIG. 68 is a schematic diagram of the XY register block of FIGS. 3 to 9;

FIG. 69 is a schematic diagram of the XY register block of FIGS. 3 to 9;

FIG. 70 is a schematic diagram of the XY register block of FIGS. 3 to 9;

FIG. 71 is a schematic diagram of the XY register block of FIGS. 3 to 9;

FIG. 72 is a schematic diagram of the XY register block of FIGS. 3 to 9;

FIG. 73 is a schematic diagram of the XY register block of FIGS. 3 to 9;

FIG. 74 is a schematic diagram of the XY register block of FIGS. 3 to 9;

FIG. 75 is a schematic diagram of the XY register block of FIGS. 3 to 9;

FIG. 76 is a schematic diagram of the XY register block of FIGS. 3 to 9;

FIG. 77 is a schematic diagram of the XY register block of FIGS. 3 to 9;

FIG. 78 is a schematic diagram of the XY register block of FIGS. 3 to 9;

FIG. 79 is a schematic diagram of the control register block of FIGS. 3 to 9;

FIG. 80 is a schematic diagram of the control register block of FIGS. 3 to 9;

FIG. 81 is a schematic diagram of the control register block of FIGS. 3 to 9;

FIG. 82 is a schematic diagram of the control register block of FIGS. 3 to 9;

FIG. 83 is a schematic diagram of the control register block of FIGS. 3 to 9;

FIG. 84 is a schematic diagram of the input pin block of FIGS. 3 to 9;

FIG. 85 is a schematic diagram of the data pin block of FIGS. 3 to 9;

FIG. 86 is a schematic diagram of the data pin block of FIGS. 3 to 9;

FIG. 87 is a schematic diagram of the data pin block of FIGS. 3 to 9;

FIG. 88 is a schematic diagram of the data status block of FIGS. 3 to 9;

FIG. 89 is a schematic diagram of the data status block of FIGS. 3 to 9;

FIG. 90 is a schematic diagram of the data status block of FIGS. 3 to 9;

FIG. 91 is a schematic diagram of the data status block of FIGS. 3 to 9;

FIG. 92 is a schematic diagram of the data status block of FIGS. 3 to 9;

FIG. 93 is a schematic diagram of the data status block of FIGS. 3 to 9;

FIG. 94 is a schematic diagram of the data status block of FIGS. 3 to 9;

FIG. 95 is a schematic diagram of the data status block of FIGS. 3 to 9;

FIG. 96 is a schematic diagram of the data status block of FIGS. 3 to 9;

FIG. 97 is a schematic diagram of the data status block of FIGS. 3 to 9;

FIG. 98 is a schematic diagram of a dual clock used in a video system controller.

FIG. 99 is a schematic diagram of a dual clock used in a video system controller.

FIG. 100 is a schematic diagram of a dual clock used in a video system controller.

FIG. 101 is a schematic diagram of one embodiment of a display memory.

FIG. 102 is a block diagram of the microprocessor of FIG. 1;

FIG. 103 is a diagram showing another embodiment of the video system.

FIG. 104 is a diagram showing another embodiment of the video system.

FIG. 105 is a diagram showing a data transfer cycle.

[Explanation of symbols]

 Reference Signs List 1 microprocessor 3 video system controller (control device) 5 display memory 11 display device 17 external shift register 35 memory cycle generator 37 arbiter 41 column address latch 43 XY address register 45 refresh address counter 47 row address latch 49 multiplexer 65 row Selection invalidation circuit

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification code FI G09G 5/18 G06F 15/64 450H (31) Priority claim number 633385 (32) Priority date July 23, 1984 (33) Priority Claiming country United States (US) (31) Priority claim number 633386 (32) Priority date July 23, 1984 (33) Priority claiming country United States (US) (31) Priority claim number 633387 (32) Priority date July 23, 1984 (33) Priority country United States (US) (31) Priority claim number 633388 (32) Priority date July 23, 1984 (33) Priority country United States (US) (31) Priority claim number 633389 (32) Priority date July 23, 1984 (33) Priority country United States (US) (72) Inventor Robert C. Saden Houston, Texas, USA, number 1220, S.S. Gesner 6425 (72) Inventor Carl M. Gutag United States Ensbrook, Houston, TX 11602 (72) Inventor Raymond Pinkham United States Missouri City, Texas, Lettever Lane 2023 (72) Inventor Mark Novak United States of America Colorado Springs, Colorado Springs, Airport Road 4225-Dee (72) Inventor John Buoy. Moravec, United States Hinlicker Drive, Willow Springs, Illinois 212 (72) Inventor Mark Double. Watts Kennedy Ranch Drive, Hockley, Texas, USA 24307 (72) Inventor Rudy Jay. ULVACTEN, The Third USA Lyon's Drive, Centerville, Ohio 87 (72) Inventor Jerry Van Aken United States Sugar Land, Texas Farnhill 13563

Claims (1)

[Claims] 1. A system memory having a DRAM array for storing data, and a DRAM for storing bitmap data for display
A display memory having an array, a host processor for processing data stored in the system memory and sending the processed data to the display memory, and controlling DRAM refresh for the system memory and the display memory; And a display control device for changing a priority order between a cycle of an access request of the host processor to a display memory and a cycle of the DRAM refresh.