EP0468973B2 - Monitor control circuit - Google Patents

Monitor control circuit Download PDF

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Publication number
EP0468973B2
EP0468973B2 EP90904821A EP90904821A EP0468973B2 EP 0468973 B2 EP0468973 B2 EP 0468973B2 EP 90904821 A EP90904821 A EP 90904821A EP 90904821 A EP90904821 A EP 90904821A EP 0468973 B2 EP0468973 B2 EP 0468973B2
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EP
European Patent Office
Prior art keywords
storage device
signal
control circuit
video storage
input
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EP90904821A
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German (de)
French (fr)
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EP0468973B1 (en
EP0468973A1 (en
Inventor
Stefan Schwarz
Ian Cartwright
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SPEA SOFTWARE GmbH
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SPEA Software GmbH
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Priority to EP92107715A priority Critical patent/EP0500147B2/en
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/395—Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G1/00—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data
    • G09G1/06—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data using single beam tubes, e.g. three-dimensional or perspective representation, rotation or translation of display pattern, hidden lines, shadows
    • G09G1/14—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data using single beam tubes, e.g. three-dimensional or perspective representation, rotation or translation of display pattern, hidden lines, shadows the beam tracing a pattern independent of the information to be displayed, this latter determining the parts of the pattern rendered respectively visible and invisible
    • G09G1/16—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data using single beam tubes, e.g. three-dimensional or perspective representation, rotation or translation of display pattern, hidden lines, shadows the beam tracing a pattern independent of the information to be displayed, this latter determining the parts of the pattern rendered respectively visible and invisible the pattern of rectangular co-ordinates extending over the whole area of the screen, i.e. television type raster
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/393—Arrangements for updating the contents of the bit-mapped memory

Definitions

  • the present invention is concerned with a Monitor control circuit for the control of a a second pixel frequency operating monitor due to a first pixel frequency digital image signal.
  • Computer monitors are known to be in Depends on the requirements regarding the required screen resolution through graphics cards different categories, the themselves through the horizontal and vertical Resolution, i.e. the number of pixels, in horizontal and vertical direction as well as by the pixel frequencies differentiate.
  • Known graphics card standards are for example MDA (320 x 200 pixels, Black and white, at 16 MHz pixel frequency), CGA (320 x 200 pixels, color, at 20 MHz pixel frequency), HERCULES (740 x 400 pixels, black and white, at 27 MHz pixel frequency), EGA (640 x 350 Pixels, color, at 30 MHz pixel frequency), VGA (640 x 480 pixels, color, at 32 MHz pixel frequency), SUPER-EGA (800 x 600 or 1024 x 768 Pixels, color, at 50 MHz pixel frequency, as well recently the so-called HR (High Resolution) graphics systems with 1024 x 768, 1080 x 1024 as well 1600 x 1280 pixels, color, at pixel frequencies between 60 MHz and 170 MHz.
  • DE-A-38 04 460 already discloses a monitor control circuit for controlling one at a second pixel frequency working monitor a digital one having a first pixel frequency Image signal, with a serial-parallel converter on the input side in the form of a shift register, on the Output connected to a video storage device is, in which the input image signal after its Serial-parallel conversion can be filed. Since it is in the memory only by a shift register Serial-parallel conversion is for that purpose the serial-parallel conversion with the clock of the subsystem after the occurrence of the blank signal of the subsystem is clocked input signal at the frequency of its Subsystem clock in the video storage device registered.
  • the raster elements can be controlled in a predetermined sequence and which has an image memory, between a processor and the recording device to arrange a FIFO memory.
  • an interrupt command interrupts the program running in the processor, whereupon new data written into the FIFO memory are, after the processor is filled interrupted program run again.
  • FR-A-2 608 291 is a circuit for Adaptation of a graphics card to a specific one TV standard to a monitor of another television standard known, one by a video processor Data processing carried out periodically generated strobe in relation to the to be omitted or necessary for the conversion inserted picture lines is interrupted. this makes possible no complete update of the monitor image.
  • Monitor control circuit for the control of a a second pixel frequency working monitor due to a first pixel frequency digital image signals according to the generic term of claim 1 by the in the characterizing Part of claim 1 specified features solved
  • the invention is based on the finding that the control of the with the second pixel frequency working monitors with the first pixel frequency is neither synchronized nor usually in is a fixed, even number ratio, by means of of the image signal of the first pixel frequency is then possible is when the data words of the digital image signal initially cached in a FIFO storage device before going into a video storage device to be filed in synchronization with the operation of the monitor at second pixel frequency in a manner known per se can be read out in order to generate the monitor display.
  • FIG. 1 The embodiment of a monitor control device shown in FIG. 1 according to the present invention, those in their entirety with the reference symbol 1, includes a register device 2, one designed as a FIFO storage device first storage device 3, a video storage device 4, a first control device 5, a second control device 6, an oscillator 7, a Display counter device 8 and a serial Readout control device 9.
  • a register device 2 one designed as a FIFO storage device first storage device 3, a video storage device 4, a first control device 5, a second control device 6, an oscillator 7, a Display counter device 8 and a serial Readout control device 9.
  • the register device 2 is on the input side connected to an input data bus 10 on which data words of a digital image signal with the first Pixel frequency are present.
  • the input data bus 10 can for example become a VGA interface extend.
  • the input data bus 10 comprises one connection each for the three basic colors R, G, B and a connector for a brightness bit I.
  • Each Data word represents a pixel with a depth of 4 bits.
  • the register device 2 is also on the input side with a Clock signal input 11 for a clock signal at the first pixel frequency Mistake.
  • the register device 2 receives from of the first control device 5 selection signals SEL0, SEL1, SEL2, SEL3 via a selection data bus 12, which has four bits.
  • the register device is on the output side 2 via a first data bus 13 Inputs of the FIFO memory device 3 in connection, which also has a reset input 14, which a vertical synchronization signal VS (1) of the first Image signal can be fed. Furthermore, the Fifo storage device 3 from the first control device 5 a write command signal at its write input 15 WF fed.
  • the first control device 5 has a clock input 16 for the first clock signal CLK (1), a blank input 17 for the blank signal BL (1) of the first image signal.
  • the FIFO storage device is on the output side 3 via a second data bus 20 with the video storage device 4 in connection.
  • the display counter device 8 has a clock input 21 for the first clock signal CLK (1), one Blank input 22 for the blank signal BL (1) of the first Image signal, a vertical synchronization input 23 for the vertical synchronization signal VS (1) and a horizontal synchronization input 24 for the Horizontal synchronization signal HS (1).
  • the display counter device is on the output side 8 by means of a third data bus 25 for one Horizontal count HC with the second controller 6 as well as with the serial readout control device 9 in connection. Furthermore, the display counter device stands 8 via a fourth data bus 26 for one Vertical count VC with the serial readout controller in connection.
  • the second control device is on the output side 6 with inputs of the video storage device via a control bus 27 and an address bus 28 in Connection.
  • the control bus 27 comprises one line each for a row address takeover signal RAS, a column address takeover signal CAS, a write command signal WB / WE and a data transmission signal DT / OE for the transfer of a data line from the Video storage device 4 into a (not shown) Read shift registers of the same.
  • the serial readout control device 9 stands on the output side via a second control bus 29 for Control signals SC, SOE for reading out the video memory device 4 with control inputs of the latter in connection.
  • the video storage device 4 is in turn on a fifth data bus 30 with a data input of the serial Readout control device 9, which in turn a vertical synchronization input 31 for the vertical synchronization signal VS (2) of the second, monitor-side image signal, a clock input 32 for a second clock signal CLK (2) with the second Pixel frequency, a blank input 33 for the second Blank signal BL (2) and a horizontal synchronization input 34 for the horizontal synchronization signal HS (2) of the second image signal on the monitor side having.
  • the serial readout control device is on the output side 9 via a sixth data bus 35 the digital-to-analog converter DAC of the (not shown) Monitors in connection. Since the structure of the Monitors which correspond to those customary in the prior art, there is no need for their explanation.
  • the register device 2 carries out a serial-parallel conversion of four in a row Data words with the pixel frequency on the input data bus 10, through, the data words generated four times on the output side Number of bits, i.e. data words with a length of 16 Are bits that are given in parallel on the first data bus 13 become.
  • This implementation of 4-bit data words in 16-bit data words takes place under the controller the first control device 5 by means of the selection signals SEL0, ... SEL3, which after completion of this Implementation of the Fifo storage device 3 Write command signal 15 supplies.
  • the second one goes out Control device 6 supplied flag EF over the empty Memory state of the Fifo memory device, whereby the second control device informs about it will that in the Fifo storage device 3 in the video storage device 4 rewritable data words available.
  • the FIFO storage device is 3 constructed such that in this Data words first read when activated by the read command RF first over the second data bus 20 read into the video storage device 4 become.
  • the second control device pro Write cycle of the video storage device 4 or Fifo memory device 3 read cycle a restore a plurality of data words the first storage device 3 into the video storage device 4, the respectively re-stored Data word count, as will be explained, on a case by case basis Case may vary.
  • Control device 6 for the correct storage of the digital image signals in the video storage device information about the number of pixels per line of the image signals present on the input side, which also required by the serial readout control device 9 which is additionally the number of lines of the image of the input signal for the Readout control required.
  • the display counter device 8 in the shown preferred embodiment by Counting the clock signals CLK (1) between two blank signals BL (1) a horizontal count HC (0 ... 9) and by counting the number of blank signals BL (1) between two vertical synchronization signals VS (1) the number of rows by the first Image signal displayed image as a vertical count VC (0 ... 9).
  • the second control device works on one Time base, which is set by the oscillator 7, being the beginning of a cycle by the occurrence of the vertical synchronization signal VS (1) on Reset input is set. That of the second Control device also supplied second (output) blank signal BL (2) is used only for Control refresh of the dynamic video storage device 4 and for controlling the shift register transfer, that is taking over an entire Memory line from the video storage device 4 into the output shift register (not shown) enables and interrupts cycle control for this purpose for controlling the Fifo storage device 3 and the video storage device 4.
  • the control of the video storage device starts addressing the first line and the first column of the video storage device 4 if the flag EF is not present, the address transfer by the row address takeover signal RAS and the column address strobe CAS can be controlled while during write mode the write command signal WB / WE is "low".
  • the takeover of the data words from the FIFO storage device 3 into the video storage device 4 happens in the so-called "page mode", whereby the row addressing and the row address takeover signal RAS while saving Data words in the different columns of this Line remain unchanged, which makes them known per se Way the write speed of the video memory is increased.
  • the exact sequence of individual control signals depends on the manufacturer's specification the video storage device 4 for the at "page mode" write mode provided for these devices. Details of the addressing are under With reference to FIGS. 9 and 10 explained in more detail.
  • Control of serial readout of the video storage device through the serial readout controller 9 takes place in synchronization with the monitor side present second horizontal synchronization signal HS (2), vertical synchronization signal VS (2), clock signal CLK (2) and blank signal BL (2) in one way known per se.
  • the first control device 5 By the first blank signal BL (1) the first control device 5 becomes an initial state set to when a first clock pulse occurs CLK (1) (with circuit-related Delay) to reset a zero selection signal SEL0 and to set a first selection signal SEL1, with the second clock pulse CLK (1) the first Selection signal reset and the second selection signal SEL2 is set, etc., eventually after after the third pulse, the third selection signal SEL3 is reset and the fifo write signal WF is set, whereupon after the fourth clock pulse, the third selection signal reset and the Fifo write signal after the subsequent first bar is reset.
  • This staggered selection signals SELO to SEL3 used to control the register device 2, their detailed structure below with reference 4 is explained in more detail.
  • the register device 2 comprises three 4-bit registers 36, 37, 38 and a 16-bit register 39, all of them with the clock signal input 11 and with the input data bus 10 communicating.
  • the exits the 4-bit registers 36 to 38 are with inputs of the 16-bit register 39.
  • Registers 36 to 39 are in the order of their reference numerals controlled by the selection signals SELO to SEL3, so that control of the 16-bit register 39 by the fourth selection signal SEL3 four 4-bit data words on the input side into a 16-bit data word on the output side are converted.
  • Fig. 5 shows the temporal Relation of the first horizontal synchronization signal HS (1), the first blank signal BL (1) and of the first clock signal CLK (1).
  • the display counter device includes 8 a horizontal counter 40, the Clock input the first clock signal CLK (1) and its Reset input the first horizontal synchronization signal HS (1) are supplied.
  • the first blank signal BL (1) controls the transfer of the meter reading of the horizontal counter 40 in the register 41 for the horizontal count value HC, which on the output side Bus 25 appears.
  • Fig. 7 shows (of course with one opposite Fig. 1 streamlined time base) the schematic temporal relationship between the first Blank signal BL (1), the first horizontal synchronization signal HS (1) and the first vertical synchronization signal VS (1).
  • Fig. 8 shows the vertical counting or line counting relevant portion of the display counter device 8, which comprises a vertical counter 42, whose clock input the first blank signal BL (1) and the reset input of the first vertical synchronization signal VS (1) are supplied, and the on the output side with a register 43 for the vertical count value VC is connected, its clock input again by the first vertical synchronization signal controlled, and the output side with the fourth data bus 26 is connected, on which the Vertical count VC is pending.
  • FIG. 9 shows the structure of the video storage device 4, four in the example shown Storage levels 44 to 47 is divided. This subdivision the video storage device enables one Reduction of the data flow rate when saving and simplified addressing.
  • each of the memory levels 44 to 47 with 512 x 512 storage spaces each of memory levels 44 to 47 at the horizontal address 256 is divided into two.
  • a storage organization results of 1024 x 1024 seats.
  • Horizontal address counter After reaching this Horizontal address is carried out by the (still to be described) Horizontal address counter jumps to the horizontal address 256, at which the storage level is divided is to continue from this horizontal address value divided up to one around the horizontal count HC increased by the number of storage levels Count value before dropping the second line of the first image signal the third line of the first image signal then into the second line of the Video storage device 44 to 47; 4 is filed.
  • the row address counter is incremented after every second reaching the by the number of Memory levels divided horizontal count HC.
  • a block diagram of the second control device is shown in Fig. 10, and includes one Column address counter 48, a row address counter 49 and a control signal generator for generating the Control signals for the video storage device 4.
  • the Column address counter 48 is at its clock input 51 is clocked by the Fifolesesignal RF and is by the first vertical synchronization signal VS (1) reset at its reset input 52 and is further to the third data bus 25 for receiving of the horizontal count value HC connected.
  • the control signal generator 50 receives the clock signal CLK * from the oscillator 7 at its clock input 54, the flag EF from the fifo storage device 3 at its flag input 55, the control signal TC from the column address counter 48 at its control signal input 56 and the secondary-side horizontal synchronization signal HS (2) at its horizontal synchronization input 57 supplied
  • the generation of the row address takeover signal RAS, the column address takeover signal CAS, the data takeover signal DT / OE for the takeover of data from the video memory device in its output shift register and the write signal WB / WE for the video memory device takes place in accordance with the specification of the video memory device used in each case for its operation in the "page-mode" write mode.
  • the readout signal RF can be generated by ANDing the column address takeover signal CAS and the second horizontal synchronization signal HS (2) by means of a gate 58.
  • a register device is used to register the data words present on the input side with the first Pixel frequency in data words of multiple Bit length for a first divided by the plurality Generate pixel frequency, reducing the requirements to the speed of injection into the Fifo storage device can be lowered.
  • the input register device will then unnecessary if the first image signal has a corresponding one has low data word rate or if one Fifo storage device with a correspondingly high Working speed is used. In this In this case, the first control device is also unnecessary.
  • the storage into the video storage device each starting from a horizontal address 0 and one Vertical address 0, i.e. starting from the left upper corner of the video storage device.
  • the subject matter of the invention is not restricted to a certain number of bits of the data words of the processed image signal and is also on Black and white image signals can be used like color image signals. If, for example, a variety of colors from 256 colors is desired, what input data words of 8 bits corresponds to two circuits 1 are connected in parallel.
  • the monitor control circuit serves essentially for control of a monitor whose pixel frequency is different is that of the digital to be displayed on it Image signal.
  • first Pixel frequency of the image signal and the concept of "Second pixel frequency” of the monitor understood so broadly be that including frequency same or similar signals with different Phase or synchronization fall.
  • the invention does not necessarily work with a FIFO memory, but includes first Storage device all such memories from which first stored data or data groups are readable again first, with the alternative of the data groups is irrelevant in which Order the data within the data groups be read out.

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Abstract

A monitor control circuit serves to control a monitor whose display can be generated by reading out a digital video signal with a second pixel frequency from a video storage device, on the basis of a digital video signal having a first pixel frequency. For gap-free conversion of the first video signal to the second video signal, or for combining video signals of different graphics standards, the digital video signal of the first pixel frequency is read into a FIFO storage device (3) with a frequency dependent on the first pixel frequency and the data words of the digital video signal which are to be stored in the video storage device (4) are read out from the FIFO storage device (3) only during time segments in which no data are read out from the video storage device (4), whereby the number of data words which can be read out from the FIFO storage device (3) for storage in the video storage device (4) may vary. <IMAGE>

Description

Die vorliegende Erfindung befaßt sich mit einer Monitorsteuerschaltung für die Ansteuerung eines bei einer zweiten Pixelfrequenz arbeitenden Monitors aufgrund eines eine erste Pixelfrequenz aufweisenden digitalen Bildsignales.The present invention is concerned with a Monitor control circuit for the control of a a second pixel frequency operating monitor due to a first pixel frequency digital image signal.

Computermonitore werden bekannterweise in Abhängigkeit von den Anforderungen bezüglich der geforderten Bildschirmauflösung durch Graphikkarten unterschiedlicher Kategorien angesteuert, die sich untereinander durch die horizontale und vertikale Auflösung, also die Anzahl der Pixel, in horizontaler und vertikaler Richtung sowie durch die Pixelfrequenzen unterscheiden. Bekannte Graphikkarten-Standards sind beispielsweise MDA (320 x 200 Bildpunkte, Schwarzweiß, bei 16 MHz Pixelfrequenz), CGA (320 x 200 Bildpunkte, Farbe, bei 20 MHz Pixelfrequenz), HERCULES (740 x 400 Bildpunkte, Schwarzweiß, bei 27 MHz Pixelfrequenz), EGA (640 x 350 Bildpunkte, Farbe, bei 30 MHz Pixelfrequenz), VGA (640 x 480 Bildpunkte, Farbe, bei 32 MHz Pixelfrequenz), SUPER-EGA (800 x 600 bzw. 1024 x 768 Bildpunkte, Farbe, bei 50 MHz Pixelfrequenz, sowie neuerdings die sogenannten HR (High Resolution)-Graphiksysteme mit 1024 x 768, 1080 x 1024 sowie 1600 x 1280 Bildpunkten, Farbe, bei Pixelfrequenzen zwischen 60 MHz und 170 MHz. Für den Fachmann ist es offensichtlich, daß sich diese verschiedenen Graphik-Standards auch bezüglich der Zeilenfrequenzen, also dem Kehrwert der Horizontalsynchronisationssignalperioden, unterscheiden, die für die genannten Systeme bei 17 kHz, 22 kHz, 25 kHz, 31,5 kHz, 50 kHz sowie 64 bis 84 kHz liegen.Computer monitors are known to be in Depends on the requirements regarding the required screen resolution through graphics cards different categories, the themselves through the horizontal and vertical Resolution, i.e. the number of pixels, in horizontal and vertical direction as well as by the pixel frequencies differentiate. Known graphics card standards are for example MDA (320 x 200 pixels, Black and white, at 16 MHz pixel frequency), CGA (320 x 200 pixels, color, at 20 MHz pixel frequency), HERCULES (740 x 400 pixels, black and white, at 27 MHz pixel frequency), EGA (640 x 350 Pixels, color, at 30 MHz pixel frequency), VGA (640 x 480 pixels, color, at 32 MHz pixel frequency), SUPER-EGA (800 x 600 or 1024 x 768 Pixels, color, at 50 MHz pixel frequency, as well recently the so-called HR (High Resolution) graphics systems with 1024 x 768, 1080 x 1024 as well 1600 x 1280 pixels, color, at pixel frequencies between 60 MHz and 170 MHz. For the specialist it is obvious that these different Graphic standards also with regard to the line frequencies, the reciprocal of the horizontal synchronization signal periods, distinguish that for the mentioned systems at 17 kHz, 22 kHz, 25 kHz, 31.5 kHz, 50 kHz and 64 to 84 kHz.

Es besteht seit längererZeit der Wunsch, die Ausgangssignale der verschiedenen Graphik-Standards mittels eines einzigen Monitores zu Bildschirmbildern umwandeln zu können. Zu diesem Zweck bedient man sich derzeit sogenannter "Multisync"-Monitore, die in der Lage sind, mittels umschaltbarer Schwingkreise mit verschiedenen Horizontalsynchronisationssignalfrequenzen zu arbeiten. Da die Umschaltung des "Multisync"-Monitores von einer Graphiknorm auf die nächste und somit von einer Arbeitsfrequenz auf die nächste mit einer gewissen Einschwingzeit verbunden ist, führt die Umschaltung der Bildschirmdarstellung von einer Graphiknorm auf eine nächste zu zeitlichen Unterbrechungen der Bildschirmanzeige oder anfänglichen Bildstörungen. Selbstredend steigt die Komplexität eines "Multisync"-Monitores mit zunehmender Anzahl der durch diesen bewältigbaren Graphikkarten-Standards an. Eine Anzeige zweier Teilbilder, die von zwei verschiedenen Graphikkarten kreiert werden, auf einem gemeinsamen Bildschirm ist bei den bekannten "Multisync"-Monitoren gleichfalls nicht möglich.There has been a desire for some time now, the output signals of the various graphics standards using a single monitor to create screen images to be able to convert. Served for this purpose so-called "multisync" monitors, which are able to use switchable resonant circuits with different horizontal synchronization signal frequencies to work. Because the switchover the "Multisync" monitor from a graphics standard to the next and thus from one working frequency to the next with a certain settling time is connected, switches the Screen display from a graphics standard to a next to time interruptions of the screen display or initial image interference. Of course, the complexity of one increases "Multisync" monitors with increasing number of through these manageable graphics card standards on. A display of two drawing files, that of two different graphics cards can be created on one common screen is known at the "Multisync" monitors also not possible.

Die DE-A-38 04 460 offenbart bereits eine Monitorsteuerschaltung für Ansteuerung eines bei einer zweiten Pixelfrequenz arbeitenden Monitores aufgrund eines eine erste Pixelfrequenz aufweisenden digitalen Bildsignales, mit einem eingangsseitigen Seriell-Parallel-Wandler in Form eines Schieberegisters, an dessen Ausgang eine Videospeichervorrichtung angeschlossen ist, in die das eingangsseitige Bildsignal nach seiner Seriell-Parallel-Wandlung ablegbar ist. Da es sich bei dem Speicher lediglich um ein Schieberegister zur Seriell-Parallel-Wandlung handelt, das zum Zwecke der Seriell-Parallel-Wandlung mit dem Takt des Subsystems nach dem jeweiligen Auftreten des Blanksignales des Subsystemes getaktet wird, wird das eingangsseitige Bildsignal mit der Frequenz seines Subsystemtaktes in die Videospeichervorrichtung eingeschrieben. Wegen der fehlenden Synchronität des Einschreibens des Bildsignales in die Videospeichervorrichung mit dem ersten Subsystemtakt und des Auslesens aus dem Videospeicher mit dem Hauptsystemtakt können Überschneidungen des Einschreibens und des Auslesens auftreten. Diese Überschneidungen werden nach dem Stand der Technik dadurch ausgeräumt, daß einige Bildelemente eines jeden Teilbildes nicht aktualisiert werden, indem dem Transferzyklus und somit dem Auslesen des Videospeichers ein Vorrang gegenüber dem Auffrischen eingeräumt wird. Die Folge dieser Art der Steuerung ist ein teilweise nicht aktueller Bildinhalt der jeweiligen Teilbilder.DE-A-38 04 460 already discloses a monitor control circuit for controlling one at a second pixel frequency working monitor a digital one having a first pixel frequency Image signal, with a serial-parallel converter on the input side in the form of a shift register, on the Output connected to a video storage device is, in which the input image signal after its Serial-parallel conversion can be filed. Since it is in the memory only by a shift register Serial-parallel conversion is for that purpose the serial-parallel conversion with the clock of the subsystem after the occurrence of the blank signal of the subsystem is clocked input signal at the frequency of its Subsystem clock in the video storage device registered. Because of the lack of synchronicity of writing the image signal into the Video storage device with the first subsystem clock and reading from the video memory the main system clock can overlap of registered and read out occur. This Overlaps are based on the state of the Technology cleared out by having some picture elements of each sub-picture cannot be updated by the transfer cycle and thus the readout of video memory takes precedence over refreshing is granted. The consequence of this kind of Control is part of the current picture content of the respective drawing files.

Aus der DE-A-34 25 636 ist es bekannt, bei einer Raster-Aufzeichnungseinrichtung, deren Rasterelemente in einer vorbestimmten Folge angesteuert werden müssen, und die einen Bildspeicher aufweist, zwischen einem Prozessor und der Aufzeichnungseinrichtung einen Fifo-Speicher anzuordnen. Sobald der Fifo-Speicher leer ist, unterbricht ein Interrupt-Befehl das im Prozessor laufende Programm, woraufhin neue Daten in den Fifo-Speicher eingeschrieben werden, wobei nach dessen Füllen der Prozessor den unterbrochenen Programmlauf wieder aufnimmt.From DE-A-34 25 636 it is known in one Raster recording device, the raster elements can be controlled in a predetermined sequence and which has an image memory, between a processor and the recording device to arrange a FIFO memory. As soon as the Fifo memory is empty, an interrupt command interrupts the program running in the processor, whereupon new data written into the FIFO memory are, after the processor is filled interrupted program run again.

Aus der FR-A-2 608 291 ist eine Schaltung zur Anpassung einer Graphikkarte einer bestimmten Fernsehnorm an einen Monitor einer anderen Fernsehnorm bekannt, bei der eine durch einen Videoprozessor erfolgende Datenverarbeitung durch einen periodisch erzeugten Auftastimpuls in Relation zu den für die Konvertierung nötigen auszulassenden oder einzufügenden Bildzeilen unterbrochen wird. Dies ermöglicht keine vollständige Aktualisierung des Monitorbildes.From FR-A-2 608 291 is a circuit for Adaptation of a graphics card to a specific one TV standard to a monitor of another television standard known, one by a video processor Data processing carried out periodically generated strobe in relation to the to be omitted or necessary for the conversion inserted picture lines is interrupted. this makes possible no complete update of the monitor image.

Im Hinblick auf diesen Stand der Technik liegt der vorliegenden Erfindung die Aufgabe zugrunde, eine Monitorsteuerschaltung zu schaffen, mit der ein bei einer zweiten Pixelfrequenz arbeitender Monitor mittels eines eine erste Pixelfrequenz aufweisenden digitalen Bildsignales ansteuerbar ist, wobei die anzuzeigenden Bildsignale jeweils aktualisiert sein sollen.In view of this state of the art present invention the task of a To create monitor control circuit with the one at using a second pixel frequency monitor a digital one having a first pixel frequency Image signals can be controlled, the ones to be displayed Image signals should be updated in each case.

Diese Aufgabe wird erfindungsgemäß durch eine Monitorsteuerschaltung für die Ansteuerung eines bei einer zweiten Pixelfrequenz arbeitenden Monitores aufgrund eines eine erste Pixelfrequenz aufweisenden digitalen Bildsignales gemäß dem Oberbegriff des Patentanspruchs 1 durch die im kennzeichnenden Teil des Patentanspruchs 1 angegebenen Merkmale gelöstThis object is achieved by a Monitor control circuit for the control of a a second pixel frequency working monitor due to a first pixel frequency digital image signals according to the generic term of claim 1 by the in the characterizing Part of claim 1 specified features solved

Der Erfindung liegtdie Erkenntnis zugrunde, daß die Ansteuerung des mit der zweiten Pixelfrequenz arbeitenden Monitores, die mit der ersten Pixelfrequenz weder synchronisiert ist noch üblicherweise in einem festen, geraden Zahlenverhältnis steht, mittels des Bildsignales der ersten Pixelfrequenz dann möglich ist, wenn die Datenworte des digitalen Bildsignales zunächst in einer Fifo-Speichervorrichtung zwischengespeichert werden, bevor sie in eine Videospeichervorrichtung abgelegt werden, die in Synchronisation mit dem Betrieb des Monitores bei der zweiten Pixelfrequenz in einer an sich bekannten Weise auslesbar ist, um die Monitoranzeige zu erzeugen. Wie noch näher erläutert wird, bewirkt die Übertragung der Datenworte von der Fifo-Speichervorrichtung in die Videospeichervorrichtung eine Steuervorrichtung, die mit der Videospeichervorrichtung und der Fifo-Speichervorrichtung verbunden ist und diese in der Weise ansteuert, daß Datenworte aus der Fifo-Speichervorrichtung in die Videospeichervorrichtung einschreibbar ist.The invention is based on the finding that the control of the with the second pixel frequency working monitors with the first pixel frequency is neither synchronized nor usually in is a fixed, even number ratio, by means of of the image signal of the first pixel frequency is then possible is when the data words of the digital image signal initially cached in a FIFO storage device before going into a video storage device to be filed in synchronization with the operation of the monitor at second pixel frequency in a manner known per se can be read out in order to generate the monitor display. How is explained in more detail, causes the transfer of Data words from the FIFO storage device into the video storage device a control device that with the video storage device and the Fifo storage device is connected and this in the Drives data words from the FIFO storage device into the video storage device is enrollable.

Bevorzugte Weiterbildungen sind in den Unteransprüchen angegeben.Preferred further developments are in the subclaims specified.

Nachfolgend wird unter Bezugnahme auf die beiliegenden Zeichnungen eine bevorzugte Ausführungsform der erfindungsgemäßen Monitorsteuerschaltung näher erläutert. Es zeigen:

  • Fig. 1 ein Blockdiagramm einer Ausführungsform der erfindungsgemäßen Monitorsteuerschaltung;
  • Fig. 2 eine zeitliche Darstellung von Signalverläufen zur Erläuterung der Funktionsweise einer ersten Steuervorrichtung gemäß Fig. 1;
  • Fig. 3 eine Blockdarstellung der in Fig. 1 gezeigten ersten Steuervorrichtung;
  • Fig. 4 ein Blockdiagramm einer in Fig. 1 gezeigten Registervorrichtung;
  • Fig. 5 eine zeitliche Darstellung von Signalverläufen zur Erläuterung der Funktionsweise einer in Fig. 1 gezeigten Anzeigezählervorrichtung;
  • Fig. 6 ein Blockdiagramm eines Details der Anzeigezählervorrichtung gemäß Fig. 1;
  • Fig. 7 eine zeitliche Darstellung von Signalverläufen zur Erläuterung der Funktion eines weiteren Teiles der in Fig. 1 gezeigten Anzeigezählervorrichtung;
  • Fig. 8 ein Blockdiagramm eines weiteren Teiles der in Fig. 1 gezeigten Anzeigezählervorrichtung;
  • Fig. 9 eine schematische Darstellung der Speicherorganisation einer in Fig. 1 gezeigten Videospeichervorrichtung; und
  • Fig. 10 Bockdiagramme der Struktur einer in Fig. 1 gezeigten zweiten Steuervorrichtung.
    • A preferred embodiment of the monitor control circuit according to the invention is explained in more detail below with reference to the accompanying drawings. Show it:
  • 1 is a block diagram of an embodiment of the monitor control circuit according to the invention;
  • FIG. 2 shows a time representation of signal profiles to explain the mode of operation of a first control device according to FIG. 1;
  • Fig. 3 is a block diagram of the first control device shown in Fig. 1;
  • Fig. 4 is a block diagram of a register device shown in Fig. 1;
  • FIG. 5 shows a temporal representation of signal curves to explain the mode of operation of a display counter device shown in FIG. 1;
  • FIG. 6 is a block diagram of a detail of the display counter device of FIG. 1;
  • FIG. 7 shows a time representation of signal profiles to explain the function of a further part of the display counter device shown in FIG. 1;
  • Fig. 8 is a block diagram of another part of the display counter device shown in Fig. 1;
  • Fig. 9 is a schematic representation of the memory organization of a video memory device shown in Fig. 1; and
  • 10 is a block diagram of the structure of a second control device shown in FIG. 1.

    • Die in Fig. 1 gezeigte Ausführungsform einer Monitorsteuervorrichtung gemäß der vorliegenden Erfindung, die in ihrer Gesamtheit mit dem Bezugszeichen 1 bezeichnet ist, umfaßt eine Registervorrichtung 2, eine als Fifo-Speichervorrichtung ausgebildete erste Speichervorrichtung 3, eine Videospeichervorrichtung 4, eine erste Steuervorrichtung 5, eine zweite Steuervorrichtung 6, einen Oszillator 7, eine Anzeigezählervorrichtung 8 und eine serielle Auslesesteuervorrichtung 9.The embodiment of a monitor control device shown in FIG. 1 according to the present invention, those in their entirety with the reference symbol 1, includes a register device 2, one designed as a FIFO storage device first storage device 3, a video storage device 4, a first control device 5, a second control device 6, an oscillator 7, a Display counter device 8 and a serial Readout control device 9.

    Die Registervorrichtung 2 ist eingangsseitig mit einem Eingangsdatenbus 10 verbunden, auf dem Datenworte eines digitalen Bildsignales mit der ersten Pixelfrequenz vorliegen. Der Eingangsdatenbus 10 kann sich beispielsweise zu einer VGA-Schnittstelle erstrecken. Der Eingangsdatenbus 10 umfaßt im Beispielsfall je einen Anschluß für die drei Grundfarben R, G, B und einen Anschluß für ein Helligkeitsbit I. Jedes Datenwort stellt ein Pixel mit 4 bit Tiefe dar. Die Registervorrichtung 2 ist ferner eingangsseitig mit einem Taktsignaleingang 11 für ein Taktsignal mitder ersten Pixelfrequenz versehen. Die Registervorrichtung 2 empfängtvon derersten Steuervorrichtung 5 Auswahlsignale SEL0, SEL1, SEL2, SEL3 über einen Auswahldatenbus 12, der vier Bit hat. Ausgangsseitig steht die Registervorrichtung 2 über einen ersten Datenbus 13 mit Eingängen der Fifo-Speichervorrichtung 3 in Verbindung, welche ferner einen Rücksetzeingang 14 hat, dem ein Vertikalsynchronisationssignal VS(1) des ersten Bildsignales zuführbar ist. Ferner werden der Fifo-Speichervorrichtung 3 von der ersten Steuervorrichtung 5 an ihrem Schreibeingang 15 ein Schreibbefehlssignal WF zugeführt. Die erste Steuervorrichtung 5 hat einen Takteingang 16 für das erste Taktsignal CLK(1), einen Blankeingang 17 für das Blanksignal BL(1) des ersten Bildsignales.The register device 2 is on the input side connected to an input data bus 10 on which data words of a digital image signal with the first Pixel frequency are present. The input data bus 10 can for example become a VGA interface extend. In the example, the input data bus 10 comprises one connection each for the three basic colors R, G, B and a connector for a brightness bit I. Each Data word represents a pixel with a depth of 4 bits. The register device 2 is also on the input side with a Clock signal input 11 for a clock signal at the first pixel frequency Mistake. The register device 2 receives from of the first control device 5 selection signals SEL0, SEL1, SEL2, SEL3 via a selection data bus 12, which has four bits. The register device is on the output side 2 via a first data bus 13 Inputs of the FIFO memory device 3 in connection, which also has a reset input 14, which a vertical synchronization signal VS (1) of the first Image signal can be fed. Furthermore, the Fifo storage device 3 from the first control device 5 a write command signal at its write input 15 WF fed. The first control device 5 has a clock input 16 for the first clock signal CLK (1), a blank input 17 for the blank signal BL (1) of the first image signal.

    Ausgangsseitig steht die Fifo-Speichervorrichtung 3 über einen zweiten Datenbus 20 mit der Videospeichervorrichtung 4 in Verbindung.The FIFO storage device is on the output side 3 via a second data bus 20 with the video storage device 4 in connection.

    Die Anzeigezählervorrichtung 8 hat einen Takteingang 21 für das erste Taktsignal CLK(1), einen Blankeingang 22 für das Blanksignal BL(1) des ersten Bildsignales, einen Vertikalsynchronisationseingang 23 für das Vertikalsynchronisationssignal VS(1) und einen Horizontalsynchronisationseingang 24 für das Horizontalsynchronisationssignal HS(1).The display counter device 8 has a clock input 21 for the first clock signal CLK (1), one Blank input 22 for the blank signal BL (1) of the first Image signal, a vertical synchronization input 23 for the vertical synchronization signal VS (1) and a horizontal synchronization input 24 for the Horizontal synchronization signal HS (1).

    Ausgangsseitig steht die Anzeigezählervorrichtung 8 mittels eines dritten Datenbusses 25 für einen Horizontalzählwert HC mit der zweiten Steuervorrichtung 6 sowie mit der seriellen Auslesesteuervorrichtung 9 in Verbindung. Ferner stehtdie Anzeigezählervorrichtung 8 über einen vierten Datenbus 26 für einen Vertikalzählwert VC mit derseriellen Auslesesteuervorrichtung in Verbindung.The display counter device is on the output side 8 by means of a third data bus 25 for one Horizontal count HC with the second controller 6 as well as with the serial readout control device 9 in connection. Furthermore, the display counter device stands 8 via a fourth data bus 26 for one Vertical count VC with the serial readout controller in connection.

    Ausgangsseitig steht die zweite Steuervorrichtung 6 mit Eingängen der Videospeichervorrichtung über einen Steuerbus 27 und einen Adreßbus 28 in Verbindung. Der Steuerbus 27 umfaßt je eine Leitung für ein Reihenadreßübernahmesignal RAS, ein Spaltenadreßübernahmesignal CAS, ein Schreibbefehlssignal WB/WE und ein Datenübertragungssignal DT/OE für die Übernahme einer Datenzeile aus der Videospeichervorrichtung 4 in ein (nicht gezeigtes) Ausleseschieberegister derselben.The second control device is on the output side 6 with inputs of the video storage device via a control bus 27 and an address bus 28 in Connection. The control bus 27 comprises one line each for a row address takeover signal RAS, a column address takeover signal CAS, a write command signal WB / WE and a data transmission signal DT / OE for the transfer of a data line from the Video storage device 4 into a (not shown) Read shift registers of the same.

    Die serielle Auslesesteuervorrichtung 9 steht ausgangsseitig über einen zweiten Steuerbus 29 für Steuersignale SC, SOE für das Auslesen der Videospeichervorrichtung 4 mit Steuereingängen der letztgenannten in Verbindung. Die Videospeichervorrichtung 4 steht wiederum über einen fünften Datenbus 30 mit einem Dateneingang der seriellen Auslesesteuervorrichtung 9 in Verbindung, die ihrerseits einen Vertikalsynchronisationseingang 31 für das Vertikalsynchronisationssignal VS(2) des zweiten, monitorseitigen Bildsignales, einen Takteingang 32 für ein zweites Taktsignal CLK(2) mit der zweiten Pixelfrequenz, einen Blankeingang 33 für das zweite Blanksignal BL(2) sowie einen Horizontalsynchronisationseingang 34 für das Horizontalsynchronisationssignal HS(2) des zweiten, monitorseitigen Bildsignales aufweist.The serial readout control device 9 stands on the output side via a second control bus 29 for Control signals SC, SOE for reading out the video memory device 4 with control inputs of the latter in connection. The video storage device 4 is in turn on a fifth data bus 30 with a data input of the serial Readout control device 9, which in turn a vertical synchronization input 31 for the vertical synchronization signal VS (2) of the second, monitor-side image signal, a clock input 32 for a second clock signal CLK (2) with the second Pixel frequency, a blank input 33 for the second Blank signal BL (2) and a horizontal synchronization input 34 for the horizontal synchronization signal HS (2) of the second image signal on the monitor side having.

    Ausgangsseitig steht die serielle Auslesesteuervorrichtung 9 über einen sechsten Datenbus 35 mit dem Digital-Analog-Wandler DAC des (nicht dargestellten) Monitors in Verbindung. Da die Struktur des Monitors der im Stand der Technik üblichen entspricht, bedarf es nicht deren Erläuterung.The serial readout control device is on the output side 9 via a sixth data bus 35 the digital-to-analog converter DAC of the (not shown) Monitors in connection. Since the structure of the Monitors which correspond to those customary in the prior art, there is no need for their explanation.

    Nachfolgend wird die Funktionsweise der bevorzugten Ausführungsform gemäß Fig. 1 erläutert, wobei jedoch bezüglich schaltungsmäßigen und funktionellen Details auf die nachfolgende Erläuterung zu den Fig. 2 bis 10 verwiesen wird.Below is the way the preferred works Embodiment according to FIG. 1 explained, wherein however in terms of circuitry and functionality Details on the following explanation 2 to 10 is referred to.

    Die Registervorrichtung 2 führt eine Seriell-Parallel-Umsetzung von jeweils vier aufeinanderfolgenden Datenworten, die mit der Pixelfrequenz am Eingangsdatenbus 10 anliegen, durch, wobei die ausgangsseitig erzeugten Datenworte die vierfache Bitzahl haben, also Datenworte einer Länge von 16 Bit sind, die parallel auf den ersten Datenbus 13 gegeben werden. Diese Umsetzung von 4-bit-Datenworten in 16-bit-Datenworte erfolgt unter der Steuerung der ersten Steuervorrichtung 5 mittels der Auswahlsignale SEL0, ... SEL3, die nach Abschluß dieser Umsetzung der Fifo-Speichervorrichtung 3 ein Schreibbefehlssignal 15 zuführt. Sobald mindestens ein Datenwort in der Fifo-Speichervorrichtung 3 abgespeichert ist, erlischt das von dieser der zweiten Steuervorrichtung 6 zugeführte Flag EF über den leeren Speicherzustand der Fifo-Speichervorrichtung, wodurch die zweite Steuervorrichtung darüber informiert wird, daß in der Fifo-Speichervorrichtung 3 in die Videospeichervorrichtung 4 umspeicherbare Datenworte vorliegen. Wie der Name sagt, ist die Fifo-Speichervorrichtung 3 derart aufgebaut, daß in diese zuerst eingelesene Datenworte bei Ansteuerung durch den Lesebefehl RF zuerst überden zweiten Datenbus 20 in die Videospeichervorrichtung 4 eingelesen werden. Wie nachfolgend noch näher erläutert wird, bewirkt die zweite Steuervorrichtung pro Schreibzyklus der Videospeichervorrichtung 4 bzw. Lesezyklus der Fifo-Speichervorrichtung 3 eine Umspeicherung einer Mehrzahl von Datenworten aus der ersten Speichervorrichtung 3 in die Videospeichervorrichtung 4, wobei die jeweils umgespeicherte Datenwortzahl, wie noch erläutert wird, von Fall zu Fall variieren kann.The register device 2 carries out a serial-parallel conversion of four in a row Data words with the pixel frequency on the input data bus 10, through, the data words generated four times on the output side Number of bits, i.e. data words with a length of 16 Are bits that are given in parallel on the first data bus 13 become. This implementation of 4-bit data words in 16-bit data words takes place under the controller the first control device 5 by means of the selection signals SEL0, ... SEL3, which after completion of this Implementation of the Fifo storage device 3 Write command signal 15 supplies. As soon as at least a data word is stored in the FIFO storage device 3 the second one goes out Control device 6 supplied flag EF over the empty Memory state of the Fifo memory device, whereby the second control device informs about it will that in the Fifo storage device 3 in the video storage device 4 rewritable data words available. As the name suggests, the FIFO storage device is 3 constructed such that in this Data words first read when activated by the read command RF first over the second data bus 20 read into the video storage device 4 become. As explained in more detail below is effected, the second control device pro Write cycle of the video storage device 4 or Fifo memory device 3 read cycle a restore a plurality of data words the first storage device 3 into the video storage device 4, the respectively re-stored Data word count, as will be explained, on a case by case basis Case may vary.

    Wie noch näher erläutert wird, benötigt die zweite Steuervorrichtung 6 für die richtige Abspeicherung des digitalen Bildsignales in der Videospeichervorrichtung eine Information über die Anzahl der Pixel pro Zeile des eingangsseitig anliegenden Bildsignales, die auch durch die serielle Auslesesteuervorrichtung 9 benötigt wird, welche zusätzlich die Anzahl der Zeilen des Bildes des eingangsseitigen Bildsignales für die Auslesesteuerung benötigt. Zu diesem Zwecke ermittelt die Anzeigezählervorrichtung 8 bei dem gezeigten, bevorzugten Ausführungsbeispiel durch Zählen der Taktsignale CLK(1) zwischen zwei Blanksignalen BL(1) einen Horizontalzählwert HC(0...9) sowie durch Zählen der Anzahl der Blanksignale BL(1) zwischen zwei Vertikalsynchronisationssignalen VS(1) die Anzahl der Zeilen des durch das erste Bildsignal dargestellten Bildes als Vertikalzählwert VC(0...9).As will be explained in more detail, the second one is required Control device 6 for the correct storage of the digital image signals in the video storage device information about the number of pixels per line of the image signals present on the input side, which also required by the serial readout control device 9 which is additionally the number of lines of the image of the input signal for the Readout control required. Determined for this purpose the display counter device 8 in the shown preferred embodiment by Counting the clock signals CLK (1) between two blank signals BL (1) a horizontal count HC (0 ... 9) and by counting the number of blank signals BL (1) between two vertical synchronization signals VS (1) the number of rows by the first Image signal displayed image as a vertical count VC (0 ... 9).

    Die zweite Steuervorrichtung arbeitet auf einer Zeitbasis, die durch den Oszillator 7 festgelegt wird, wobei der Anfang eines Zyklus durch das Auftreten des Vertikalsynchronisationssignales VS(1) am Rücksetzeingang festgelegt wird. Das der zweiten Steuervorrichtung gleichfalls zugeführte zweite (ausgangsseitige) Blanksignal BL(2) dient allein zur Steuerung des Auffrischens der dynamischen Videospeichervorrichtung 4 und zur Steuerung der Schieberegisterübernahme, das die Übernahme einer ganzen Speicherzeile aus der Videospeichervorrichtung 4 in das Ausgangsschieberegister (nicht dargestellt) ermöglicht, und unterbricht zu diesem Zweck die Zyklussteuerung für die Ansteuerung der Fifo-Speichervorrichtung 3 und der Videospeichervorrichtung 4. Die Ansteuerung der Videospeichervorrichtung beginnt mit der Adressierung der ersten Zeile und der ersten Spalte der Videospeichervorrichtung 4 bei Nicht-Vorliegen des Flag EF, wobei die Adressenübernahme durch das Reihenadreßübernahmesignal RAS und das Spaltenadreßübernahmesignal CAS gesteuert werden, wobei während des Schreibmodus das Schreibbefehlssignal WB/WE "tief" ist. Die Übernahme der Datenworte von der Fifo-Speichervorrichtung 3 in die Videospeichervorrichtung 4 geschieht im sogenannten "page-mode", wobei die Zeilenadressierung und das Zeilenadreßübernahmesignal RAS während des Einspeicherns von Datenworten in die verschiedenen Spalten dieser Zeile unverändert bleiben, wodurch in an sich bekannter Weise die Einschreibgeschwindigkeit des Videospeichers erhöht wird. Die genaue Abfolge der einzelnen Steuersignale hängt von der Herstellerspezifikation der Videospeichervorrichtung 4 für den bei diesen Vorrichtungen vorgesehenen "page-mode"-Schreibmodus. Details der Adressierung werden unter Bezugnahme auf die Fig. 9 und 10 näher erläutert.The second control device works on one Time base, which is set by the oscillator 7, being the beginning of a cycle by the occurrence of the vertical synchronization signal VS (1) on Reset input is set. That of the second Control device also supplied second (output) blank signal BL (2) is used only for Control refresh of the dynamic video storage device 4 and for controlling the shift register transfer, that is taking over an entire Memory line from the video storage device 4 into the output shift register (not shown) enables and interrupts cycle control for this purpose for controlling the Fifo storage device 3 and the video storage device 4. The control of the video storage device starts addressing the first line and the first column of the video storage device 4 if the flag EF is not present, the address transfer by the row address takeover signal RAS and the column address strobe CAS can be controlled while during write mode the write command signal WB / WE is "low". The takeover of the data words from the FIFO storage device 3 into the video storage device 4 happens in the so-called "page mode", whereby the row addressing and the row address takeover signal RAS while saving Data words in the different columns of this Line remain unchanged, which makes them known per se Way the write speed of the video memory is increased. The exact sequence of individual control signals depends on the manufacturer's specification the video storage device 4 for the at "page mode" write mode provided for these devices. Details of the addressing are under With reference to FIGS. 9 and 10 explained in more detail.

    Die Steuerung des seriellen Auslesens der Videospeichervorrichtung durch die serielle Auslesesteuervorrichtung 9 erfolgt in Synchronisation mit dem monitorseitig vorliegenden zweiten Horizontalsynchronisationssignal HS(2), Verikalsynchronisationssignal VS(2), Taktsignal CLK(2) und Blanksignal BL(2) in einer an sich bekannten Weise.Control of serial readout of the video storage device through the serial readout controller 9 takes place in synchronization with the monitor side present second horizontal synchronization signal HS (2), vertical synchronization signal VS (2), clock signal CLK (2) and blank signal BL (2) in one way known per se.

    An dieser Stelle sei auf einen wesentlichen Aspekt der Erfindung hingewiesen, der sich aus der erfindungsgemäßen Umsetzung des Bildsignales der ersten Pixelfrequenz in ein Bildsignal der zweiten Pixelfrequenz ergibt Es ist möglich, nicht nur das am ausgangsseitigen sechsten Datenbus 35 generierte Bildsignal dem Monitor zuzufüren, sondern auch dieses Bildsignal mit einem zweiten, synchronen Bildsignal zu kombinieren, von dem die ausgangsseitige Zeitbasis (VS(2), CLK(2), BL(2), HS(2)) erhalten wurde. Damit ist eine Kombination eines beliebigen ersten Bildsignales, der am Eingang 10, 11 der Schaltung anliegt, mit einem beliebigen zweiten, von einem anderen Graphikstandard stammenden Bildsignal in der Weise möglich, daß das erste Bildsignal auf einer Teilfläche des Monitors zur Anzeige gebracht wird und das zweite Bildsignal auf der restlichen Monitorfläche gezeigt wird.At this point, let's focus on one essential aspect pointed out the invention, which results from the invention Implementation of the image signal of the first pixel frequency into an image signal of the second pixel frequency it is possible not only that on output sixth data bus 35 generated Image signal to the monitor, but also this Image signal with a second, synchronous image signal to combine, of which the output side Time base (VS (2), CLK (2), BL (2), HS (2)) was obtained. It is a combination of any first Image signal, the input 10, 11 of the circuit is present, with any second one other graphics standard derived image signal in possible in such a way that the first image signal on a Part of the monitor is displayed and the second image signal on the remaining monitor surface will be shown.

    Die Fig. 2 und 3 verdeutlichen die Betriebsweise der ersten Steuervorrichtung 5, die im wesentlichen als Zähler arbeitet. Durch das erste Blanksignal BL(1) wird die erste Steuervorrichtung 5 in einen Anfangszustand gesetzt, um bei Auftreten eines ersten Taktpulses CLK(1) (mit schaltungstechnisch bedingter Verzögerung) ein nulltes Auswahlsignal SEL0 rückzusetzen und ein erstes Auswahlsignal SEL1 zu setzen, wobei beim zweiten Taktpuls CLK(1) das erste Auswahlsignal rückgesetzt und das zweite Auswahisignal SEL2 gesetzt wird, usw., wobei schließlich nach dem dritten Puls das dritte Auswahlsignal SEL3 rückgesetzt und das Fifo- Schreibsignal WF gesetzt wird, woraufhin nach dem vierten Taktpuls das dritte Auswahlsignal rückgesetzt und das Fifo-Schreibsignal nach dem darauffolgenden ersten Takt rückgesetzt wird. Diese gestaffelten Auswahlsignale SELO bis SEL3 werden zur Steuerung der Registervorrichtung 2 verwendet, deren detaillierter Aufbau nachfolgend unter Bezugnahme auf Fig. 4 näher erläutert wird.2 and 3 illustrate the mode of operation the first control device 5, which essentially works as a counter. By the first blank signal BL (1) the first control device 5 becomes an initial state set to when a first clock pulse occurs CLK (1) (with circuit-related Delay) to reset a zero selection signal SEL0 and to set a first selection signal SEL1, with the second clock pulse CLK (1) the first Selection signal reset and the second selection signal SEL2 is set, etc., eventually after after the third pulse, the third selection signal SEL3 is reset and the fifo write signal WF is set, whereupon after the fourth clock pulse, the third selection signal reset and the Fifo write signal after the subsequent first bar is reset. This staggered selection signals SELO to SEL3 used to control the register device 2, their detailed structure below with reference 4 is explained in more detail.

    Die Registervorrichtung 2 umfaßt drei 4-bit-Register 36, 37, 38 und ein 16-bit-Register 39, die sämtlich mit dem Taktsignaleingang 11 und mit dem Eingangsdatenbus 10 in Verbindung stehen. Die Ausgänge der 4-bit-Register 36 bis 38 sind mit Eingängen des 16-bit-Registers 39 verbunden. Die Register 36 bis 39 werden in der Reihenfolge ihrer Bezugszeichen von den Auswahisignalen SELO bis SEL3 angesteuert, so daß Ansteuerung des 16-bit-Registers 39 durch das vierte Auswahlsignal SEL3 vier eingangsseitige 4-bit-Datenworte in ein ausgangsseitiges 16-bit-Datenwort umgewandelt sind.The register device 2 comprises three 4-bit registers 36, 37, 38 and a 16-bit register 39, all of them with the clock signal input 11 and with the input data bus 10 communicating. The exits the 4-bit registers 36 to 38 are with inputs of the 16-bit register 39. Registers 36 to 39 are in the order of their reference numerals controlled by the selection signals SELO to SEL3, so that control of the 16-bit register 39 by the fourth selection signal SEL3 four 4-bit data words on the input side into a 16-bit data word on the output side are converted.

    Nachfolgend wird unter Bezugnahme auf die Fig. 5 bis 8 die Struktur und Funktion der Anzeigezählervorrichtung 8 näher erläutert. Fig. 5 zeigt die zeitliche Relation des ersten Horizontalsynchronisationssignales HS(1), des ersten Blanksignales BL(1) und des ersten Taktsignales CLK(1).In the following, with reference to FIG. 5 to 8 show the structure and function of the display counter device 8 explained in more detail. Fig. 5 shows the temporal Relation of the first horizontal synchronization signal HS (1), the first blank signal BL (1) and of the first clock signal CLK (1).

    Wie in Fig. 6 gezeigt ist, umfaßt die Anzeigezählervorrichtung 8 einen Horizontalzähler 40, dessen Takteingang das erste Taktsignal CLK(1) und dessen Rücksetzeingang das erste Horizontalsynchronisationssignal HS(1) zugeführt werden. Das erste Blanksignal BL(1) steuert die Übernahme des Zählerstandes des Horizontalzählers 40 in das Register 41 für den Horizontalzählwert HC, der ausgangsseitig am Bus 25 erscheint.As shown in Fig. 6, the display counter device includes 8 a horizontal counter 40, the Clock input the first clock signal CLK (1) and its Reset input the first horizontal synchronization signal HS (1) are supplied. The first blank signal BL (1) controls the transfer of the meter reading of the horizontal counter 40 in the register 41 for the horizontal count value HC, which on the output side Bus 25 appears.

    Fig. 7 zeigt (selbstverständlich mit einer gegenüber Fig. 1 gestrafften Zeitbasis) den schematisierten zeitlichen Zusammenhang zwischen dem ersten Blanksignal BL(1), dem ersten Horizontalsynchronisationssignal HS(1) und dem ersten Vertikalsynchronisationssignal VS(1).Fig. 7 shows (of course with one opposite Fig. 1 streamlined time base) the schematic temporal relationship between the first Blank signal BL (1), the first horizontal synchronization signal HS (1) and the first vertical synchronization signal VS (1).

    Fig. 8 zeigt den die Vertikalzählung oder Zeilenzählung betreffenden Anteil der Anzeigezählervorrichtung 8, welcher einen Vertikalzähler 42 umfaßt, dessen Takteingang das erste Blanksignal BL(1) und dessen Rücksetzeingang das erste Vertikalsynchronisationssignal VS(1) zugeführt werden, und der ausgangsseitig mit einem Register 43 für den Vertikal-Zählwert VC verbunden ist, dessen Takteingang wiederum durch das erste Vertikalsynchronisationssignal angesteuert, und das ausgangsseitig mit dem vierten Datenbus 26 in Verbindung steht, auf dem der Vertikalzählwert VC ansteht.Fig. 8 shows the vertical counting or line counting relevant portion of the display counter device 8, which comprises a vertical counter 42, whose clock input the first blank signal BL (1) and the reset input of the first vertical synchronization signal VS (1) are supplied, and the on the output side with a register 43 for the vertical count value VC is connected, its clock input again by the first vertical synchronization signal controlled, and the output side with the fourth data bus 26 is connected, on which the Vertical count VC is pending.

    Fig. 9 zeigt die Struktur der Videospeichervorrichtung 4, die in dem gezeigten Beispielsfall in vier Speicherebenen 44 bis 47 unterteilt ist. Diese Unterteilung der Videospeichervorrichtung ermöglicht eine Reduktion der Datenflußrate bei der Einspeicherung und eine vereinfachte Adressierung. Bei dem gezeigten Beispielsfall ist jede der Speicherebenen 44 bis 47 mit 512 x 512 Speicherplätzen versehen, wobei jede der Speicherebenen 44 bis 47 bei der Horizontaladresse 256 gezweiteilt ist. Es ergibt sich eine Speicherorganisation von 1024 x 1024 Plätzen. Beim Ablegen der Datenworte in der Videospeichervorrichtung werden die Daten jeweils gleichzeitig den Eingängen D0 bis D3 zugeführt, wobei in der beschriebenen "page-mode"-Speicherweise zunächst die erste Zeile des Bildes in den jeweiligen ersten Speicherzeilen zwischen den Horizontaladressen 0 und einer Maximaladresse abgelegt werden, die dem Horizontalzählwert HC geteilt durch die Anzahl 4 der Speicherebenen entspricht. Nach Erreichen dieser Horizontaladresse vollfürt der (noch zu beschreibende) Horizontaladreßzähler einen Sprung zu der Horizontaladresse 256, bei der die Speicherebene unterteilt ist, um fortfahrend von diesem Horizontaladreßwert bis zu einem um den Horizontalzählwert HC geteilt durch die Anzahl der Speicherebenen erhöhten Wert zu zählen, bevor nach erfolgtem Ablegen der zweiten Zeile des ersten Bildsignales die dritte Zeile des ersten Bildsignales sodann in die zweite Zeile der Videospeichervorrichtung 44 bis 47; 4 abgelegt wird. Das Inkrementieren des Reihenadreßzählers erfolgt nach jedem zweiten Erreichen des um die Anzahl der Speicherebenen geteilten Horizontalzählwertes HC.Fig. 9 shows the structure of the video storage device 4, four in the example shown Storage levels 44 to 47 is divided. This subdivision the video storage device enables one Reduction of the data flow rate when saving and simplified addressing. With the shown For example, each of the memory levels 44 to 47 with 512 x 512 storage spaces, each of memory levels 44 to 47 at the horizontal address 256 is divided into two. A storage organization results of 1024 x 1024 seats. When dropping of the data words in the video storage device the data will be input at the same time D0 to D3 supplied, in which described "page-mode" - initially the first Line of the image in the respective first memory lines between the horizontal addresses 0 and a maximum address that the Horizontal count HC divided by the number 4 of Corresponds to storage levels. After reaching this Horizontal address is carried out by the (still to be described) Horizontal address counter jumps to the horizontal address 256, at which the storage level is divided is to continue from this horizontal address value divided up to one around the horizontal count HC increased by the number of storage levels Count value before dropping the second line of the first image signal the third line of the first image signal then into the second line of the Video storage device 44 to 47; 4 is filed. The row address counter is incremented after every second reaching the by the number of Memory levels divided horizontal count HC.

    Ein Blockdiagramm der zweiten Steuervorrichtung ist in Fig. 10 wiedergegeben, und umfaßt einen Spaltenadreßzähler 48, einen Reihenadreßzähler 49 und einen Steuersignalgenerator zum Erzeugen der Steuersignale für die Videospeichereinrichtung 4. Der Spaltenadreßzähler 48 wird an seinem Takteingang 51 durch das Fifolesesignal RF getaktet und wird durch das erste Vertikalsynchronisationssignal VS(1) an seinem Rücksetzeingang 52 rückgesetzt und ist ferner an den dritten Datenbus 25 zum Empfangen des Horizontalzählwertes HC angeschlossen.A block diagram of the second control device is shown in Fig. 10, and includes one Column address counter 48, a row address counter 49 and a control signal generator for generating the Control signals for the video storage device 4. The Column address counter 48 is at its clock input 51 is clocked by the Fifolesesignal RF and is by the first vertical synchronization signal VS (1) reset at its reset input 52 and is further to the third data bus 25 for receiving of the horizontal count value HC connected.

    Nach Rücksetzen des Spaltenadreßzählers 48 vollführt dieser die soeben unter Bezugnahme auf Fig. 9 erläuterte Horizontaladreßzählung. Im Beispielsfall ist dies eine von Null bis zu einem Viertel des Horizontalzählwertes HC ansteigende Zählung mit nachfolgendem Sprung auf die Mittenhorizontaladresse 256, um anschließend wiederum die Adresse kontinuierlich zu inkrementieren, bis diese Mittenadresse um ein Viertel des Horizontalzählwertes HC übertroffen ist. Zu diesem Zeitpunkt erscheint eine "1" am Steuerausgang TC des Spaltenadreßzählers 48, welcher mit dem Takteingang 53 des Reihenadreßzählers 49 verbunden ist, der durch diesen Signalpuls inkrementiert wird, bis er durch Auftreten des ersten Vertikalsynchronisationssignales VS(1) rückgesetzt wird.After resetting the column address counter 48 the latter is just performing the reference to Fig. 9 explained horizontal address counting. In the example case this is one from zero to a quarter of the horizontal count HC increasing count with subsequent jump to the middle horizontal address 256 to then turn the address again increment continuously until this center address by a quarter of the horizontal count HC is exceeded. At this point, a appears "1" at the control output TC of the column address counter 48, which with the clock input 53 of the row address counter 49 is connected by this signal pulse is incremented until it occurs of the first vertical synchronization signal VS (1) is reset.

    Dem Steuersignalgenerator 50 werden das Taktsignal CLK* vom Oszillator 7 an dessen Takteingang 54, das Flag EF von der Fifo-Speichervorrichtung 3 an dessen Flageingang 55 das Steuersignal TC vom Spaltenadreßzähler 48 an dessen Steuersignaleingang 56 sowie das sekundärseitige Horizontalsynchronisationssignal HS(2) an dessen Horizontalsynchronisationseingang 57 zugeführt Die Erzeugung des Reihenadreßübernahmesignals RAS, des Spaltenadreßübernahmesignal CAS, des Datenübernahmesignales DT/OE für die Übernahme von Daten aus der Videospeichervorrichtung in dessen Ausgangsschieberegister und des schreibsignales WB/WE für die Videospeichervorrichtung erfolgt gemäß der Spezifikation der jeweils verwendeten Videospeichervorrichtung für deren Betrieb in den "page-mode"-Schreibmodus. Das Auslesesignal RF kann durch UND-Verknüpfen des Spaltenadreßübernahmesignales CAS und des zweiten Horizontalsynchronisationssignales HS(2) mittels eines Gatters 58 erzeugt werden.The control signal generator 50 receives the clock signal CLK * from the oscillator 7 at its clock input 54, the flag EF from the fifo storage device 3 at its flag input 55, the control signal TC from the column address counter 48 at its control signal input 56 and the secondary-side horizontal synchronization signal HS (2) at its horizontal synchronization input 57 supplied The generation of the row address takeover signal RAS, the column address takeover signal CAS, the data takeover signal DT / OE for the takeover of data from the video memory device in its output shift register and the write signal WB / WE for the video memory device takes place in accordance with the specification of the video memory device used in each case for its operation in the "page-mode" write mode. The readout signal RF can be generated by ANDing the column address takeover signal CAS and the second horizontal synchronization signal HS (2) by means of a gate 58.

    Bei dem beschriebenen Ausführungsbeispiel wird eine Registervorrichtung verwendet, um die eingangsseitig anliegenden Datenworte mit der ersten Pixelfrequenz in Datenworte von mehrfacher Bitlänge bei einer durch die Mehrzahl geteilten ersten Pixelfrequenz zu erzeugen, wodurch die Anforderungen an die Einspeicherungsgeschwindigkeit in die Fifo-Speichervorrichtung gesenkt werden können. Die eingangsseitige Registervorrichtung wird jedoch dann entbehrlich, wenn das erste Bildsignal eine entsprechende niedrige Datenwortrate hat oder wenn eine Fifo-Speichervorrichtung mit entsprechend hoher Arbeitsgeschwindigkeit verwendet wird. In diesem Fall ist auch die erste Steuervorrichtung entbehrlich.In the described embodiment a register device is used to register the data words present on the input side with the first Pixel frequency in data words of multiple Bit length for a first divided by the plurality Generate pixel frequency, reducing the requirements to the speed of injection into the Fifo storage device can be lowered. However, the input register device will then unnecessary if the first image signal has a corresponding one has low data word rate or if one Fifo storage device with a correspondingly high Working speed is used. In this In this case, the first control device is also unnecessary.

    Bei der erläuterten Ausführungsform wird die Abspeicherung in die Videospeichervorrichtung jeweils ausgehend von einer Horizontaladresse 0 und einer Vertikaladresse 0, also ausgehend von der linken oberen Ecke der Videospeichervorrichtung vorgenommen.In the illustrated embodiment, the storage into the video storage device each starting from a horizontal address 0 and one Vertical address 0, i.e. starting from the left upper corner of the video storage device.

    Der Erfindungsgegenstand ist nicht beschränkt auf eine bestimmte Anzahl von Bits der Datenworte des verarbeiteten Bildsignales und ist ebenso auf Schwarzweiß-Bildsignale wie Farb-Bildsignale anwendbar. Wenn beispielsweise eine Farbvielfalt von 256 Farben gewünscht ist, was Eingangsdatenworten von 8 bit entspricht, so können zwei Schaltungen gemäß Fig. 1 parallel geschaltet werden.The subject matter of the invention is not restricted to a certain number of bits of the data words of the processed image signal and is also on Black and white image signals can be used like color image signals. If, for example, a variety of colors from 256 colors is desired, what input data words of 8 bits corresponds to two circuits 1 are connected in parallel.

    Obwohl die bevorzugte Ausführungsform des Erfindungsgegenstande hardware-mäßig mittels Gate-Arrays implementiert ist, ist es denkbar, Zählervorrichtungen und Steuervorrichtungen sowie eine geeignete Ansteuervorrichtung für die erste Speichervorrichtung, die diese als Fifo-Speichervorrichtung arbeiten läßt, software-mäßig zu realisieren.Although the preferred embodiment of the subject invention in terms of hardware by means of gate arrays is implemented, it is conceivable counter devices and control devices and a suitable one Control device for the first storage device, which this as a FIFO storage device lets work to implement software-wise.

    Grundsätzlich dient die erfindungsgemäße Monitorsteuerschaltung im wesentlichen zur Ansteuerung eines Monitors, dessen Pixelfrequenz verschieden ist von der des auf diesem darzustellenden digitalen Bildsignales. Jedoch soll der Begriff der "ersten Pixelfrequenz" des Bildsignales und der Begriff der "zweiten Pixelfrequenz" des Monitors so breit verstanden werden, daß hierunter auch frequenzmäßig gleiche oder ähnliche Signale mit unterschiedlicher Phase bzw. Synchronisation fallen.Basically, the monitor control circuit according to the invention serves essentially for control of a monitor whose pixel frequency is different is that of the digital to be displayed on it Image signal. However, the term "first Pixel frequency "of the image signal and the concept of "Second pixel frequency" of the monitor understood so broadly be that including frequency same or similar signals with different Phase or synchronization fall.

    Die Erfindung arbeitet nicht notwendigerweise mit einem Fifo-Speicher, sondern umfaßt als erste Speichervorrichtung alle solchen Speicher, aus denen zuerst abgespeicherte Daten oder Datengruppen zuerst wieder auslesbar sind, wobei es bei der Alternative der Datengruppen unmaßgeblich ist, in welcher Reihenfolge die Daten innerhalb der Datengruppen ausgelesen werden.The invention does not necessarily work with a FIFO memory, but includes first Storage device all such memories from which first stored data or data groups are readable again first, with the alternative of the data groups is irrelevant in which Order the data within the data groups be read out.

    Claims (17)

    1. A monitor control circuit for driving a monitor, which displays a monitor image of an image signal at a second pixel frequency, on the basis of a digital image signal having a first pixel frequency,
      wherein the image signal having the first pixel frequency is supplied to an input of the monitor control circuit, and
      wherein the image signal of the first pixel frequency is not synchronized with the monitor image display of the second pixel frequency,
      the monitor control circuit comprising
      a FIFO storage device (3),
      a first control device (5) writing the image signal provided at the input of the monitor control circuit with a frequency dependent on the first pixel frequency into the FIFO storage device (3),
      a video storage device (4) connected to the output of the FIFO storage device,
      a second control device (6) connected to the video storage device (4) and the FIFO storage device (3) and reading data words of the digital image signal from the FIFO storage device (3) and writing them into the video storage device (4) in such a manner that the reading of the data words from the FIFO storage device (3) is interrupted when data words are being read from the video storage device (4) and that the reading from the FIFO storage device (3) is interrupted when a signal (EF) indicating the empty condition of same is generated,
      so that the number of data words which can be re-stored from the FIFO storage device (3) to the video storage device (4) varies.
    2. A monitor control circuit according to claim 1, characterized by
      a register device (2), which has its input side connected to the FIFO storage device (3) and by means of which the data words of the digital image signal received at the first pixel frequency can be converted into data words, which include a multiple number of bits with respect to the number of bits in the received data words, at a first pixel frequency divided by said multiple.
    3. A monitor control circuit according to claim 2, characterized in that
      the register device (2) includes a number of first registers (36, 37, 38) equal to said multiple minus one, each of said registers (36, 37, 38) storing one of the received data words,
      the register device (2) additionally includes a second register (39) for storing the data word which includes the multiple number of bits, said second register (39) having part of its inputs connected to outputs of said first registers (36, 37, 38) and another part of its inputs connected to a bus (10) for storing one of the received data words, and
      the first control device (5) sequentially controls each of the first registers (36, 37, 38) and the second register (39) by a selection signal (SEL0, SEL1, SEL2, SEL3) for accepting input-side data words.
    4. A monitor control circuit according to claim 3, characterized in that
      the first control device (5) is provided with a clock input (16), which is adapted to have supplied thereto a clock signal (CLK(1)) having the first pixel frequency, and with a holding input (17), which is adapted to have supplied thereto a blank signal (BL(1)) of the first image signal, and
      the first control device (5) has a number of selection outputs (12) corresponding to said multiple and is constructed in such a way that the respective selection signals (SEL0, SEL1, SEL2, SEL3) at the selection outputs (12) are displaced with respect to one another by a first pixel period.
    5. A monitor control circuit according to claim 3 or 4, characterized in that
      the first control device (5) additionally includes a write command output for producing a write command (WF) for the FIFO storage device (3), said write command (WF) being displaced by at least one first pixel period with respect to the selection signal (SEL3) for the second register (39), and that the FIFO storage device (3) has a write command input (15) and accepts a waiting data word when a write command is applied.
    6. A monitor control circuit according to one of claims 1 to 5, characterized by
      a display counting device (8), which is adapted to have supplied thereto the first clock signal (CLK(1)) having the first pixel frequency and the first blank signal (BL(1)) of the first image signal, said display counting device (8) being provided with a horizontal counter (40, 41) for counting the first clock signals (CLK(1)) between two first blank signals (BL(1)).
    7. A monitor control circuit according to claim 6, characterized in that
      the display counting device (8) additionally included a vertical counter (42, 43), which is adapted to have supplied thereto the first blank signals (BL(1)) and the first vertical synchronization signals (VS(1)) and by means of which the number of first blank signals (BL(1)) between two first vertical synchronization signals (VS(1)) can be ascertained.
    8. A monitor control circuit according to one of claims 1 to 7, characterized in that
      FIFO storage device (3) has a reset input (14), which is adapted to have supplied thereto the first vertical synchronization signal (VS(1)).
    9. A monitor control circuit according to claim 8, characterized in that
      the FIFO storage device (3) has a flag output for a flag (EF) indicating the empty condition of the storage areas of the FIFO storage device (3), and
      the flag output is connected to a flag input of the second control device (6).
    10. A monitor control circuit according to one of claims 1 to 7, characterized in that
      the second control device (6) has a read command output (RF) which is connected to a read control input of the FIFO storage device, and
      the FIFO storage device (3) is constructed in such a way that in response to each read command pulse (RF) applied to its read control input it will transfer a data word to the video storage device (4).
    11. A monitor control circuit according to one of claims 1 to 11, characterized in that
      the second control device (6) has a reset input, which is adapted to have supplied thereto the vertical synchronization signal (VS(1)) of the first image signal, and
      the second control device (6) is additionally provided with a clock input which has connected thereto an oscillator (7).
    12. A monitor control circuit according to one of claims 6 to 11, characterized in that
      the second control device (6) is connected to the display counting device (8) and receives therefrom at least the count (HC) of the horizontal counter (40, 41).
    13. A monitor control circuit according to claim 11 or 12 in dependence on claim 10, characterized in that for driving the video storage device (4) on the time basis of the clock predetermined by the oscillator (7), the second control device (6) will start from a logical initial condition and produce, per read cycle, one read command pulse (RF) for the FIFO storage device (3), one horizontal address signal (ADR) and one vertical address signal (ADR) for addressing the video storage device (4) and video storage control signals (RAS, CAS, WB/WE, DT/OE) in response to the appearance of the first vertical synchronization signal (VS(1)).
    14. A monitor control circuit according to claim 13, characterized in that
      the video storage device (4) is provided with an output shift register, and
      the video storage control signals comprise a column address transfer signal (CAS), a line address transfer signal (RAS), a write signal (WB/WE) representative of the write condition for writing into the video storage device (4) and a shift register transfer signal (DT/OE) permitting transfer of a data word from the video storage device (4) to the output shift register.
    15. A monitor control circuit according to claim 14, characterized in that the second control device (6) produces the above-mentioned control signals for the video storage device (4) in a way, dependent on the specification of the video storage device (4) used, such that the data words supplied by the FIFO storage device (3) are written into the video storage device (4) in the so-called "page-mode" memory control fashion, in the case of which the line address signal (ADR) and the line address transfer signal (RAS) for the video storage device (4) remain unchanged when data are being stored in a line of the video storage device (4).
    16. A monitor control circuit according to one of claims 1 to 15, characterized in that
      the video storage device (4) is subdivided into a plurality of storage levels (44 to 47) adapted to be horizontally and vertically addressed at the same time and adapted to be written and read at the same time.
    17. A monitor control circuit according to one of claims 1 to 16, characterized in that
      the video storage device (4) is subdivided at at least one horizontal address (256) into at least one first and one second storage area (0 to 255, 256 to 512), the second control device (6) is constructed such that it will first count the horizontal address from zero to the count (HC) of the horizontal counter (40, 41) and, subsequently, after a jump, it will continue to count from the horizontal address (256), which determines the horizontal division of the video storage device (4, 44 to 47), up to the horizontal division address (256) increased by the count (HC) of the horizontal counter (40, 41), and
      the horizontal address produced by the second control device (6) is reset by the first vertical synchronization signal (VS(1)).
    EP90904821A 1989-05-12 1990-03-21 Monitor control circuit Expired - Lifetime EP0468973B2 (en)

    Priority Applications (1)

    Application Number Priority Date Filing Date Title
    EP92107715A EP0500147B2 (en) 1989-05-12 1990-03-21 Method of and device for controlling a monitor

    Applications Claiming Priority (3)

    Application Number Priority Date Filing Date Title
    DE3915562A DE3915562C1 (en) 1989-05-12 1989-05-12
    DE3915562 1989-05-12
    PCT/EP1990/000466 WO1990013886A2 (en) 1989-05-12 1990-03-21 Monitor control circuit

    Related Child Applications (2)

    Application Number Title Priority Date Filing Date
    EP92107715A Division EP0500147B2 (en) 1989-05-12 1990-03-21 Method of and device for controlling a monitor
    EP92107715.2 Division-Into 1992-05-07

    Publications (3)

    Publication Number Publication Date
    EP0468973A1 EP0468973A1 (en) 1992-02-05
    EP0468973B1 EP0468973B1 (en) 1993-02-17
    EP0468973B2 true EP0468973B2 (en) 2001-05-09

    Family

    ID=6380538

    Family Applications (2)

    Application Number Title Priority Date Filing Date
    EP92107715A Expired - Lifetime EP0500147B2 (en) 1989-05-12 1990-03-21 Method of and device for controlling a monitor
    EP90904821A Expired - Lifetime EP0468973B2 (en) 1989-05-12 1990-03-21 Monitor control circuit

    Family Applications Before (1)

    Application Number Title Priority Date Filing Date
    EP92107715A Expired - Lifetime EP0500147B2 (en) 1989-05-12 1990-03-21 Method of and device for controlling a monitor

    Country Status (9)

    Country Link
    US (1) US5329290A (en)
    EP (2) EP0500147B2 (en)
    JP (1) JP2971132B2 (en)
    KR (1) KR960003396B1 (en)
    AT (2) ATE85858T1 (en)
    DE (3) DE3915562C1 (en)
    DK (2) DK0500147T4 (en)
    ES (2) ES2089283T5 (en)
    WO (1) WO1990013886A2 (en)

    Families Citing this family (10)

    * Cited by examiner, † Cited by third party
    Publication number Priority date Publication date Assignee Title
    JPH0573208A (en) * 1991-09-13 1993-03-26 Wacom Co Ltd Coordinate detector with display device of controller separation type
    US5815208A (en) * 1994-12-09 1998-09-29 Methode Electronics, Inc. VGA to NTSC converter and a method for converting VGA image to NTSC images
    DE19546841C2 (en) * 1995-12-15 2000-06-15 Sican Gmbh Multiple overlay with an overlay controller
    US5796391A (en) * 1996-10-24 1998-08-18 Motorola, Inc. Scaleable refresh display controller
    TW583639B (en) 2000-03-24 2004-04-11 Benq Corp Display device having automatic calibration function
    JP2003195803A (en) * 2001-12-27 2003-07-09 Nec Corp Plasma display
    US20040179016A1 (en) * 2003-03-11 2004-09-16 Chris Kiser DRAM controller with fast page mode optimization
    KR20110083409A (en) * 2010-01-14 2011-07-20 (주)엠씨테크놀로지 Timing controller, apparatus for controlling synchronization using timing controller
    ITCO20110001A1 (en) 2011-01-07 2012-07-08 Giacomini Spa "RADIANT PANEL IN PLASTERBOARD FOR FALSE CEILINGS AND COUNTERFLOWER MADE WITH THOSE RADIANT PANELS"
    JP6354866B1 (en) * 2017-01-06 2018-07-11 日立金属株式会社 Clad material for negative electrode current collector of secondary battery and method for producing the same

    Family Cites Families (9)

    * Cited by examiner, † Cited by third party
    Publication number Priority date Publication date Assignee Title
    GB1568378A (en) * 1976-01-30 1980-05-29 Micro Consultants Ltd Video processing system
    US4511965A (en) * 1983-03-21 1985-04-16 Zenith Electronics Corporation Video ram accessing system
    US4851834A (en) * 1984-01-19 1989-07-25 Digital Equipment Corp. Multiport memory and source arrangement for pixel information
    DE3425636A1 (en) * 1984-07-12 1986-01-16 Olympia Werke Ag, 2940 Wilhelmshaven Method for activating a raster recording device
    GB8613153D0 (en) * 1986-05-30 1986-07-02 Int Computers Ltd Data display apparatus
    US4796203A (en) * 1986-08-26 1989-01-03 Kabushiki Kaisha Toshiba High resolution monitor interface and related interfacing method
    FR2608291B1 (en) * 1986-12-15 1989-04-07 Locatel METHOD AND CIRCUIT FOR ADAPTING THE "GRAPHIC" CARD OF A COMPUTER TO A FUNCTIONAL MONITOR FOLLOWING A SCAN STANDARD DIFFERENT FROM THAT OF THE SAME CARD
    JPS63282790A (en) * 1987-02-14 1988-11-18 株式会社リコー Display controller
    JPS63255747A (en) * 1987-04-13 1988-10-24 Mitsubishi Electric Corp Picture memory device

    Also Published As

    Publication number Publication date
    JPH04507147A (en) 1992-12-10
    DE59010304D1 (en) 1996-05-30
    EP0468973B1 (en) 1993-02-17
    EP0468973A1 (en) 1992-02-05
    ATE137352T1 (en) 1996-05-15
    DE59000902D1 (en) 1993-03-25
    US5329290A (en) 1994-07-12
    ATE85858T1 (en) 1993-03-15
    DK0500147T3 (en) 1996-05-13
    ES2038054T3 (en) 1993-07-01
    ES2089283T3 (en) 1996-10-01
    KR960003396B1 (en) 1996-03-09
    DK0500147T4 (en) 2001-10-08
    JP2971132B2 (en) 1999-11-02
    ES2089283T5 (en) 2002-01-16
    EP0500147A3 (en) 1992-10-14
    EP0500147B1 (en) 1996-04-24
    ES2038054T5 (en) 2001-09-16
    DK0468973T4 (en) 2001-07-30
    EP0500147A2 (en) 1992-08-26
    DE3915562C1 (en) 1990-10-31
    KR920701936A (en) 1992-08-12
    WO1990013886A3 (en) 1990-12-27
    WO1990013886A2 (en) 1990-11-15
    EP0500147B2 (en) 2001-08-22
    DK0468973T3 (en) 1993-05-10

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