EP0500147B2 - Method of and device for controlling a monitor - Google Patents

Method of and device for controlling a monitor Download PDF

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Publication number
EP0500147B2
EP0500147B2 EP92107715A EP92107715A EP0500147B2 EP 0500147 B2 EP0500147 B2 EP 0500147B2 EP 92107715 A EP92107715 A EP 92107715A EP 92107715 A EP92107715 A EP 92107715A EP 0500147 B2 EP0500147 B2 EP 0500147B2
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EP
European Patent Office
Prior art keywords
storage device
signal
data words
video storage
image signal
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EP92107715A
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German (de)
French (fr)
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EP0500147B1 (en
EP0500147A2 (en
EP0500147A3 (en
Inventor
Stefan Schwarz
Ian Cartwright
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SPEA SOFTWARE GMBH
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SPEA Software GmbH
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/395—Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G1/00—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data
    • G09G1/06—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data using single beam tubes, e.g. three-dimensional or perspective representation, rotation or translation of display pattern, hidden lines, shadows
    • G09G1/14—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data using single beam tubes, e.g. three-dimensional or perspective representation, rotation or translation of display pattern, hidden lines, shadows the beam tracing a pattern independent of the information to be displayed, this latter determining the parts of the pattern rendered respectively visible and invisible
    • G09G1/16—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data using single beam tubes, e.g. three-dimensional or perspective representation, rotation or translation of display pattern, hidden lines, shadows the beam tracing a pattern independent of the information to be displayed, this latter determining the parts of the pattern rendered respectively visible and invisible the pattern of rectangular co-ordinates extending over the whole area of the screen, i.e. television type raster
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/393—Arrangements for updating the contents of the bit-mapped memory

Definitions

  • the present invention is concerned with a Method for driving a at a second pixel frequency working monitor, its display by reading out a digital image signal with a second pixel frequency from a video storage device can be generated based on all data words a digital pixel having a first pixel frequency Image signal.
  • the present invention is also concerned with a monitor control circuit which serves a monitor operating at a second pixel frequency to control, its display by reading a digital image signals with the second pixel frequency can be generated from a video storage device due to all data words a first pixel frequency digital image signal.
  • Computer monitors are known to become dependent of the requirements regarding the required Screen resolution due to different graphics cards Controlled categories that are among themselves through the horizontal and vertical resolution, so the number of pixels, in horizontal and vertical Distinguish direction as well as by the pixel frequencies.
  • Known graphics card standards are, for example MDA (320 x 200 pixels, black and white, at 16 MHz pixel frequency), CGA (320 x 200 pixels, color, at 20 MHz pixel frequency), HERCULES (740x400 pixels, Black and white, at 27 MHz pixel frequency), EGA (640 x 350 pixels, color, at 30 MHz pixel frequency), VGA (640 x 480 pixels, color, at 32 MHz Pixel frequency), SUPER-EGA (800 x 600 or 1024 x 768 pixels, color, at 50 MHz pixel frequency, as well recently the so-called HR (High Resolution) graphics systems with 1024 x 768, 1080 x 1024 and 1600 x 1280 pixels, color, at pixel frequencies between 60 MHz and 170 MHz.
  • HR High
  • DE-A1-38 04 460 already discloses a monitor control circuit for controlling one at a second pixel frequency working monitor a digital one having a first pixel frequency Image signal, with a serial-parallel converter on the input side in the form of a shift register, on the Output connected to a video storage device is, in which the input image signal after its Serial-parallel conversion can be filed. Since it is the memory is only a shift register for serial-parallel conversion acts for the purpose of Serial-parallel conversion with the clock of the subsystem after the occurrence of the blank signal of the subsystem is clocked, the input side Image signal with the frequency of its subsystem clock written in the video storage device.
  • the raster elements can be controlled in a predetermined sequence must, and which has an image memory between a processor and the recording device to arrange a FIFO memory. Once the FIFO store is empty, an interrupt command interrupts the im Processor running program, whereupon new data are written into the Fifo memory, whereby after filling the processor the interrupted Resume program run.
  • FR-A-2 608 291 is a circuit for adaptation a graphics card of a certain television standard known to a monitor of another television standard, one with a video processor Data processing by a periodically generated Fast pulse in relation to that for the conversion necessary to be omitted or inserted Image lines is interrupted. This does not make it possible complete update of the monitor image.
  • EP-A-261791 is not concerned with the illustration an image signal with a first pixel frequency on a monitor running at a second pixel frequency works, but with updating the content of a Refresh memory for a high resolution monitor due to an image signal source generated by a Main memory is formed.
  • Both the image signal source which can be read out under the control of a microprocessor is, like the rest of the entire monitor system work under the uniform timing of a single clock generator, so that the problem of Conversion of image signals of different pixel frequencies cannot occur here.
  • This well-known System to refresh the memory of one Only such data points of the Main memory, which contain new image information, pushed into a data fifo buffer.
  • a data pattern, which to refresh and not to refresh Refresh memory pixel is displayed in another Fifo register by the microprocessor brought in. Be in a normal mode of operation all image data for the monitor in sequence only from the refresh memory under the effect of a Read address generator and fed to the monitor. If a refresh is needed, be discontinuously only the image pixels to be refreshed pushed out of the data fifo buffer and on the one hand under control of the control fifo memory in the refresh memory and on the other hand to the so defined Pixels of the monitor passed.
  • the invention is therefore based on the object such a monitor driving method and such To create monitor control circuit by monitor operating at a second pixel frequency a digital one having a first pixel frequency Image signals can be controlled such that the ones to be displayed Image signals are error-free and complete are updated.
  • the invention is based on the finding that the control of the one working with the second pixel frequency Monitors with the first pixel frequency is neither synchronized nor usually in a fixed, there is an even number ratio, by means of the image signal the first pixel frequency is then possible if the data words of the digital image signal initially cached in a FIFO storage device before going into a video storage device stored in synchronization with the operation of the monitor at the second pixel frequency can be read out in a manner known per se, to generate the monitor display.
  • FIG. 1 The embodiment of a monitor control device shown in FIG. 1 according to the present invention, those in their entirety with the reference number 1 a register device 2, a first storage device designed as a FIFO storage device 3, a video storage device 4, a first control device 5, a second control device 6, an oscillator 7, a display counter device 8 and a serial readout control device 9.
  • the register device 2 is on the input side with a Input data bus 10 connected on the data words a digital image signal with the first pixel frequency available.
  • the input data bus 10 can extend to a VGA interface, for example.
  • the input data bus 10 comprises one connection each for the three basic colors R, G, B and a connection for a brightness bit I.
  • Each data word represents a pixel with 4 bit depth.
  • the register device 2 is also on the input side with a clock signal input 11 for a clock signal with the first pixel frequency.
  • the register device 2 receives from the first Control device 5 selection signals SEL0, SEL1, SEL2, SEL3 via a selection data bus 12, the four Bit.
  • the register device 2 is on the output side via a first data bus 13 with inputs of the Fifo storage device 3 in connection, which also a Reset input 14 has a vertical synchronization signal VS (1) of the first image signal can be fed is. Furthermore, the FIFO memory device 3 of the first control device 5 at its write input 15, a write command signal WF is supplied.
  • the first Control device 5 has a clock input 16 for the first clock signal CLK (1), a blank input 17 for the blank signal BL (1) of the first image signal.
  • the FIFO storage device is on the output side 3 via a second data bus 20 with the video storage device 4 in connection.
  • the display counter device 8 has a clock input 21 for the first clock signal CLK (1), a blank input 22 for the blank signal BL (1) of the first image signal, a vertical synchronization input 23 for the vertical synchronization signal VS (1) and a horizontal synchronization input 24 for the horizontal synchronization signal HS (1).
  • the display counter device is on the output side 8 by means of a third data bus 25 for a horizontal count HC with the second control device 6 as well as with the serial readout control device 9 in Connection.
  • the display counter device also stands 8 via a fourth data bus 26 for a vertical count VC with the serial readout controller in Connection.
  • the second control device 6 is on the output side with inputs of the video storage device via a Control bus 27 and an address bus 28 in connection.
  • the Control bus 27 each includes a line for a row address takeover signal RAS, a column address strobe CAS, a write command signal WB / WE and a data transfer signal DT / OE for taking over a Data line from the video storage device 4 in one Readout shift registers of the same (not shown).
  • the serial read-out control device 9 is on the output side via a second control bus 29 for control signals SC, SOE for reading out the video storage device 4 with control inputs of the latter in connection.
  • the video storage device 4 stands again via a fifth data bus 30 with a Data input from the serial readout control device 9 connected, which in turn has a vertical synchronization input 31 for the vertical synchronization signal VS (2) of the second monitor-side image signal, one Clock input 32 for a second clock signal CLK (2) with the second pixel frequency, a blank input 33 for the second blank signal BL (2) and a horizontal synchronization input 34 for the horizontal synchronization signal HS (2) of the second image signal on the monitor side having.
  • the serial readout control device is on the output side 9 via a sixth data bus 35 with the DAC digital-to-analog converter (not shown) Monitors in connection. Because the structure of the monitor what is required in the prior art is required not their explanation.
  • the register device 2 carries out a serial-parallel conversion of four consecutive data words, those with the pixel frequency on the input data bus 10 are present, through, the output generated Data words that have four times the number of bits, so Data words with a length of 16 bits are in parallel be given the first data bus 13.
  • This implementation of 4-bit data words in 16-bit data words under the control of the first control device 5 by means of the selection signals SEL0, ... SEL3, which after Completion of this implementation of the FIFO storage device 3 supplies a write command signal 15.
  • the FIFO storage device is 3 constructed in such a way that it is read in first Data words when triggered by the read command RF first into the video storage device via the second data bus 20 4 can be read.
  • Control device 6 for the correct storage of the digital image signals in the video storage device information about the number of pixels per line of the image signals present on the input side, which also required by the serial readout control device 9 which is additionally the number of lines of the image of the input image signal for the readout control needed.
  • the display counter device determines 8 in the preferred shown Embodiment by counting the clock signals CLK (1) a horizontal count between two blank signals BL (1) HG (0 ... 9) and by counting the number of Blank signals BL (1) between two vertical synchronization signals VS (1) the number of rows by the first image signal displayed image as a vertical count VC (0 .. .9).
  • the second control device works on a time basis, which is determined by the oscillator 7, wherein the beginning of a cycle by the occurrence of the vertical synchronization signal VS (1) at the reset input is set. That of the second control device also supplied second (output side) Blank signal BL (2) is used only to control the refresh the dynamic video storage device 4 and to control the shift register takeover, the the takeover of an entire line of memory from the video storage device 4 in the output shift register (not shown) allows and interrupts the cycle control for the control the FIFO storage device 3 and the video storage device 4.
  • the control of the video storage device starts addressing the first line and the first column of the video storage device 4 if the flag EF is not present, the address transfer by the row address takeover signal RAS and the column address acquisition signal CAS controlled , whereby during the write mode the Write command signal WB / WE is "low".
  • the takeover of the data words from the FIFO storage device 3 in the video storage device 4 takes place in the so-called "page-mode", where the line addressing and the row address takeover signal RAS during the Storage of data words in the different Columns of this row remain unchanged, which means in the writing speed is known the video memory is increased.
  • the exact sequence the individual control signals depends on the manufacturer's specification the video storage device 4 for the at "page mode" write mode provided for these devices. Details of the addressing are under With reference to FIGS. 9 and 10 explained in more detail.
  • Control of serial readout of the video storage device through the serial readout controller 9 takes place in synchronization with the monitor side present second horizontal synchronization signal HS (2), vertical synchronization signal VS (2), Clock signal CLK (2) and blank signal BL (2) in one known way.
  • the first blank signal BL (1) the first control device 5 in an initial state set to CLK when a first clock pulse occurs (1) (with circuit-related delay) reset a zero selection signal SEL0 and on to set the first selection signal SEL1, the second Clock pulse CLK (1) reset the first selection signal and the second selection signal SEL2 is set, etc., finally the third after the third pulse Selection signal SEL3 reset and the Fifo write signal WF is set, whereupon after the fourth Clock pulse reset the third selection signal and that Fifo write signal after the following first Clock is reset.
  • These staggered selection signals SEL0 to SEL3 are used to control the register device 2 used, its structure explained in more detail below with reference to FIG. 4 becomes.
  • the register device 2 comprises three 4-bit registers 36, 37, 38 and a 16-bit register 39, all of them with the clock signal input 11 and with the input data bus 10 communicating.
  • the outputs of the 4-bit registers 36 to 38 are with inputs of the 16-bit register 39 connected.
  • the registers 36 to 39 are in the order of their reference numbers from the selection signals SEL0 to SEL3 controlled so that control of the 16-bit register 39 by the fourth selection signal SEL3 four 4-bit data words on the input side converted into a 16-bit data word on the output side are.
  • 5 shows the temporal relation of the first horizontal synchronization signal HS (1), the first blank signal BL (1) and the first Clock signal CLK (1).
  • the display counter device includes 8 a horizontal counter 40, the clock input the first clock signal CLK (1) and its reset input the first horizontal synchronization signal HS (1) are supplied.
  • the first blank signal BL (1) controls the transfer of the counter reading from the horizontal counter 40 in the register 41 for the horizontal count HC, which appears on the output side of bus 25.
  • Fig. 7 shows (of course with one opposite Fig. 1 streamlined time base) the schematic temporal Relationship between the first blank signal BL (1), the first horizontal synchronization signal HS (1) and the first vertical synchronization signal VS (1).
  • the display counter device 8 shows the vertical counting or line counting relevant portion of the display counter device 8, which comprises a vertical counter 42, the clock input the first blank signal BL (1) and its reset input the first vertical synchronization signal VS (1) and the output side with a Register 43 for the vertical count VC connected is whose clock input is again through the first Vertical synchronization signal driven, and that on the output side with the fourth data bus 26 in connection stands on which the vertical count VC is present.
  • Fig. 9 shows the structure of the video storage device 4, in the example shown in four memory levels 44 to 47 is divided. This subdivision the video storage device enables a reduction the data flow rate when saving and a simplified addressing.
  • each of the memory levels 44 to 47 is 512 x 512 storage locations, each of the storage levels 44 to 47 divided in two at the horizontal address 256 is.
  • a storage organization results of 1024 x 1024 seats.
  • Horizontal address counter After reaching this Horizontal address is carried out by the (still to be described) Horizontal address counter jumps to the horizontal address 256, at which the storage level is divided is to continue from this horizontal address value to to a divided by the horizontal count HC count the number of storage levels increased value before after the second line of the first image signal, the third line of the first image signal then on the second line of the video storage device 44 to 47; 4 is filed. Incrementing the Row address counter occurs after every second reaching the divided by the number of storage levels Horizontal count HC.
  • a block diagram of the second control device is shown in Fig. 10 and includes a column address counter 48, a row address counter 49 and one Control signal generator for generating the control signals for the video storage device 4.
  • the column address counter 48 is through at its clock input 51 the fifolesis signal is clocked by the first RF Vertical synchronization signal VS (.1) at its reset input 52 reset and is also on the third Data bus 25 for receiving the horizontal count HC connected.
  • the control signal generator 50 becomes the clock signal CLK * from oscillator 7 at its clock input 54, the flag EF from the fifo storage device 3 thereon Flag input 55, the control signal TC from the column address counter 48 at its control signal input 56 and the secondary-side horizontal synchronization signal HS (2) at its horizontal synchronization input 57 fed.
  • the generation of the Row address takeover signal RAS, the column address takeover signal CAS, the data transfer signal DT / OE for the transfer of data from the Video storage device in its output shift register and the write signal WB / WE for the video storage device takes place according to the specification of the video storage device used for each Operation in "page-mode" write mode.
  • the Readout signal RF can be combined by ANDing the CAS address takeover signal and the second Horizontal synchronization signal HS (2) by means of a Gates 58 are generated.
  • a register device used to the input side data words at the first pixel frequency in data words of multiple bit length at one to generate by the plurality of divided first pixel frequencies thereby reducing the speed of injection into the FIFO storage device can be lowered.
  • the input register device however becomes dispensable when the first Image signal a corresponding low data word rate has or if a Fifo storage device with correspondingly high working speed used becomes.
  • the storage into the video storage device each starting from a horizontal address 0 and one Vertical address 0, i.e. starting from the top left Corner of the video storage device made.
  • the subject matter of the invention is not limited to a certain number of bits of the data words of the processed Image signal and is also based on black and white image signals how to use color image signals. If, for example, a color variety of 256 colors What is desired is what corresponds to 8-bit input data words two circuits in accordance with FIG be switched.

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Abstract

A monitor control circuit serves to control a monitor whose display can be generated by reading out a digital video signal with a second pixel frequency from a video storage device, on the basis of a digital video signal having a first pixel frequency. For gap-free conversion of the first video signal to the second video signal, or for combining video signals of different graphics standards, the digital video signal of the first pixel frequency is read into a FIFO storage device (3) with a frequency dependent on the first pixel frequency and the data words of the digital video signal which are to be stored in the video storage device (4) are read out from the FIFO storage device (3) only during time segments in which no data are read out from the video storage device (4), whereby the number of data words which can be read out from the FIFO storage device (3) for storage in the video storage device (4) may vary. <IMAGE>

Description

Die vorliegende Erfindung befaßt sich mit einem Verfahren zur Ansteuerung eines bei einer zweiten Pixelfrequenz arbeitenden Monitors, dessen Anzeige durch Auslesen eines digitalen Bildsignales mit einer zweiten Pixelfrequenz aus einer Videospeichervorrichtung erzeugbar ist, aufgrund sämtlicher Datenworte eines eine erste Pixelfrequenz aufweisenden digitalen Bildsignales. Ferner befaßt sich die vorliegende Erfindung mit einer Monitorsteuerschaltung, die dazu dient, einen bei einer zweiten Pixelfrequenz arbeitenden Monitor anzusteuern, dessen Anzeige durch Auslesen eines digitalen Bildsignales mit der zweiten Pixelfrequenz aus einer Videospeichervorrichtung erzeugbar ist, aufgrund sämtlicher Datenworte eines eine erste Pixelfrequenz aufweisenden digitalen Bildsignales.The present invention is concerned with a Method for driving a at a second pixel frequency working monitor, its display by reading out a digital image signal with a second pixel frequency from a video storage device can be generated based on all data words a digital pixel having a first pixel frequency Image signal. The present invention is also concerned with a monitor control circuit which serves a monitor operating at a second pixel frequency to control, its display by reading a digital image signals with the second pixel frequency can be generated from a video storage device due to all data words a first pixel frequency digital image signal.

Computermonitore werden bekannterweise in Abhängigkeit von den Anforderungen bezüglich der geforderten Bildschirmauflösung durch Graphikkarten unterschiedlicher Kategorien angesteuert, die sich untereinander durch die horizontale und vertikale Auflösung, also die Anzahl der Pixel, in horizontaler und vertikaler Richtung sowie durch die Pixelfrequenzen unterscheiden. Bekannte Graphikkarten-Standards sind beispielsweise MDA (320 x 200 Bildpunkte, Schwarzweiß, bei 16 MHz Pixelfrequenz), CGA (320 x 200 Bildpunkte, Farbe, bei 20 MHz Pixelfrequenz), HERCULES (740x400 Bildpunkte, Schwarzweiß, bei 27 MHz Pixelfrequenz), EGA (640 x 350 Bildpunkte, Farbe, bei 30 MHz Pixelfrequenz), VGA (640 x 480 Bildpunkte, Farbe, bei 32 MHz Pixelfrequenz), SUPER-EGA (800 x 600 bzw. 1024 x 768 Bildpunkte, Farbe, bei 50 MHz Pixelfrequenz, sowie neuerdings die sogenannten HR (High Resolution)-Graphiksysteme mit 1024 x 768, 1080 x 1024 sowie 1600 x 1280 Bildpunkten, Farbe, bei Pixelfrequenzen zwischen 60 MHz und 170 MHz. Für den Fachmann ist es offensichtlich, daß sich diese verschiedenen Graphik-Standards auch bezüglich der Zeilenfrequenzen, also dem Kehrwert der Horizontalsynchronisationssignalperioden, unterscheiden, die für die genannten Systeme bei 17 kHz, 22 kHz, 25 kHz, 31,5 kHz, 50 kHz sowie 64 bis 84 kHz liegen.Computer monitors are known to become dependent of the requirements regarding the required Screen resolution due to different graphics cards Controlled categories that are among themselves through the horizontal and vertical resolution, so the number of pixels, in horizontal and vertical Distinguish direction as well as by the pixel frequencies. Known graphics card standards are, for example MDA (320 x 200 pixels, black and white, at 16 MHz pixel frequency), CGA (320 x 200 pixels, color, at 20 MHz pixel frequency), HERCULES (740x400 pixels, Black and white, at 27 MHz pixel frequency), EGA (640 x 350 pixels, color, at 30 MHz pixel frequency), VGA (640 x 480 pixels, color, at 32 MHz Pixel frequency), SUPER-EGA (800 x 600 or 1024 x 768 pixels, color, at 50 MHz pixel frequency, as well recently the so-called HR (High Resolution) graphics systems with 1024 x 768, 1080 x 1024 and 1600 x 1280 pixels, color, at pixel frequencies between 60 MHz and 170 MHz. For the professional it is obvious that these different graphics standards also with regard to the line frequencies, so the reciprocal of the horizontal synchronization signal periods, distinguish that for the systems mentioned at 17 kHz, 22 kHz, 25 kHz, 31.5 kHz, 50 kHz and 64 to 84 kHz.

Es besteht seit längerer Zeit der Wunsch, die Ausgangssignale der verschiedenen Graphik-Standards mittels eines einzigen Monitores zu Bildschirmbildern umwandeln zu können. Zu diesem Zweck bedient man sich derzeit sogenannter "Multisync"-Monitore, die in der Lage sind, mittels umschaltbarer Schwingkreise mit verschiedenen Horizontalsynchronisationssignalfrequenzen zu arbeiten. Da die Umschaltung des "Multisync"-Monitores von einer Graphiknorm auf die nächste und somit von einer Arbeitsfrequenz auf die nächste mit einer gewissen Einschwingzeit verbunden ist, führt die Umschaltung der Bildschirmdarstellung von einer Graphiknorm auf eine nächste zu zeitlichen Unterbrechungen der Bildschirmanzeige oder anfänglichen Bildstörungen. Selbstredend steigt die Komplexität eines "Multisync"-Monitores mit zunehmender Anzahl der durch diesen bewältigbaren Graphikkarten-Standards an. Eine Anzeige zweier Teilbilder, die von zwei verschiedenen Graphikkarten kreiert werden, auf einem gemeinsamen Bildschirm ist bei den bekannten "Multisync"-Monitoren gleichfalls nicht möglich.There has been a desire for a long time, the output signals of the various graphic standards from a single monitor to screen images to be able to. For this purpose you use yourself currently so-called "multisync" monitors that are capable are, by means of switchable resonant circuits with different Horizontal sync signal frequencies to work. Since the switchover of the "Multisync" monitor from one graphic standard to the next and thus from one Working frequency to the next with a certain Settling time is connected, the switchover of the Screen display from a graphics standard to a next to time interruptions of the screen display or initial image interference. Of course the complexity of a "multisync" monitor increases with increasing Number of graphics card standards manageable by this on. A display of two drawing files, which are created from two different graphics cards, on a common screen is the well-known "Multisync" monitors also not possible.

Die DE-A1-38 04 460 offenbart bereits eine Monitorsteuerschaltung für Ansteuerung eines bei einer zweiten Pixelfrequenz arbeitenden Monitores aufgrund eines eine erste Pixelfrequenz aufweisenden digitalen Bildsignales, mit einem eingangsseitigen Seriell-Parallel-Wandler in Form eines Schieberegisters, an dessen Ausgang eine Videospeichervorrichtung angeschlossen ist, in die das eingangsseitige Bildsignal nach seiner Seriell-Parallel-Wandlung ablegbar ist. Da es sich bei dem Speicher lediglich um ein Schieberegister zur Seriell-Parallel-Wandlung handelt, das zum Zwecke der Seriell-Parallel-Wandlung mit dem Takt des Subsystems nach dem jeweiligen Auftreten des Blanksignales des Subsystemes getaktet wird, wird das eingangsseitige Bildsignal mit der Frequenz seines Subsystemtaktes in die Videospeichervorrichtung eingeschrieben. Wegen der fehlenden Synchronität des Einschreibens des Bildsignales in die Videospeichervorrichung mit dem ersten Subsystemtakt und des Auslesens aus dem Videospeicher mit dem Hauptsystemtakt können Überschneidungen des Einschreibens und des Auslesens auftreten. Diese Überschneidungen werden nach dem Stand der Technik dadurch ausgeräumt, daß einige Bildelemente eines jeden Teilbildes nicht aktualisiert werden, indem dem Transferzyklus und somit dem Auslesen des Videospeichers ein Vorrang gegenüber dem Auffrischen eingeräumt wird. Die Folge dieser Art der Steuerung ist ein teilweise nicht aktueller Bildinhalt der jeweiligen Teilbilder.DE-A1-38 04 460 already discloses a monitor control circuit for controlling one at a second pixel frequency working monitor a digital one having a first pixel frequency Image signal, with a serial-parallel converter on the input side in the form of a shift register, on the Output connected to a video storage device is, in which the input image signal after its Serial-parallel conversion can be filed. Since it is the memory is only a shift register for serial-parallel conversion acts for the purpose of Serial-parallel conversion with the clock of the subsystem after the occurrence of the blank signal of the subsystem is clocked, the input side Image signal with the frequency of its subsystem clock written in the video storage device. Because of the lack of synchronicity of the registered mail of the image signal in the video storage device the first subsystem clock and reading from the Video memory with the main system clock can overlap of registration and reading occur. These overlaps are made after State of the art eliminated in that some Picture elements of each drawing file are not updated by the transfer cycle and thus the reading of video memory takes precedence over that Refresh is granted. The consequence of this kind of Control is a partially not current image content of the respective drawing files.

Aus der DE-A1-34 25 636 ist es bekannt, bei einer Raster-Aufzeichnungseinrichtung, deren Rasterelemente in einer vorbestimmten Folge angesteuert werden müssen, und die einen Bildspeicher aufweist, zwischen einem Prozessor und der Aufzeichnungseinrichtung einen Fifo-Speicher anzuordnen. Sobald der Fifo-Speicher leer ist, unterbricht ein Interrupt-Befehl das im Prozessor laufende Programm, woraufhin neue Daten in den Fifo-Speicher eingeschrieben werden, wobei nach dessen Füllen der Prozessor den unterbrochenen Programmlauf wieder aufnimmt.From DE-A1-34 25 636 it is known for one Raster recording device, the raster elements can be controlled in a predetermined sequence must, and which has an image memory between a processor and the recording device to arrange a FIFO memory. Once the FIFO store is empty, an interrupt command interrupts the im Processor running program, whereupon new data are written into the Fifo memory, whereby after filling the processor the interrupted Resume program run.

Aus dem Fachbuch Jan Hendrik Jansen, Anwendungen digitaler Bauelemente, Franzis-Verlag, ISBN 3-7723-7931-1, 1985, ist es bekannt, daß Fifo-Speicher Register sind, die in der digitalen Elektronik zum Speichern von Zwischenergebnissen dienen und die zur Koppelung von nach unterschiedlichen Zeitschemata arbeitenden Medien eingesetzt werden können. Mit Monitorsteuerschaltungen befaßt sich diese Fachveröffentlichung nicht.From the specialist book Jan Hendrik Jansen, applications digital components, Franzis-Verlag, ISBN 3-7723-7931-1, 1985, it is known that FIFO memory Registers are used in digital electronics for storage of interim results and serve to Coupling according to different time schedules working media can be used. With monitor control circuits deals with this specialist publication Not.

Aus der FR-A-2 608 291 ist eine Schaltung zur Anpassung einer Graphikkarte einer bestimmten Fernsehnorm an einen Monitor einer anderen Fernsehnorm bekannt, bei der eine durch einen Videoprozessor erfolgende Datenverarbeitung durch einen periodisch erzeugten Auffastimpuls in Relation zu den für die Konvertierung nötigen auszulassenden oder einzufügenden Bildzeilen unterbrochen wird. Dies ermöglicht keine vollständige Aktualisierung des Monitorbildes.From FR-A-2 608 291 is a circuit for adaptation a graphics card of a certain television standard known to a monitor of another television standard, one with a video processor Data processing by a periodically generated Fast pulse in relation to that for the conversion necessary to be omitted or inserted Image lines is interrupted. This does not make it possible complete update of the monitor image.

Aus der Fachveröffentlichung IBM-TDB, Band 28, Nr. 6, November 1985, Seiten 2615 bis 2620 ist ein weiteres Verfahren zur Umwandlung eines von einer Graphikkarte stammenden digitalen Videosignales in ein Bildsignal eines anderen Graphikstandards bekannt, bei dem jedoch gleichfalls nur eine unvollständige Aktualisierung der Bildinhalte erreicht wird, so daß es insbesondere bei schnell bewegten Szenen zu merkbaren Bildverfälschungen kommt. Bei diesem System wird das Schieberegister als vollständige Zeile durch einen Mikroprozessor ausgelesen, der erst die vollständige Zeile in einen Bildpuffer ablegen muß, bevor nach Erhöhung eines Zeilenzählers eine weitere vollständige Zeile des eingangsseitigen Bildsignales aufgenommen werden kann. Anstelle des Schieberegisters zum Speichern der Datenworte von jeweils einer Zeile des eingangsseitigen Bildsignales kann ebenfalls ein Fifo-Speicher verwendet werden, der jedoch auch zur Aufnahme von jeweils einer vollständigen Bildzeile angesteuert wird. Wegen der fehlenden Aktualisierung kommt es nur bei langsam bewegten Bildern zu einem befriedigenden Bild, während schnell bewegte Bilder mangels Aktualisierung nicht zufriedenstellend wiedergegeben werden.From the specialist publication IBM-TDB, Volume 28, No. 6, November 1985, pages 2615 to 2620 is another Process for converting one from a graphics card derived digital video signals in one Image signal of another graphics standard known but also only an incomplete update the image content is achieved so that it is particular noticeable in fast moving scenes Image falsification is coming. With this system the shift register as a complete line by one Microprocessor read out, only the complete one Line must be placed in a frame buffer before after increasing of a line counter another complete Line of the input image signal recorded can be. Instead of the shift register for saving of data words from one line of the input side Fifo memory can also store image signals be used, but also for recording controlled by one complete image line each becomes. Because of the missing update only with slow moving images satisfactory picture while fast moving pictures not reproduced satisfactorily due to lack of update become.

Die EP-A-261791 befaßt sich nicht mit der Darstellung eines Bildsignales mit einer ersten Pixelfrequenz auf einem Monitor, der mit einer zweiten Pixelfrequenz arbeitet, sondern mit der Aktualisierung des Inhaltes eines Auffrischspeichers für einen Monitor mit hoher Auflösung aufgrund einer Bildsignalquelle, die durch einen Hauptspeicher gebildet ist. Sowohl die Bildsignalquelle, welche unter der Steuerung eines Mikroprozessors auslesbar ist, wie auch der Rest des gesamten Monitorsystemes arbeiten unter der einheitlichen Zeitgabe eines einzigen Taktgenerators, so daß die Problematik der Umwandlung von Bildsignalen unterschiedlicher Pixelfrequenzen hier nicht auftreten kann. Bei diesem bekannten System zur Auffrischung des Speichers eines Monitors werden lediglich solche Datenpunkte des Hauptspeichers, die eine neue Bildinformation enthalten, in einen Daten-Fifo-Puffer geschoben. Ein Datenmuster, welches aufzufrischende und nicht aufzufrischende Pixel des Auffrischspeichers anzeigt, wird in einem weiteren Fifo-Register durch den Mikroprozessor eingebracht. In einer normalen Betriebsweise werden sämtliche Bilddaten für den Monitor der Reihe nach lediglich aus dem Auffrischspeicher unter der Wirkung eines Adressgenerators ausgelesen und dem Monitor zugeführt. Falls ein Auffrischen erforderlich ist, werden diskontinierlich lediglich die aufzufrischenden Bildpixel aus dem Daten-Fifo-Puffer herausgeschoben und einerseits unter Steuerung des Steuer-Fifo-Speichers in den Auffrischspeicher und andererseits an die so festgelegten Pixel des Monitors weitergegeben.EP-A-261791 is not concerned with the illustration an image signal with a first pixel frequency on a monitor running at a second pixel frequency works, but with updating the content of a Refresh memory for a high resolution monitor due to an image signal source generated by a Main memory is formed. Both the image signal source, which can be read out under the control of a microprocessor is, like the rest of the entire monitor system work under the uniform timing of a single clock generator, so that the problem of Conversion of image signals of different pixel frequencies cannot occur here. In this well-known System to refresh the memory of one Only such data points of the Main memory, which contain new image information, pushed into a data fifo buffer. A data pattern, which to refresh and not to refresh Refresh memory pixel is displayed in another Fifo register by the microprocessor brought in. Be in a normal mode of operation all image data for the monitor in sequence only from the refresh memory under the effect of a Read address generator and fed to the monitor. If a refresh is needed, be discontinuously only the image pixels to be refreshed pushed out of the data fifo buffer and on the one hand under control of the control fifo memory in the refresh memory and on the other hand to the so defined Pixels of the monitor passed.

Daher liegt der Erfindung die Aufgabe zugrunde, ein derartiges Monitoransteuerverfahren und eine derartige Monitorsteuerschaltung zu schaffen, durch die bei einer zweiten Pixelfrequenz arbeitender Monitor mittels eines eine erste Pixelfrequenz aufweisenden digitalen Bildsignales derart ansteuerbar ist, daß die anzuzeigenden Bildsignale jeweils fehlerfrei und vollständig aktualisiert sind.The invention is therefore based on the object such a monitor driving method and such To create monitor control circuit by monitor operating at a second pixel frequency a digital one having a first pixel frequency Image signals can be controlled such that the ones to be displayed Image signals are error-free and complete are updated.

Diese Aufgabe wird durch ein Verfahren gemäß Patentanspruch 1 und durch eine Monitorsteuerschattung gemäß Patentanspruch 5 gelöst.This object is achieved by a method according to claim 1 and by a monitor control shade solved according to claim 5.

Der Erfindung liegt die Erkenntnis zugrunde, daß die Ansteuerung des mit der zweiten Pixelfrequenz arbeitenden Monitores, die mit der ersten Pixelfrequenz weder synchronisiert ist noch üblicherweise in einem festen, geraden Zahlenverhältnis steht, mittels des Bildsignales der ersten Pixelfrequenz dann möglich ist, wenn die Datenworte des digitalen Bildsignales zunächst in einer Fifo-Speichervorrichtung zwischengespeichert werden, bevor sie in eine Videospeichervorrichtung abgelegt werden, die in Synchronisation mit dem Betrieb des Monitores bei der zweiten Pixelfrequenz in einer an sich bekannten Weise auslesbar ist, um die Monitoranzeige zu erzeugen. Wie noch näher erläutert wird, bewirkt die Übertragung der Datenworte von der Fifo-Speichervorrichtung in die Videospeichervorrichtung eine Steuervorrichtung, die mit der Videospeichervorrichtung und der Fifo-Speichervorrichtung verbunden ist und diese in der Weise ansteuert, daß Datenworte aus der Fifo-Speichervorrichtung in die Videospeichervorrichtung einschreibbar ist.The invention is based on the finding that the control of the one working with the second pixel frequency Monitors with the first pixel frequency is neither synchronized nor usually in a fixed, there is an even number ratio, by means of the image signal the first pixel frequency is then possible if the data words of the digital image signal initially cached in a FIFO storage device before going into a video storage device stored in synchronization with the operation of the monitor at the second pixel frequency can be read out in a manner known per se, to generate the monitor display. How closer is explained, causes the transmission of the data words from the FIFO storage device to the video storage device a control device associated with the video storage device and the Fifo storage device is connected and this controls in such a way that data words from the FIFO storage device into the video storage device is enrollable.

Bevorzugte Weiterbildungen sind in den Unteransprüchen angegeben.Preferred further developments are in the subclaims specified.

Nachfolgend wird unter Bezugnahme auf die beiliegenden Zeichnungen eine bevorzugte Ausführungsform der erfindungsgemäßen Monitorsteuerschaltung näher erläutert. Es zeigen:

Fig. 1
ein Blockdiagramm einer Ausführungsform der erfindungsgemäßen Monitorsteuerschaltung;
Fig. 2
eine zeitliche Darstellung von Signalverläufen zur Erläuterung der Funktionsweise einer ersten Steuervorrichtung gemäß Fig. 1;
Fig. 3
eine Blockdarstellung der in Fig. 1 gezeigten ersten Steuervorrichtung;
Fig. 4
ein Blockdiagramm einer in Fig. 1 gezeigten Registervorrichtung;
Fig. 5
eine zeitliche Darstellung von Signalverläufen zur Erläuterung der Funktionsweise einer in Fig. 1 gezeigten Anzeigezählervorrichtung;
Fig. 6
ein Blockdiagramm eines Details der Anzeigezählervorrichtung gemäß Fig. 1;
Fig. 7
eine zeitliche Darstellung von Signalverläufen zur Erläuterung der Funktion eines weiteren Teiles der in Fig. 1 gezeigten Anzeigezählervorrichtung;
Fig. 8
ein Blockdiagramm eines weiteren Teiles der in Fig. 1 gezeigten Anzeigezählervorrichtung;
Fig. 9
eine schematische Darstellung der Speicherorganisation einer in Fig. 1 gezeigten Videospeichervorrichtung; und
Fig. 10
Blockdiagramme der Struktur einer in Fig. 1 gezeigten zweiten Steuervorrichtung.
A preferred embodiment of the monitor control circuit according to the invention is explained in more detail below with reference to the accompanying drawings. Show it:
Fig. 1
a block diagram of an embodiment of the monitor control circuit according to the invention;
Fig. 2
a temporal representation of waveforms to explain the operation of a first control device according to FIG. 1;
Fig. 3
a block diagram of the first control device shown in Fig. 1;
Fig. 4
1 is a block diagram of a register device shown in FIG. 1;
Fig. 5
a temporal representation of waveforms to explain the operation of a display counter device shown in Fig. 1;
Fig. 6
1 is a block diagram of a detail of the display counter device of FIG. 1;
Fig. 7
a temporal representation of waveforms to explain the function of another part of the display counter device shown in Fig. 1;
Fig. 8
1 is a block diagram of another part of the display counter device shown in FIG. 1;
Fig. 9
is a schematic representation of the memory organization of a video memory device shown in Fig. 1; and
Fig. 10
Block diagrams of the structure of a second control device shown in FIG. 1.

Die in Fig. 1 gezeigte Ausführungsform einer Monitorsteuervorrichtung gemäß der vorliegenden Erfindung, die in ihrer Gesamtheit mit dem Bezugszeichen 1 bezeichnet ist, umfaßt eine Registervorrichtung 2, eine als Fifo-Speichervorrichtung ausgebildete erste Speichervorrichtung 3, eine Videospeichervorrichtung 4, eine erste Steuervorrichtung 5, eine zweite Steuervorrichtung 6, einen Oszillator 7, eine Anzeigezählervorrichtung 8 und eine serielle Auslesesteuervorrichtung 9.The embodiment of a monitor control device shown in FIG. 1 according to the present invention, those in their entirety with the reference number 1 a register device 2, a first storage device designed as a FIFO storage device 3, a video storage device 4, a first control device 5, a second control device 6, an oscillator 7, a display counter device 8 and a serial readout control device 9.

Die Registervorrichtung 2 ist eingangsseitig mit einem Eingangsdatenbus 10 verbunden, auf dem Datenworte eines digitalen Bildsignales mit der ersten Pixelfrequenz vorliegen. Der Eingangsdatenbus 10 kann sich beispielsweise zu einer VGA-Schnittstelle erstrekken. Der Eingangsdatenbus 10 umfaßt im Beispielsfall je einen Anschluß für die drei Grundfarben R, G, B und einen Anschluß für ein Helligkeitsbit I. Jedes Datenwort stellt ein Pixel mit 4 bit Tiefe dar. Die Registervorrichtung 2 ist femer eingangsseitig mit einem Taktsignaleingang 11 für ein Taktsignal mit der ersten Pixelfrequenz versehen. Die Registervorrichtung 2 empfängt von der ersten Steuervorrichtung 5 Auswahlsignale SEL0, SEL1, SEL2, SEL3 über einen Auswahldatenbus 12, der vier Bit hat. Ausgangsseitig steht die Registervorrichtung 2 über einen ersten Datenbus 13 mit Eingängen der Fifo-Speichervorrichtung 3 in Verbindung, welche ferner einen Rücksetzeingang 14 hat, dem ein Vertikalsynchronisationssignal VS(1) des ersten Bildsignales zuführbar ist. Ferner werden der Fifo-Speichervorrichtung 3 von der ersten Steuervorrichtung 5 an ihrem Schreibeingang 15 ein Schreibbefehlssignal WF zugeführt. Die erste Steuervorrichtung 5 hat einen Takteingang 16 für das erste Taktsignal CLK(1), einen Blankeingang 17 für das Blanksignal BL(1) des ersten Bildsignales.The register device 2 is on the input side with a Input data bus 10 connected on the data words a digital image signal with the first pixel frequency available. The input data bus 10 can extend to a VGA interface, for example. In the example, the input data bus 10 comprises one connection each for the three basic colors R, G, B and a connection for a brightness bit I. Each data word represents a pixel with 4 bit depth. The register device 2 is also on the input side with a clock signal input 11 for a clock signal with the first pixel frequency. The register device 2 receives from the first Control device 5 selection signals SEL0, SEL1, SEL2, SEL3 via a selection data bus 12, the four Bit. The register device 2 is on the output side via a first data bus 13 with inputs of the Fifo storage device 3 in connection, which also a Reset input 14 has a vertical synchronization signal VS (1) of the first image signal can be fed is. Furthermore, the FIFO memory device 3 of the first control device 5 at its write input 15, a write command signal WF is supplied. The first Control device 5 has a clock input 16 for the first clock signal CLK (1), a blank input 17 for the blank signal BL (1) of the first image signal.

Ausgangsseitig steht die Fifo-Speichervorrichtung 3 über einen zweiten Datenbus 20 mit der Videospeichervorrichtung 4 in Verbindung.The FIFO storage device is on the output side 3 via a second data bus 20 with the video storage device 4 in connection.

Die Anzeigezählervorrichtung 8 hat einen Takteingang 21 für das erste Taktsignal CLK(1), einen Blankeingang 22 für das Blanksignal BL(1) des ersten Bildsignales, einen Vertikalsynchronisationseingang 23 für das Vertikalsynchronisationssignal VS(1) und einen Horizontalsynchronisationseingang 24 für das Horizontalsynchronisationssignal HS(1).The display counter device 8 has a clock input 21 for the first clock signal CLK (1), a blank input 22 for the blank signal BL (1) of the first image signal, a vertical synchronization input 23 for the vertical synchronization signal VS (1) and a horizontal synchronization input 24 for the horizontal synchronization signal HS (1).

Ausgangsseitig steht die Anzeigezählervorrichtung 8 mittels eines dritten Datenbusses 25 für einen Horizontalzählwert HC mit der zweiten Steuervorrichtung 6 sowie mit der seriellen Auslesesteuervorrichtung 9 in Verbindung. Ferner steht die Anzeigezählervorrichtung 8 über einen vierten Datenbus 26 für einen Vertikalzählwert VC mit der seriellen Auslesesteuervorrichtung in Verbindung.The display counter device is on the output side 8 by means of a third data bus 25 for a horizontal count HC with the second control device 6 as well as with the serial readout control device 9 in Connection. The display counter device also stands 8 via a fourth data bus 26 for a vertical count VC with the serial readout controller in Connection.

Ausgangsseitig steht die zweite Steuervorrichtung 6 mit Eingängen der Videospeichervorrichtung über einen Steuerbus 27 und einen Adreßbus 28 in Verbindung. Der Steuerbus 27 umfaßt je eine Leitung für ein Reihenadreßübernahmesignal RAS, ein Spaltenadreßübernahmesignal CAS, ein Schreibbefehlssignal WB/WE und ein Datenübertragungssignal DT/OE für die Übernahme einer Datenzeile aus der Videospeichervorrichtung 4 in ein (nicht gezeigtes) Ausleseschieberegister derselben.The second control device 6 is on the output side with inputs of the video storage device via a Control bus 27 and an address bus 28 in connection. The Control bus 27 each includes a line for a row address takeover signal RAS, a column address strobe CAS, a write command signal WB / WE and a data transfer signal DT / OE for taking over a Data line from the video storage device 4 in one Readout shift registers of the same (not shown).

Die serielle Auslesesteuervorrichtung 9 steht ausgangsseitig über einen zweiten Steuerbus 29 für Steuersignale SC, SOE für das Auslesen der Videospeichervorrichtung 4 mit Steuereingängen der letztgenannten in Verbindung. Die Videospeichervorrichtung 4 steht wiederum über einen fünften Datenbus 30 mit einem Dateneingang der seriellen Auslesesteuervorrichtung 9 in Verbindung, die ihrerseits einen Vertikalsynchronisationseingang 31 für das Vertikalsynchronisationssignal VS(2) des zweiten, monitorseitigen Bildsignales, einen Takteingang 32 für ein zweites Taktsignal CLK(2) mit der zweiten Pixelfrequenz, einen Blankeingang 33 für das zweite Blanksignal BL(2) sowie einen Horizontalsynchronisationseingang 34 für das Horizontalsynchronisationssignal HS(2) des zweiten, monitorseitigen Bildsignales aufweist.The serial read-out control device 9 is on the output side via a second control bus 29 for control signals SC, SOE for reading out the video storage device 4 with control inputs of the latter in connection. The video storage device 4 stands again via a fifth data bus 30 with a Data input from the serial readout control device 9 connected, which in turn has a vertical synchronization input 31 for the vertical synchronization signal VS (2) of the second monitor-side image signal, one Clock input 32 for a second clock signal CLK (2) with the second pixel frequency, a blank input 33 for the second blank signal BL (2) and a horizontal synchronization input 34 for the horizontal synchronization signal HS (2) of the second image signal on the monitor side having.

Ausgangsseitig steht die serielle Auslesesteuervorrichtung 9 über einen sechsten Datenbus 35 mit dem Digital-Analog-Wandler DAC des (nicht dargestellten) Monitors in Verbindung. Da die Struktur des Monitors der im Stand der Technik üblichen entspricht, bedarf es nicht deren Erläuterung.The serial readout control device is on the output side 9 via a sixth data bus 35 with the DAC digital-to-analog converter (not shown) Monitors in connection. Because the structure of the monitor what is required in the prior art is required not their explanation.

Nachfolgend wird die Funktionsweise der bevorzugten Ausführungsform gemäß Fig. 1 erläutert, wobei jedoch bezüglich schaltungsmäßigen und funktionellen Details auf die nachfolgende Erläuterung zu den Fig. 2 bis 10 verwiesen wird.Below is the way the preferred works Embodiment according to FIG. 1 explained, wherein however in terms of circuitry and functionality Details on the following explanation of FIG. 2 until 10 is referred.

Die Registervorrichtung 2 führt eine Seriell-Parallel-Umsetzung von jeweils vier aufeinanderfolgenden Datenworten, die mit der Pixelfrequenz am Eingangsdatenbus 10 anliegen, durch, wobei die ausgangsseitig erzeugten Datenworte die vierfache Bitzahl haben, also Datenworte einer Länge von 16 Bit sind, die parallel auf den ersten Datenbus 13 gegeben werden. Diese Umsetzung von 4-bit-Datenworten in 16-bit-Datenworte erfolgt unter der Steuerung der ersten Steuervorrichtung 5 mittels der Auswahlsignale SEL0, ... SEL3, die nach Abschluß dieser Umsetzung der Fifo-Speichervorrichtung 3 ein Schreibbefehlssignal 15 zuführt. Sobald mindestens ein Datenwort in der Fifo-Speichervorrichtung 3 abgespeichert ist, erlischt das von dieser der zweiten Steuervorrichtung 6 zugeführte Flag EF über den leeren Speicherzustand der Fifo-Speichervorrichtung, wodurch die zweite Steuervorrichtung darüber informiert wird, daß in der Fifo-Speichervorrichtung 3 in die Videospeichervorrichtung 4 umspeicherbare Datenworte vorliegen. Wie der Name sagt, ist die Fifo-Speichervorrichtung 3 derart aufgebaut, daß in diese zuerst eingelesene Datenworte bei Ansteuerung durch den Lesebefehl RF zuerst über den zweiten Datenbus 20 in die Videospeichervorrichtung 4 eingelesen werden. Wie nachfolgend noch näher erläutert wird, bewirkt die zweite Steuervorrichtung pro Schreibzyklus der Videospeichervorrichtung 4 bzw. Lesezyklus der Fifo-Speichervorrichtung 3 eine Umspeicherung einer Mehrzahl von Datenworten aus der ersten Speichervorrichtung 3 in die Videospeichervorrichtung 4, wobei die jeweils umgespeicherte Datenwortzahl, wie noch erläutert wird, von Fall zu Fall variieren kann.The register device 2 carries out a serial-parallel conversion of four consecutive data words, those with the pixel frequency on the input data bus 10 are present, through, the output generated Data words that have four times the number of bits, so Data words with a length of 16 bits are in parallel be given the first data bus 13. This implementation of 4-bit data words in 16-bit data words under the control of the first control device 5 by means of the selection signals SEL0, ... SEL3, which after Completion of this implementation of the FIFO storage device 3 supplies a write command signal 15. As soon as at least a data word in the FIFO storage device 3 is saved, that of the second goes out Control device 6 supplied flag EF over the empty Fifo memory device memory state, whereby the second control device informs about it that in the Fifo storage device 3 into the video storage device There are 4 rewritable data words. As the name suggests, the FIFO storage device is 3 constructed in such a way that it is read in first Data words when triggered by the read command RF first into the video storage device via the second data bus 20 4 can be read. As below will be explained in more detail, causes the second control device per write cycle of the video storage device 4 or read cycle of the Fifo memory device 3 a transfer of a plurality of data words from the first storage device 3 to the video storage device 4, the respectively re-stored Data word count, as will be explained, of case may vary in case.

Wie noch näher erläutert wird, benötigt die zweite Steuervorrichtung 6 für die richtige Abspeicherung des digitalen Bildsignales in der Videospeichervorrichtung eine Information über die Anzahl der Pixel pro Zeile des eingangsseitig anliegenden Bildsignales, die auch durch die serielle Auslesesteuervorrichtung 9 benötigt wird, welche zusätzlich die Anzahl der Zeilen des Bildes des eingangsseitigen Bildsignalesfür die Auslesesteuerung benötigt. Zu diesem Zwecke ermittelt die Anzeigezählervorrichtung 8 bei dem gezeigten, bevorzugten Ausführungsbeispiel durch Zählen der Taktsignale CLK (1) zwischen zwei Blanksignalen BL(1) einen Horizontalzählwert HG(0...9) sowie durch Zählen der Anzahl der Blanksignale BL(1) zwischen zwei Vertikalsynchronisationssignalen VS(1) die Anzahl der Zeilen des durch das erste Bildsignal dargestellten Bildes als Vertikalzählwert VC(0.. .9).As will be explained in more detail, the second one is required Control device 6 for the correct storage of the digital image signals in the video storage device information about the number of pixels per line of the image signals present on the input side, which also required by the serial readout control device 9 which is additionally the number of lines of the image of the input image signal for the readout control needed. For this purpose, the display counter device determines 8 in the preferred shown Embodiment by counting the clock signals CLK (1) a horizontal count between two blank signals BL (1) HG (0 ... 9) and by counting the number of Blank signals BL (1) between two vertical synchronization signals VS (1) the number of rows by the first image signal displayed image as a vertical count VC (0 .. .9).

Die zweite Steuervorrichtung arbeitet auf einer Zeitbasis, die durch den Oszillator 7 festgelegt wird, wobei der Anfang eines Zyklus durch das Auftreten des Vertikalsynchronisationssignales VS(1) am Rücksetzeingang festgelegt wird. Das der zweiten Steuervorrichtung gleichfalls Zugeführte zweite (ausgangsseitige) Blanksignal BL(2) dient allein zur Steuerung des Auffrischens der dynamischen Videospeichervorrichtung 4 und zur Steuerung der Schieberegisterübernahme, das die Übernahme einer ganzen Speicherzeile aus der Videospeichervorrichtung 4 in das Ausgangsschieberegister (nicht dargestellt) ermöglicht, und unterbricht zu diesem Zweck die Zyklussteuerung für die Ansteuerung der Fifo-Speichervorrichtung 3 und der Videospeichervorrichtung 4. Die Ansteuerung der Videospeichervorrichtung beginnt mit der Adressierung der ersten Zeile und der ersten Spalte der Videospeichervorrichtung 4 bei Nicht-Vorliegen des Flag EF, wobei die Adressenübernahme durch das Reihenadreßübernahmesignal RAS und das Spaltenadreßübemahmesignal CAS gesteuert werden, wobei während des Schreibmodus das Schreibbefehlssignal WB/WE "tief" ist. Die Übernahme der Datenworte von der Fifo-Speichervorrichtung 3 in die Videospeichervorrichtung 4 geschieht im sogenannten "page-mode", wobei die Zeilenadressierung und das Zeilenadreßübernahmesignal RAS während des Einspeicherns von Datenworten in die verschiedenen Spalten dieser Zeile unverändert bleiben, wodurch in an sich bekannter Weise die Einschreibgeschwindigkeit des Videospeichers erhöht wird. Die genaue Abfolge der einzelnen Steuersignale hängt von der Herstellerspezifikation der Videospeichervorrichtung 4 für den bei diesen Vorrichtungen vorgesehenen "page-mode"-Schreibmodus. Details der Adressierung werden unter Bezugnahme auf die Fig. 9 und 10 näher erläutert.The second control device works on a time basis, which is determined by the oscillator 7, wherein the beginning of a cycle by the occurrence of the vertical synchronization signal VS (1) at the reset input is set. That of the second control device also supplied second (output side) Blank signal BL (2) is used only to control the refresh the dynamic video storage device 4 and to control the shift register takeover, the the takeover of an entire line of memory from the video storage device 4 in the output shift register (not shown) allows and interrupts the cycle control for the control the FIFO storage device 3 and the video storage device 4. The control of the video storage device starts addressing the first line and the first column of the video storage device 4 if the flag EF is not present, the address transfer by the row address takeover signal RAS and the column address acquisition signal CAS controlled , whereby during the write mode the Write command signal WB / WE is "low". The takeover of the data words from the FIFO storage device 3 in the video storage device 4 takes place in the so-called "page-mode", where the line addressing and the row address takeover signal RAS during the Storage of data words in the different Columns of this row remain unchanged, which means in the writing speed is known the video memory is increased. The exact sequence the individual control signals depends on the manufacturer's specification the video storage device 4 for the at "page mode" write mode provided for these devices. Details of the addressing are under With reference to FIGS. 9 and 10 explained in more detail.

Die Steuerung des seriellen Auslesens der Videospeichervorrichtung durch die serielle Auslesesteuervorrichtung 9 erfolgt in Synchronisation mit dem monitorseitig vorliegenden zweiten Horizontalsynchronisationssignal HS(2), Verikalsynchronisationssignal VS(2), Taktsignal CLK(2) und Blanksignal BL(2) in einer an sich bekannten Weise.Control of serial readout of the video storage device through the serial readout controller 9 takes place in synchronization with the monitor side present second horizontal synchronization signal HS (2), vertical synchronization signal VS (2), Clock signal CLK (2) and blank signal BL (2) in one known way.

An dieser Stelle sei auf einen wesentlichen Aspekt der Erfindung hingewiesen, der sich aus der erfindungsgemäßen Umsetzung des Bildsignales der ersten Pixelfrequenz in ein Bildsignal der zweiten Pixelfrequenz ergibt. Es ist möglich, nicht nur das am ausgangsseitigen sechsten Datenbus 35 generierte Bildsignal dem Monitor zuzuführen, sondern auch dieses Bildsignal mit einem zweiten, synchronen Bildsignal zu kombinieren, von dem die ausgangsseitige Zeitbasis (VS(2), CLK(2), BL(2), HS(2)) erhalten wurde. Damit ist eine Kombination eines beliebigen ersten Bildsignales, der am Eingang 10, 11 der Schaltung anliegt, mit einem beliebigen zweiten, von einem anderen Graphikstandard stammenden Bildsignal in der Weise möglich, daß das erste Bildsignal auf einer Teilfläche des Monitors zur Anzeige gebracht wird und das zweite Bildsignal auf der restlichen Monitorfläche gezeigt wird.At this point, let's focus on one essential aspect pointed out the invention, which results from the invention Implementation of the image signal of the first pixel frequency results in an image signal of the second pixel frequency. It is possible, not just the one on the output side sixth data bus 35 generated image signal to the monitor feed, but also this image signal with a to combine the second, synchronous image signal, of which the time base on the output side (VS (2), CLK (2), BL (2), HS (2)) was obtained. So that's a combination of any first image signal, which is at the entrance 10, 11 of the circuit is present, with any second, from a different graphics standard Image signal possible in such a way that the first Image signal on a partial area of the monitor for display is brought and the second image signal on the rest Monitor area is shown.

Die Fig. 2 und 3 verdeutlichen die Betriebsweise der ersten Steuervorrichtung 5, die im wesentlichen als Zähler arbeitet. Durch das erste Blanksignal BL(1) wird die erste Steuervorrichtung 5 in einen Anfangszustand gesetzt, um bei Auftreten eines ersten Taktpulses CLK (1) (mit schaltungstechnisch bedingter Verzögerung) ein nulltes Auswahlsignal SEL0 rückzusetzen und ein erstes Auswahlsignal SEL1 zu setzen, wobei beim zweiten Taktpuls CLK(1) das erste Auswahlsignal rückgesetzt und das zweite Auswahlsignal SEL2 gesetzt wird, usw., wobei schließlich nach dem dritten Puls das dritte Auswahlsignal SEL3 rückgesetzt und das Fifo-Schreibsignal WF gesetzt wird, woraufhin nach dem vierten Taktpuls das dritte Auswahlsignal rückgesetzt und das Fifo-Schreibsignal nach dem darauffolgenden ersten Takt rückgesetzf wird. Diese gestaffelten Auswahlsignale SEL0 bis SEL3 werden zur Steuerung der Registervorrichtung 2 verwendet, deren Aufbau nachfolgend unter Bezugnahme auf Fig. 4 näher erläutert wird.2 and 3 illustrate the operation of the first control device 5, which essentially as Counter works. The first blank signal BL (1) the first control device 5 in an initial state set to CLK when a first clock pulse occurs (1) (with circuit-related delay) reset a zero selection signal SEL0 and on to set the first selection signal SEL1, the second Clock pulse CLK (1) reset the first selection signal and the second selection signal SEL2 is set, etc., finally the third after the third pulse Selection signal SEL3 reset and the Fifo write signal WF is set, whereupon after the fourth Clock pulse reset the third selection signal and that Fifo write signal after the following first Clock is reset. These staggered selection signals SEL0 to SEL3 are used to control the register device 2 used, its structure explained in more detail below with reference to FIG. 4 becomes.

Die Registervorrichtung 2 umfaßt drei 4-bit-Register 36, 37, 38 und ein 16-bit-Register 39, die sämtlich mit dem Taktsignaleingang 11 und mit dem Eingangsdatenbus 10 in Verbindung stehen. Die Ausgänge der 4-bit-Register 36 bis 38 sind mit Eingängen des 16-bit-Registers 39 verbunden. Die Register 36 bis 39 werden in der Reihenfolge ihrer Bezugszeichen von den Auswahlsignalen SEL0 bis SEL3 angesteuert, so daß Ansteuerung des 16-bit-Registers 39 durch das vierte Auswahlsignal SEL3 vier eingangsseitige 4-bit-Datenworte in ein ausgangsseitiges 16-bit-Datenwort umgewandelt sind.The register device 2 comprises three 4-bit registers 36, 37, 38 and a 16-bit register 39, all of them with the clock signal input 11 and with the input data bus 10 communicating. The outputs of the 4-bit registers 36 to 38 are with inputs of the 16-bit register 39 connected. The registers 36 to 39 are in the order of their reference numbers from the selection signals SEL0 to SEL3 controlled so that control of the 16-bit register 39 by the fourth selection signal SEL3 four 4-bit data words on the input side converted into a 16-bit data word on the output side are.

Nachfolgend wird unter Bezugnahme auf die Fig. 5 bis 8 die Struktur und Funktion der Anzeigezählervorrichtung 8 näher erläutert. Fig. 5 zeigt die zeitliche Relation des ersten Horizontalsynchronisationssignales HS(1), des ersten Blanksignales BL(1) und des ersten Taktsignales CLK(1).In the following, with reference to FIG. 5 to 8 the structure and function of the display counter device 8 explained in more detail. 5 shows the temporal relation of the first horizontal synchronization signal HS (1), the first blank signal BL (1) and the first Clock signal CLK (1).

Wie in Fig. 6 gezeigt ist, umfaßt die Anzeigezählervorrichtung 8 einen Horizontalzähler 40, dessen Takteingang das erste Taktsignal CLK(1) und dessen Rücksetzeingang das erste Horizontalsynchronisationssignal HS(1) zugeführt werden. Das erste Blanksignal BL (1) steuert die Übernahme des Zählerstandes des Horizontalzählers 40 in das Register 41 für den Horizontalzählwert HC, der ausgangsseitig am Bus 25 erscheint.As shown in Fig. 6, the display counter device includes 8 a horizontal counter 40, the clock input the first clock signal CLK (1) and its reset input the first horizontal synchronization signal HS (1) are supplied. The first blank signal BL (1) controls the transfer of the counter reading from the horizontal counter 40 in the register 41 for the horizontal count HC, which appears on the output side of bus 25.

Fig. 7 zeigt (selbstverständlich mit einer gegenüber Fig. 1 gestrafften Zeitbasis) den schematisierten zeitlichen Zusammenhang zwischen dem ersten Blanksignal BL(1), dem ersten Horizontalsynchronisationssignal HS(1) und dem ersten Vertikalsynchronisationssignal VS(1).Fig. 7 shows (of course with one opposite Fig. 1 streamlined time base) the schematic temporal Relationship between the first blank signal BL (1), the first horizontal synchronization signal HS (1) and the first vertical synchronization signal VS (1).

Fig 8 zeigt den die Vertikalzählung oder Zeilenzählung betreffenden Anteil der Anzeigezählervorrichtung 8, welcher einen Vertikalzähler 42 umfaßt, dessen Takteingang das erste Blanksignal BL(1) und dessen Rücksetzeingang das erste Vertikalsynchronisationssignal VS(1) zugeführt werden, und der ausgangsseitig mit einem Register 43 für den Vertikal-Zählwert VC verbunden ist, dessen Takteingang wiederum durch das erste Vertikalsynchronisationssignal angesteuert, und das ausgangsseitig mit dem vierten Datenbus 26 in Verbindung steht, auf dem der Vertikalzählwert VC ansteht.8 shows the vertical counting or line counting relevant portion of the display counter device 8, which comprises a vertical counter 42, the clock input the first blank signal BL (1) and its reset input the first vertical synchronization signal VS (1) and the output side with a Register 43 for the vertical count VC connected is whose clock input is again through the first Vertical synchronization signal driven, and that on the output side with the fourth data bus 26 in connection stands on which the vertical count VC is present.

Fig. 9 zeigt die Struktur der Videospeichervorrichtung 4, die in dem gezeigten Beispielsfall in vier Speicherebenen 44 bis 47 unterteilt ist. Diese Unterteilung der Videospeichervorrichtung ermöglicht eine Reduktion der Datenflußrate bei der Einspeicherung und eine vereinfachte Adressierung. Bei dem gezeigten Beispielsfall ist jede der Speicherebenen 44 bis 47 mit 512 x 512 Speicherplätzen versehen, wobei jede der Speicherebenen 44 bis 47 bei der Horizontaladresse 256 gezweiteilt ist. Es ergibt sich eine Speicherorganisation von 1024 x 1024 Plätzen. Beim Ablegen der Datenworte in der Videospeichervorrichtung werden die Daten jeweils gleichzeitig den Eingängen D0 bis D3 zugeführt, wobei in der beschriebenen "page-mode"-Speicherweise zunächst die erste Zeile des Bildes in den jeweiligen ersten Speicherzeilen zwischen den Horizontaladressen 0 und einer Maximaladresse abgelegt werden, die dem Horizontalzählwert HC geteilt durch die Anzahl 4 der Speicherebenen entspricht. Nach Erreichen dieser Horizontaladresse vollführt der (noch zu beschreibende) Horizontaladreßzähler einen Sprung zu der Horizontaladresse 256, bei der die Speicherebene unterteilt ist, um fortfahrend von diesem Horizontaladreßwert bis zu einem um den Horizontalzählwert HC geteilt durch die Anzahl der Speicherebenen erhöhten Wert zu zählen, bevor nach erfolgtem Ablegen der zweiten Zeile des ersten Bildsignales die dritte Zeile des ersten Bildsignales sodann in die zweite Zeile der Videospeichervorrichtung 44 bis 47; 4 abgelegt wird. Das Inkrementieren des Reihenadreßzählers erfolgt nach jedem zweiten Erreichen des um die Anzahl der Speicherebenen geteilten Horizontalzählwertes HC.Fig. 9 shows the structure of the video storage device 4, in the example shown in four memory levels 44 to 47 is divided. This subdivision the video storage device enables a reduction the data flow rate when saving and a simplified addressing. In the example shown each of the memory levels 44 to 47 is 512 x 512 storage locations, each of the storage levels 44 to 47 divided in two at the horizontal address 256 is. A storage organization results of 1024 x 1024 seats. When storing the data words in the video storage device, the data are each simultaneously fed to inputs D0 to D3, where in the described "page-mode" memory first the first line of the picture in the respective first lines of memory between the horizontal addresses 0 and a maximum address, which the horizontal count HC divided by the number 4 corresponds to the storage levels. After reaching this Horizontal address is carried out by the (still to be described) Horizontal address counter jumps to the horizontal address 256, at which the storage level is divided is to continue from this horizontal address value to to a divided by the horizontal count HC count the number of storage levels increased value before after the second line of the first image signal, the third line of the first image signal then on the second line of the video storage device 44 to 47; 4 is filed. Incrementing the Row address counter occurs after every second reaching the divided by the number of storage levels Horizontal count HC.

Ein Blockdiagramm der zweiten Steuervorrichtung ist in Fig. 10 wiedergegeben, und umfaßt einen Spaltenadreßzähler 48, einen Reihenadreßzähler 49 und einen Steuersignalgenerator zum Erzeugen der Steuersignale für die Videospeichereinrichtung 4. Der Spaltenadreßzähler 48 wird an seinem Takteingang 51 durch das Fifolesesignal RF getaktet und wird durch das erste Vertikalsynchronisationssignal VS(.1) an seinem Rücksetzeingang 52 rückgesetzt und ist ferner an den dritten Datenbus 25 zum Empfangen des Horizontalzählwertes HC angeschlossen.A block diagram of the second control device is shown in Fig. 10 and includes a column address counter 48, a row address counter 49 and one Control signal generator for generating the control signals for the video storage device 4. The column address counter 48 is through at its clock input 51 the fifolesis signal is clocked by the first RF Vertical synchronization signal VS (.1) at its reset input 52 reset and is also on the third Data bus 25 for receiving the horizontal count HC connected.

Nach Rücksetzen des Spaltenadreßzählers 48 vollführt dieser die soeben unter Bezugnahme auf Fig. 9 erläuterte Horizontaladreßzählung. Im Beispielsfall ist dies eine von Null bis zu einem Viertel des Horizontalzählwertes HC ansteigende Zählung mit nachfolgendem Sprung auf die Mittenhorizontaladresse 256, um anschließend wiederum die Adresse kontinuierlich zu inkrementieren, bis diese Mittenadresse um ein Viertel des Horizontalzählwertes HC übertroffen ist. Zu diesem Zeitpunkt erscheint eine "1 " am Steuerausgang TC des Spaltenadreßzählers 48, welcher mit dem Takteingang 53 des Reihenadreßzählers 49 verbunden ist, der durch diesen Signalpuls inkrementiert wird, bis er durch Auftreten des ersten Vertikalsynchronisationssignales VS (1) rückgesetzt wird.After resetting the column address counter 48 completed this is just with reference to FIG. 9 horizontal address count explained. In the example case is this is from zero to a quarter of the horizontal count HC increasing count followed by Jump to center horizontal address 256 to then the address again continuously increment until this center address by a quarter of the horizontal count HC is exceeded. To this A "1" appears at the control output TC of the time Column address counter 48, which with the clock input 53 of the row address counter 49 is connected by this signal pulse is incremented until it occurs of the first vertical synchronization signal VS (1) is reset.

Dem Steuersignalgenerator 50 werden das Taktsignal CLK* vom Oszillator 7 an dessen Takteingang 54, das Flag EF von der Fifo-Speichervorrichtung 3 an dessen Flageingang 55 das Steuersignal TC vom Spaltenadreßzähler 48 an dessen Steuersignaleingang 56 sowie das sekundärseitige Horizontalsynchronisationssignal HS(2) an dessen Horizontalsynchronisationseingang 57 zugeführt. Die Erzeugung des Reihenadreßübernahmesignals RAS, des Spaltenadreßübernahmesignal CAS, des Datenübernahmesignales DT/OE für die Übernahme von Daten aus der Videospeichervorrichtung in dessen Ausgangsschieberegister und des Schreibsignales WB/WE für die Videospeichervorrichtung erfolgt gemäß der Spezifikation der jeweils verwendeten Videospeichervorrichtung für deren Betrieb in den "page-mode"-Schreibmodus. Das Auslesesignal RF kann durch UND-Verknüpfen des Spallenadreßübernahmesignales CAS und des zweiten Horizontalsynchronisationssignales HS(2) mittels eines Gatters 58 erzeugt werden.The control signal generator 50 becomes the clock signal CLK * from oscillator 7 at its clock input 54, the flag EF from the fifo storage device 3 thereon Flag input 55, the control signal TC from the column address counter 48 at its control signal input 56 and the secondary-side horizontal synchronization signal HS (2) at its horizontal synchronization input 57 fed. The generation of the Row address takeover signal RAS, the column address takeover signal CAS, the data transfer signal DT / OE for the transfer of data from the Video storage device in its output shift register and the write signal WB / WE for the video storage device takes place according to the specification of the video storage device used for each Operation in "page-mode" write mode. The Readout signal RF can be combined by ANDing the CAS address takeover signal and the second Horizontal synchronization signal HS (2) by means of a Gates 58 are generated.

Bei dem beschriebenen Ausführungsbeispiel wird eine Registervorrichtung verwendet, um die eingangsseitig anliegenden Datenworte mit der ersten Pixelfrequenz in Datenworte von mehrfacher Bitlänge bei einer durch die Mehrzahl geteilten ersten Pixelfrequenz zu erzeugen, wodurch die Anforderungen an die Einspeicherungsgeschwindigkeit in die Fifo-Speichervorrichtung gesenkt werden können. Die eingangsseitige Registervorrichtung wird jedoch dann entbehrlich, wenn das erste Bildsignal eine entsprechende niedrige Datenwortrate hat oder wenn eine Fifo-Speichervorrichtung mit entsprechend hoher Arbeitsgeschwindigkeit verwendet wird.In the described embodiment a register device used to the input side data words at the first pixel frequency in data words of multiple bit length at one to generate by the plurality of divided first pixel frequencies thereby reducing the speed of injection into the FIFO storage device can be lowered. The input register device however becomes dispensable when the first Image signal a corresponding low data word rate has or if a Fifo storage device with correspondingly high working speed used becomes.

Bei der erläuterten Ausführungsform wird die Abspeicherung in die Videospeichervorrichtung jeweils ausgehend von einer Horizontaladresse 0 und einer Vertikaladresse 0, also ausgehend von der linken oberen Ecke der Videospeichervorrichtung vorgenommen.In the illustrated embodiment, the storage into the video storage device each starting from a horizontal address 0 and one Vertical address 0, i.e. starting from the top left Corner of the video storage device made.

Der Erfindungsgegenstand ist nicht beschränkt auf eine bestimmte Anzahl von Bits der Datenworte des verarbeiteten Bildsignales und ist ebenso auf Schwarzweiß-Bildsignale wie Farb-Bildsignale anwendbar. Wenn beispielsweise eine Farbvielfalt von 256 Farben gewünscht ist, was Eingangsdatenworten von 8 bit entspricht, so können zwei Schaltungen gemäß Fig. 1 parallel geschaltet werden.The subject matter of the invention is not limited to a certain number of bits of the data words of the processed Image signal and is also based on black and white image signals how to use color image signals. If, for example, a color variety of 256 colors What is desired is what corresponds to 8-bit input data words two circuits in accordance with FIG be switched.

Obwohl die bevorzugte Ausführungsform des Erfindungsgegenstande hardware-mäßig mittels Gate-Arrays implementiert ist, ist es denkbar, Zählervorrichtungen und Steuervorrichtungen sowie eine geeignete Ansteuervorrichtung für die erste Speichervorrichtung, die diese als Fifo-Speichervorrichtung arbeiten läßt, soft-ware-mäßig zu realisieren.Although the preferred embodiment of the subject invention in terms of hardware by means of gate arrays is implemented, it is conceivable counter devices and control devices and a suitable control device for the first storage device that lets it work as a FIFO storage device, soft-ware-wise to realize.

Claims (19)

  1. A method of driving a monitor, which operates at a second pixel frequency and the display of which is adapted to be generated by reading an output-side digital image signal at the second pixel frequency from a video storage device (4), on the basis of all the data words of an input-side digital image signal having a first pixel frequency, wherein the image signal having the first pixel frequency is not synchronized with the monitor image display of the second pixel frequency,
    said method comprising the following steps:
    reading each of the successive data words of the input-side digital image signal into a fifo storage device (3) at a frequency depending on said first pixel frequency;
    reading from the fifo storage device (3) data words of the digital image signal which are to be stored in the video storage device (4), the reading of data words from the fifo storage device (3) being interrupted when data words are being read from the video storage device (4) and the reading of data words from the fifo storage device (3) being also interrupted in an empty condition of said fifo storage device (3) so that the number of data words which can be re-stored from the fifo storage device (3) into the video storage device (4) varies.
  2. A method according to claim 1, comprising the following step:
    combining the image signal read from the video storage device (4) with an additional image signal, by means of which the second pixel frequency is determined, for jointly displaying on the monitor two images whose original image signals have different pixel frequencies.
  3. A method according to claim 2, wherein the image signal having the first pixel frequency and said additional image signal are image signals of different graphics standards.
  4. A method according to one of the claims 1 to 3, wherein the data words read from the fifo storage device (3) are outputted an a data bus (20) which serves to establish a data connection with the video storage device (4).
  5. A monitor control circuit for driving a monitor, which operates at a second pixel frequency and the display of which is adapted to be generated by reading an output--side digital image signal at the second pixel frequency from a video storage device (4), on the basis of all the data words of an input-side digital image signal having a first pixel frequency, the image signal having the first pixel frequency being not synchronized with the monitor image display of the second pixel frequency, comprising
    a fifo storage device (3),
    a first control device (5) which reads each of the successive data words of the input-side digital image signal into the fifo storage device (3) at a frequency depending on the first pixel frequency,
    a second control device (6) for controlling the reading of data words of the digital image signal, which are to be written into the video storage device (4), from the fifo storage device (3), said second control device (6) interrupting the reading of data words from the fifo storage device (3) when data words are being read from the video storage device (4) and interrupting the reading of data words from the fifo storage device (3) also in an empty condition of said fifo storage device (3) so that the number of data words which can be re-stored from the fifo storage device (3) into the video storage device (4) varies.
  6. A monitor control circuit according to claim 5, comprising a register device (2), which has its input side connected to the fifo storage device (3) and by means of which the data words of the digital image signal received at the first pixel frequency can be converted into data words, which include a multiple number of bits with respect to the number of bits in the received data words, at a first pixel frequency divided by said multiple.
  7. A monitor control circuit according to claim 6, wherein the register device (2) includes a number of first registers (36, 37, 38) equal to said multiple minus one, each of said registers (36, 37, 38) storing one of the received data words,
    the register device (2) additionally includes a second register (39) for storing the data word which includes the multiple number of bits, said second register (39) having part of its inputs connected to outputs of said first registers (36, 37, 38) and another part of its inputs connected to a bus (10) for storing one of the received data words, and
    the first control device (5) sequentially controls each of the first registers (36, 37, 38) and the second register (39) by a selection signal (SEL0, SEL1, SEL2, SEL3) for accepting input-side data words.
  8. A monitor control circuit according to claim 7, wherein the first control device (5) is provided with a clock input (16), which is adapted to have supplied thereto a clock signal (CLK(1)) having the first pixel frequency, and with a holding input (17), which is adapted to have supplied thereto a blank signal (BL(1)) of the first image signal, and
    the first control device (5) has a number of selection outputs (12) corresponding to said multiple and is constructed in such a way that the respective selection signals (SEL0, SEL1, SEL2, SEL3) at the selection outputs (12) are displaced with respect to one another by a first pixel period.
  9. A monitor control circuit according to claim 7 or 8, wherein the first control device (5) additionally includes a write command output for producing a write command (WF) for the fifo storage device (3), said write command (WF) being displaced by at least one first pixel period with respect to the selection signal (SEL3) for the second register (39), and the fifo storage device (3) has a write command input (15) and accepts a waiting data word when a write command is applied.
  10. A monitor control circuit according to one of the claims 5 to 9, comprising a display counting device (8), which is adapted to have supplied thereto the first clock signal (CLK(1)) having the first pixel frequency and the first blank signal (BL(1)) of the first image signal, said display counting device (8) being provided with a horizontal counter (40, 41) for counting the first clock signals (CLK(1)) between two first blank signals (BL(1)).
  11. A monitor control circuit according to claim 6, wherein the display counting device (8) additionally includes a vertical counter (42, 43), which is adapted to have supplied thereto the first blank signals (BL(1)) and the first vertical synchronization signals (VS(1)) and by means of which the number of first blank signals (BL(1)) between two first vertical synchronization signals (VS(1)) can be ascertained.
  12. A monitor control circuit according to one of the claims 5 to 11, wherein the fifo storage device (3) has a reset input (14), which is adapted to have supplied thereto the first vertical synchronization signal (VS(1)).
  13. A monitor control circuit according to claim 12, wherein the fifo storage device (3) has a flag output for a flag (EF) indicating the empty condition of the storage areas of the fifo storage device (3), and the flag output is connected to a flag input of the second control device (6).
  14. A monitor control circuit according to one of the claims 11 to 13, wherein the second control device (6) has a read command output (RF) which is connected to a read control input of the fifo storage device, and
    the fifo storage device (3) is constructed in such a way that in response to each read command pulse (RF) applied to its read control input it will transfer a data word to the video storage device (4).
  15. A monitor control circuit according to one of the claims 5 to 14, wherein the second control device (6) has a reset input, which is adapted to have supplied thereto the vertical synchronization signal (VS(1)) of the first image signal, and
    the second control device (6) is additionally provided with a clock input which has connected thereto an oscillator (7).
  16. A monitor control circuit according to one of the claims 10 to 15, wherein the second control device (6) is connected to the display counting device (8) and receives therefrom at least the count (HC) of the horizontal counter (40, 41).
  17. A monitor control circuit according to claim 15 or 16 in dependence on claim 14, wherein, for driving the video storage device (4) on the time basis of the clock predetermined by the oscillator (7), the second control device (6) will start from a logical initial condition and produce, per read cycle, one read command pulse (RF) for the fifo storage device (3), one horizontal address signal (ADR) and one vertical address signal (ADR) for addressing the video storage device (4) and video storage control signals (RAS, CAS, WB/WE, DT/OE) in response to the appearance of the first vertical synchronization signal (VS(1)).
  18. A monitor control circuit according to claim 17, wherein the video storage control signals comprise a columm address transfer signal (CAS), a line address transfer signal (RAS), a write signal (WB/WE) representative of the write condition for writing into the video storage device (4) and a shift register transfer signal (DT/OE) permitting transfer of a data word from the video storage device (4) to the output shift register.
  19. A monitor control circuit according to claim 18, wherein the second control device (6) produces the above-mentioned control signals for the video storage device (4) in a way, dependent on the specification of the video storage device (4) used, such that the data words supplied by the fifo storage device (3) are written into the video storage device (4) in the so-called "page-mode" memory control fashion, in the case of which the line address signal (ADR) and the line address transfer signal (RAS) for the video storage device (4) remain unchanged when data are being stored in a line of the video storage device (4).
EP92107715A 1989-05-12 1990-03-21 Method of and device for controlling a monitor Expired - Lifetime EP0500147B2 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE3915562 1989-05-12
DE3915562A DE3915562C1 (en) 1989-05-12 1989-05-12
EP90904821A EP0468973B2 (en) 1989-05-12 1990-03-21 Monitor control circuit

Related Parent Applications (2)

Application Number Title Priority Date Filing Date
EP90904821A Division EP0468973B2 (en) 1989-05-12 1990-03-21 Monitor control circuit
EP90904821.7 Division 1990-03-21

Publications (4)

Publication Number Publication Date
EP0500147A2 EP0500147A2 (en) 1992-08-26
EP0500147A3 EP0500147A3 (en) 1992-10-14
EP0500147B1 EP0500147B1 (en) 1996-04-24
EP0500147B2 true EP0500147B2 (en) 2001-08-22

Family

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Application Number Title Priority Date Filing Date
EP92107715A Expired - Lifetime EP0500147B2 (en) 1989-05-12 1990-03-21 Method of and device for controlling a monitor
EP90904821A Expired - Lifetime EP0468973B2 (en) 1989-05-12 1990-03-21 Monitor control circuit

Family Applications After (1)

Application Number Title Priority Date Filing Date
EP90904821A Expired - Lifetime EP0468973B2 (en) 1989-05-12 1990-03-21 Monitor control circuit

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US (1) US5329290A (en)
EP (2) EP0500147B2 (en)
JP (1) JP2971132B2 (en)
KR (1) KR960003396B1 (en)
AT (2) ATE85858T1 (en)
DE (3) DE3915562C1 (en)
DK (2) DK0500147T4 (en)
ES (2) ES2089283T5 (en)
WO (1) WO1990013886A2 (en)

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Also Published As

Publication number Publication date
KR960003396B1 (en) 1996-03-09
DE59000902D1 (en) 1993-03-25
WO1990013886A3 (en) 1990-12-27
JPH04507147A (en) 1992-12-10
EP0468973B2 (en) 2001-05-09
ES2089283T5 (en) 2002-01-16
EP0500147B1 (en) 1996-04-24
ES2089283T3 (en) 1996-10-01
EP0500147A2 (en) 1992-08-26
DK0468973T4 (en) 2001-07-30
DK0468973T3 (en) 1993-05-10
DK0500147T3 (en) 1996-05-13
ATE85858T1 (en) 1993-03-15
EP0468973A1 (en) 1992-02-05
DK0500147T4 (en) 2001-10-08
DE3915562C1 (en) 1990-10-31
ES2038054T3 (en) 1993-07-01
EP0468973B1 (en) 1993-02-17
WO1990013886A2 (en) 1990-11-15
ES2038054T5 (en) 2001-09-16
US5329290A (en) 1994-07-12
JP2971132B2 (en) 1999-11-02
ATE137352T1 (en) 1996-05-15
DE59010304D1 (en) 1996-05-30
KR920701936A (en) 1992-08-12
EP0500147A3 (en) 1992-10-14

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