EP0500147B2 - Méthode et dispositif de commande d'un moniteur - Google Patents

Méthode et dispositif de commande d'un moniteur Download PDF

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Publication number
EP0500147B2
EP0500147B2 EP92107715A EP92107715A EP0500147B2 EP 0500147 B2 EP0500147 B2 EP 0500147B2 EP 92107715 A EP92107715 A EP 92107715A EP 92107715 A EP92107715 A EP 92107715A EP 0500147 B2 EP0500147 B2 EP 0500147B2
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EP
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Prior art keywords
storage device
signal
data words
video storage
image signal
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EP92107715A
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German (de)
English (en)
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EP0500147B1 (fr
EP0500147A2 (fr
EP0500147A3 (en
Inventor
Stefan Schwarz
Ian Cartwright
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SPEA SOFTWARE GMBH
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SPEA Software GmbH
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/395—Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G1/00—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data
    • G09G1/06—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data using single beam tubes, e.g. three-dimensional or perspective representation, rotation or translation of display pattern, hidden lines, shadows
    • G09G1/14—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data using single beam tubes, e.g. three-dimensional or perspective representation, rotation or translation of display pattern, hidden lines, shadows the beam tracing a pattern independent of the information to be displayed, this latter determining the parts of the pattern rendered respectively visible and invisible
    • G09G1/16—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data using single beam tubes, e.g. three-dimensional or perspective representation, rotation or translation of display pattern, hidden lines, shadows the beam tracing a pattern independent of the information to be displayed, this latter determining the parts of the pattern rendered respectively visible and invisible the pattern of rectangular co-ordinates extending over the whole area of the screen, i.e. television type raster
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/393—Arrangements for updating the contents of the bit-mapped memory

Definitions

  • the present invention is concerned with a Method for driving a at a second pixel frequency working monitor, its display by reading out a digital image signal with a second pixel frequency from a video storage device can be generated based on all data words a digital pixel having a first pixel frequency Image signal.
  • the present invention is also concerned with a monitor control circuit which serves a monitor operating at a second pixel frequency to control, its display by reading a digital image signals with the second pixel frequency can be generated from a video storage device due to all data words a first pixel frequency digital image signal.
  • Computer monitors are known to become dependent of the requirements regarding the required Screen resolution due to different graphics cards Controlled categories that are among themselves through the horizontal and vertical resolution, so the number of pixels, in horizontal and vertical Distinguish direction as well as by the pixel frequencies.
  • Known graphics card standards are, for example MDA (320 x 200 pixels, black and white, at 16 MHz pixel frequency), CGA (320 x 200 pixels, color, at 20 MHz pixel frequency), HERCULES (740x400 pixels, Black and white, at 27 MHz pixel frequency), EGA (640 x 350 pixels, color, at 30 MHz pixel frequency), VGA (640 x 480 pixels, color, at 32 MHz Pixel frequency), SUPER-EGA (800 x 600 or 1024 x 768 pixels, color, at 50 MHz pixel frequency, as well recently the so-called HR (High Resolution) graphics systems with 1024 x 768, 1080 x 1024 and 1600 x 1280 pixels, color, at pixel frequencies between 60 MHz and 170 MHz.
  • HR High
  • DE-A1-38 04 460 already discloses a monitor control circuit for controlling one at a second pixel frequency working monitor a digital one having a first pixel frequency Image signal, with a serial-parallel converter on the input side in the form of a shift register, on the Output connected to a video storage device is, in which the input image signal after its Serial-parallel conversion can be filed. Since it is the memory is only a shift register for serial-parallel conversion acts for the purpose of Serial-parallel conversion with the clock of the subsystem after the occurrence of the blank signal of the subsystem is clocked, the input side Image signal with the frequency of its subsystem clock written in the video storage device.
  • the raster elements can be controlled in a predetermined sequence must, and which has an image memory between a processor and the recording device to arrange a FIFO memory. Once the FIFO store is empty, an interrupt command interrupts the im Processor running program, whereupon new data are written into the Fifo memory, whereby after filling the processor the interrupted Resume program run.
  • FR-A-2 608 291 is a circuit for adaptation a graphics card of a certain television standard known to a monitor of another television standard, one with a video processor Data processing by a periodically generated Fast pulse in relation to that for the conversion necessary to be omitted or inserted Image lines is interrupted. This does not make it possible complete update of the monitor image.
  • EP-A-261791 is not concerned with the illustration an image signal with a first pixel frequency on a monitor running at a second pixel frequency works, but with updating the content of a Refresh memory for a high resolution monitor due to an image signal source generated by a Main memory is formed.
  • Both the image signal source which can be read out under the control of a microprocessor is, like the rest of the entire monitor system work under the uniform timing of a single clock generator, so that the problem of Conversion of image signals of different pixel frequencies cannot occur here.
  • This well-known System to refresh the memory of one Only such data points of the Main memory, which contain new image information, pushed into a data fifo buffer.
  • a data pattern, which to refresh and not to refresh Refresh memory pixel is displayed in another Fifo register by the microprocessor brought in. Be in a normal mode of operation all image data for the monitor in sequence only from the refresh memory under the effect of a Read address generator and fed to the monitor. If a refresh is needed, be discontinuously only the image pixels to be refreshed pushed out of the data fifo buffer and on the one hand under control of the control fifo memory in the refresh memory and on the other hand to the so defined Pixels of the monitor passed.
  • the invention is therefore based on the object such a monitor driving method and such To create monitor control circuit by monitor operating at a second pixel frequency a digital one having a first pixel frequency Image signals can be controlled such that the ones to be displayed Image signals are error-free and complete are updated.
  • the invention is based on the finding that the control of the one working with the second pixel frequency Monitors with the first pixel frequency is neither synchronized nor usually in a fixed, there is an even number ratio, by means of the image signal the first pixel frequency is then possible if the data words of the digital image signal initially cached in a FIFO storage device before going into a video storage device stored in synchronization with the operation of the monitor at the second pixel frequency can be read out in a manner known per se, to generate the monitor display.
  • FIG. 1 The embodiment of a monitor control device shown in FIG. 1 according to the present invention, those in their entirety with the reference number 1 a register device 2, a first storage device designed as a FIFO storage device 3, a video storage device 4, a first control device 5, a second control device 6, an oscillator 7, a display counter device 8 and a serial readout control device 9.
  • the register device 2 is on the input side with a Input data bus 10 connected on the data words a digital image signal with the first pixel frequency available.
  • the input data bus 10 can extend to a VGA interface, for example.
  • the input data bus 10 comprises one connection each for the three basic colors R, G, B and a connection for a brightness bit I.
  • Each data word represents a pixel with 4 bit depth.
  • the register device 2 is also on the input side with a clock signal input 11 for a clock signal with the first pixel frequency.
  • the register device 2 receives from the first Control device 5 selection signals SEL0, SEL1, SEL2, SEL3 via a selection data bus 12, the four Bit.
  • the register device 2 is on the output side via a first data bus 13 with inputs of the Fifo storage device 3 in connection, which also a Reset input 14 has a vertical synchronization signal VS (1) of the first image signal can be fed is. Furthermore, the FIFO memory device 3 of the first control device 5 at its write input 15, a write command signal WF is supplied.
  • the first Control device 5 has a clock input 16 for the first clock signal CLK (1), a blank input 17 for the blank signal BL (1) of the first image signal.
  • the FIFO storage device is on the output side 3 via a second data bus 20 with the video storage device 4 in connection.
  • the display counter device 8 has a clock input 21 for the first clock signal CLK (1), a blank input 22 for the blank signal BL (1) of the first image signal, a vertical synchronization input 23 for the vertical synchronization signal VS (1) and a horizontal synchronization input 24 for the horizontal synchronization signal HS (1).
  • the display counter device is on the output side 8 by means of a third data bus 25 for a horizontal count HC with the second control device 6 as well as with the serial readout control device 9 in Connection.
  • the display counter device also stands 8 via a fourth data bus 26 for a vertical count VC with the serial readout controller in Connection.
  • the second control device 6 is on the output side with inputs of the video storage device via a Control bus 27 and an address bus 28 in connection.
  • the Control bus 27 each includes a line for a row address takeover signal RAS, a column address strobe CAS, a write command signal WB / WE and a data transfer signal DT / OE for taking over a Data line from the video storage device 4 in one Readout shift registers of the same (not shown).
  • the serial read-out control device 9 is on the output side via a second control bus 29 for control signals SC, SOE for reading out the video storage device 4 with control inputs of the latter in connection.
  • the video storage device 4 stands again via a fifth data bus 30 with a Data input from the serial readout control device 9 connected, which in turn has a vertical synchronization input 31 for the vertical synchronization signal VS (2) of the second monitor-side image signal, one Clock input 32 for a second clock signal CLK (2) with the second pixel frequency, a blank input 33 for the second blank signal BL (2) and a horizontal synchronization input 34 for the horizontal synchronization signal HS (2) of the second image signal on the monitor side having.
  • the serial readout control device is on the output side 9 via a sixth data bus 35 with the DAC digital-to-analog converter (not shown) Monitors in connection. Because the structure of the monitor what is required in the prior art is required not their explanation.
  • the register device 2 carries out a serial-parallel conversion of four consecutive data words, those with the pixel frequency on the input data bus 10 are present, through, the output generated Data words that have four times the number of bits, so Data words with a length of 16 bits are in parallel be given the first data bus 13.
  • This implementation of 4-bit data words in 16-bit data words under the control of the first control device 5 by means of the selection signals SEL0, ... SEL3, which after Completion of this implementation of the FIFO storage device 3 supplies a write command signal 15.
  • the FIFO storage device is 3 constructed in such a way that it is read in first Data words when triggered by the read command RF first into the video storage device via the second data bus 20 4 can be read.
  • Control device 6 for the correct storage of the digital image signals in the video storage device information about the number of pixels per line of the image signals present on the input side, which also required by the serial readout control device 9 which is additionally the number of lines of the image of the input image signal for the readout control needed.
  • the display counter device determines 8 in the preferred shown Embodiment by counting the clock signals CLK (1) a horizontal count between two blank signals BL (1) HG (0 ... 9) and by counting the number of Blank signals BL (1) between two vertical synchronization signals VS (1) the number of rows by the first image signal displayed image as a vertical count VC (0 .. .9).
  • the second control device works on a time basis, which is determined by the oscillator 7, wherein the beginning of a cycle by the occurrence of the vertical synchronization signal VS (1) at the reset input is set. That of the second control device also supplied second (output side) Blank signal BL (2) is used only to control the refresh the dynamic video storage device 4 and to control the shift register takeover, the the takeover of an entire line of memory from the video storage device 4 in the output shift register (not shown) allows and interrupts the cycle control for the control the FIFO storage device 3 and the video storage device 4.
  • the control of the video storage device starts addressing the first line and the first column of the video storage device 4 if the flag EF is not present, the address transfer by the row address takeover signal RAS and the column address acquisition signal CAS controlled , whereby during the write mode the Write command signal WB / WE is "low".
  • the takeover of the data words from the FIFO storage device 3 in the video storage device 4 takes place in the so-called "page-mode", where the line addressing and the row address takeover signal RAS during the Storage of data words in the different Columns of this row remain unchanged, which means in the writing speed is known the video memory is increased.
  • the exact sequence the individual control signals depends on the manufacturer's specification the video storage device 4 for the at "page mode" write mode provided for these devices. Details of the addressing are under With reference to FIGS. 9 and 10 explained in more detail.
  • Control of serial readout of the video storage device through the serial readout controller 9 takes place in synchronization with the monitor side present second horizontal synchronization signal HS (2), vertical synchronization signal VS (2), Clock signal CLK (2) and blank signal BL (2) in one known way.
  • the first blank signal BL (1) the first control device 5 in an initial state set to CLK when a first clock pulse occurs (1) (with circuit-related delay) reset a zero selection signal SEL0 and on to set the first selection signal SEL1, the second Clock pulse CLK (1) reset the first selection signal and the second selection signal SEL2 is set, etc., finally the third after the third pulse Selection signal SEL3 reset and the Fifo write signal WF is set, whereupon after the fourth Clock pulse reset the third selection signal and that Fifo write signal after the following first Clock is reset.
  • These staggered selection signals SEL0 to SEL3 are used to control the register device 2 used, its structure explained in more detail below with reference to FIG. 4 becomes.
  • the register device 2 comprises three 4-bit registers 36, 37, 38 and a 16-bit register 39, all of them with the clock signal input 11 and with the input data bus 10 communicating.
  • the outputs of the 4-bit registers 36 to 38 are with inputs of the 16-bit register 39 connected.
  • the registers 36 to 39 are in the order of their reference numbers from the selection signals SEL0 to SEL3 controlled so that control of the 16-bit register 39 by the fourth selection signal SEL3 four 4-bit data words on the input side converted into a 16-bit data word on the output side are.
  • 5 shows the temporal relation of the first horizontal synchronization signal HS (1), the first blank signal BL (1) and the first Clock signal CLK (1).
  • the display counter device includes 8 a horizontal counter 40, the clock input the first clock signal CLK (1) and its reset input the first horizontal synchronization signal HS (1) are supplied.
  • the first blank signal BL (1) controls the transfer of the counter reading from the horizontal counter 40 in the register 41 for the horizontal count HC, which appears on the output side of bus 25.
  • Fig. 7 shows (of course with one opposite Fig. 1 streamlined time base) the schematic temporal Relationship between the first blank signal BL (1), the first horizontal synchronization signal HS (1) and the first vertical synchronization signal VS (1).
  • the display counter device 8 shows the vertical counting or line counting relevant portion of the display counter device 8, which comprises a vertical counter 42, the clock input the first blank signal BL (1) and its reset input the first vertical synchronization signal VS (1) and the output side with a Register 43 for the vertical count VC connected is whose clock input is again through the first Vertical synchronization signal driven, and that on the output side with the fourth data bus 26 in connection stands on which the vertical count VC is present.
  • Fig. 9 shows the structure of the video storage device 4, in the example shown in four memory levels 44 to 47 is divided. This subdivision the video storage device enables a reduction the data flow rate when saving and a simplified addressing.
  • each of the memory levels 44 to 47 is 512 x 512 storage locations, each of the storage levels 44 to 47 divided in two at the horizontal address 256 is.
  • a storage organization results of 1024 x 1024 seats.
  • Horizontal address counter After reaching this Horizontal address is carried out by the (still to be described) Horizontal address counter jumps to the horizontal address 256, at which the storage level is divided is to continue from this horizontal address value to to a divided by the horizontal count HC count the number of storage levels increased value before after the second line of the first image signal, the third line of the first image signal then on the second line of the video storage device 44 to 47; 4 is filed. Incrementing the Row address counter occurs after every second reaching the divided by the number of storage levels Horizontal count HC.
  • a block diagram of the second control device is shown in Fig. 10 and includes a column address counter 48, a row address counter 49 and one Control signal generator for generating the control signals for the video storage device 4.
  • the column address counter 48 is through at its clock input 51 the fifolesis signal is clocked by the first RF Vertical synchronization signal VS (.1) at its reset input 52 reset and is also on the third Data bus 25 for receiving the horizontal count HC connected.
  • the control signal generator 50 becomes the clock signal CLK * from oscillator 7 at its clock input 54, the flag EF from the fifo storage device 3 thereon Flag input 55, the control signal TC from the column address counter 48 at its control signal input 56 and the secondary-side horizontal synchronization signal HS (2) at its horizontal synchronization input 57 fed.
  • the generation of the Row address takeover signal RAS, the column address takeover signal CAS, the data transfer signal DT / OE for the transfer of data from the Video storage device in its output shift register and the write signal WB / WE for the video storage device takes place according to the specification of the video storage device used for each Operation in "page-mode" write mode.
  • the Readout signal RF can be combined by ANDing the CAS address takeover signal and the second Horizontal synchronization signal HS (2) by means of a Gates 58 are generated.
  • a register device used to the input side data words at the first pixel frequency in data words of multiple bit length at one to generate by the plurality of divided first pixel frequencies thereby reducing the speed of injection into the FIFO storage device can be lowered.
  • the input register device however becomes dispensable when the first Image signal a corresponding low data word rate has or if a Fifo storage device with correspondingly high working speed used becomes.
  • the storage into the video storage device each starting from a horizontal address 0 and one Vertical address 0, i.e. starting from the top left Corner of the video storage device made.
  • the subject matter of the invention is not limited to a certain number of bits of the data words of the processed Image signal and is also based on black and white image signals how to use color image signals. If, for example, a color variety of 256 colors What is desired is what corresponds to 8-bit input data words two circuits in accordance with FIG be switched.

Claims (19)

  1. Méthode de commande d'un moniteur fonctionnant à une seconde fréquence de pixels dont l'affichage peut être généré par la lecture, d'un dispositif de mémoire vidéo (4), d'un signal vidéo numérique du côté sortie à la seconde fréquence de pixels, sur base de tous les mots de données d'un signal vidéo numérique du côté entrée présentant une première fréquence de pixels, le signal vidéo à la première fréquence de pixels n'étant pas synchronisé avec l'affichage d'image au moniteur à la seconde fréquence de pixels, avec les étapes de procédé suivantes consistant à:
    entrer, dans un dispositif de mémoire 'fifo' (3), chacun des mots de données successifs du signal vidéo numérique du côté entrée à une fréquence fonction de la première fréquence de pixels,
    lire, d'un dispositif de mémoire 'fifo' (3), les mots de données du signal vidéo numérique à mémoriser dans le dispositif de mémoire vidéo (4), la lecture du dispositif de mémoire 'fifo' (3) étant interrompue pendant la lecture des mots de données du dispositif de mémoire vidéo (4) et la lecture du dispositif de mémoire 'fifo' (3) étant, par ailleurs, interrompue lors d'un état vide du dispositif de mémoire 'fifo' (3), de sorte que le nombre de mots de données pouvant être transférés du dispositif de mémoire 'fifo' (3) au dispositif de mémoire vidéo (4) varie.
  2. Procédé suivant la revendication 1, avec l'étape de procédé suivante consistant à:
    combiner le signal vidéo lu du dispositif de mémoire vidéo (4) avec un autre signal vidéo par lequel est fixée la seconde fréquence de pixels, pour l'affichage commun au moniteur de deux images dont les signaux vidéo originaux ont des fréquences de pixels différentes.
  3. Procédé suivant la revendication 2, dans lequel le signal vidéo à la première fréquence de pixels et l'autre signal vidéo sont des signaux vidéo de standards graphiques différents.
  4. Procédé suivant l'une des revendications 1 à 3, dans lequel les mots de données lus du dispositif de mémoire 'fifo' (3) sont sortis sur un collecteur de données (20) servant à la communication de données avec le dispositif de mémoire vidéo (4).
  5. Circuit de commande de moniteur pour la commande d'un moniteur fonctionnant à une seconde fréquence de pixels dont l'affichage peut être généré par la lecture, d'un dispositif de mémoire vidéo (4), d'un signal vidéo numérique du côté sortie à la seconde fréquence de pixels, sur base de tous les mots de données d'un signal vidéo numérique présentant une première fréquence de pixels, le signal vidéo à la première fréquence de pixels n'étant pas synchronisé avec l'affichage d'image au moniteur à la seconde fréquence de pixels, avec:
    un dispositif de mémoire 'fifo' (3),
    un premier dispositif de commande (5) qui introduit dans le dispositif de mémoire 'fifo' (3) chacun des mots de données successifs du signal vidéo numérique du côté entrée à une fréquence fonction de la première fréquence de pixels,
    un second dispositif de commande (6) destiné à commander la lecture du dispositif de mémoire 'fifo' (3) des mots de données du signal vidéo numérique à introduire dans le dispositif de mémoire vidéo (4), lequel interrompt la lecture du dispositif de mémoire 'fifo' (3) pendant la lecture de mots de données du dispositif de mémoire vidéo (4) et interrompt, par ailleurs, la lecture du dispositif de mémoire 'fifo' (3) lors d'un état vide de celui-ci, de sorte que le nombre de mots de données pouvant être transférés du dispositif de mémoire 'fifo' (3) au dispositif de mémoire vidéo (4) varie.
  6. Circuit de commande de moniteur suivant la revendication 5, avec un dispositif de registres (2) relié, du côté de l'entrée, au dispositif de mémoire 'fifo' (3), par lequel les mots de données du signal vidéo numérique reçus à la première fréquence de pixels peuvent être transformés en mots de données à nombre de bits multiple basé sur le nombre de bits des mots de données reçus à la première fréquence de pixels divisée par la pluralité.
  7. Circuit de commande de moniteur suivant la revendication 6, dans lequel le dispositif de registres (2) présente un nombre de premiers registres (36, 37, 38), pour l'enregistrement de chacun des mots de données reçus, inférieur de un par rapport à la pluralité,
    le dispositif de registres (2) présente, par ailleurs, un second registre (39), pour l'enregistrement du mot de données au nombre de bits multiple, qui est raccordé, par une partie de ses entrées, à des sorties des premiers registres (36, 37, 38) et, par une autre partie de ses entrées, à un collecteur (10) pour l'enregistrement de l'un des mots de données reçus, et
    le premier dispositif de commande (5) commande en séquence chacun des premiers registres (36, 37, 38) et le second registre (39) avec un signal de sélection (SEL0, SEL1, SEL2, SEL3) pour la reprise de mots de données présents du côté entrée.
  8. Circuit de commande de moniteur suivant la revendication 7, dans lequel le premier dispositif de commande (5) présente une entrée d'horloge (16), à laquelle peut être amené un signal d'horloge (CLK(1)) de la première fréquence de pixels, et présente une entrée de maintien (17), à laquelle peut être amené un signal de suppression (BL(1)) du premier signal vidéo, et
       le premier dispositif de commande (5) présente un nombre de sorties de sélection (12) correspondant à la pluralité et se présente de telle manière que les signaux de sélection (SEL0, SEL1, SEL2, SEL3) sont, aux sorties de sélection (13), décalés, chacun, d'une première période de pixels l'un par rapport à l'autre.
  9. Circuit de commande de moniteur suivant la revendication 7 ou 8, dans lequel le premier dispositif de commande (5) présente, par ailleurs, une sortie de commande d'écriture pour générer une commande d'écriture (WF) pour le dispositif de mémoire 'fifo' (3), la commande d'écriture (WF) étant décalée, par rapport au signal de sélection (SEL3) pour le second registre (39), d'au moins une première période de pixels, et
       le dispositif de mémoire 'fifo' (3) présente une entrée de commande d'écriture (15) et, lorsqu'une commande d'écrite se présente, enregistre un mot de données présent.
  10. Circuit de commande de moniteur suivant l'une des revendications 5 à 9, avec un dispositif compteur d'affichage (8) auquel peuvent être amenés le premier signal d'horloge (CLK(1)) de la première fréquence de pixels et le premier signal de suppression (BL(1) du premier signal vidéo, le dispositif compteur d'affichage (8) présentant un compteur horizontal (40, 41) pour le comptage des premiers signaux d'horloge (CLK(1) entre deux premiers signaux de suppression (BL(1)).
  11. Circuit de commande de moniteur suivant la revendication 10, dans lequel le dispositif compteur d'affichage (8) présente, par ailleurs, un compteur vertical (42, 43) auquel peuvent être amenés les premiers signaux de suppression (BL(1)) et les premiers signaux de synchronisation verticale (VS(1)) et à l'aide duquel peut être déterminé le nombre de premiers signaux de suppression (BL(1)) entre deux premiers signaux de synchronisation verticale (VS(1)).
  12. Circuit de commande de moniteur suivant l'une des revendications 5 à 11, dans lequel le dispositif de mémoire 'fifo' (3) présente une entrée d'effacement (14) à laquelle est amené le premier signal de synchronisation verticale (VS(1)).
  13. Circuit de commande de moniteur suivant la revendication 12, dans lequel le dispositif de mémoire 'fifo' (3) présente une sortie de drapeau pour un drapeau (EF) indiquant un état libre des zones de mémoire du dispositif de mémoire 'fifo' (3), et
       la sortie de drapeau est reliée à une entrée de drapeau du second dispositif de commande (6).
  14. Circuit de commande de moniteur suivant l'une des revendications 11 à 13, dans lequel le second dispositif de commande (6) présente une sortie de commande de lecture (RF) qui est reliée à une entrée de commande de lecture du dispositif de mémoire 'fifo' et
       le dispositif de mémoire 'fifo' (3) se présente de telle manière qu'il transmet, à chaque impulsion de commande de lecture (RF) à son entrée de commande de lecture, un mot de données destiné à être mémorisé dans le dispositif de mémoire vidéo (4).
  15. Circuit de commande de moniteur suivant l'une des revendications 5 à 14, dans lequel le second dispositif de commande (6) présente une entrée d'effacement à laquelle peut être amené le signal de synchronisation verticale (VS(1)) du premier signal vidéo et
       le second dispositif de commande (6) présente, par ailleurs, une entrée d'horloge, à laquelle est raccordé un oscillateur (7).
  16. Circuit de commande de moniteur suivant l'une des revendications 10 à 15, dans lequel le second dispositif de commande (6) est relié au dispositif compteur d'affichage (8) et reçoit de celui-ci au moins la valeur de comptage (HC) du compteur horizontal (40, 41).
  17. Circuit de commande de moniteur suivant la revendication 15 ou 16, en rapport avec la revendication 14, dans lequel le second dispositif de commande (6) génère, pour la commande du dispositif de mémoire vidéo (4), sur la base de temps de la cadence donnée par l'oscillateur (7), partant d'un état de départ logique lors de la production du premier signal de synchronisation verticale (VS(1)), par temps de lecture, chaque fois une impulsion de commande de lecture (RF) pour le dispositif de mémoire 'fifo' (3), un signal d'adresse horizontale (ADR) et un signal d'adresse verticale (ADR) pour l'adressage du dispositif de mémoire vidéo (4) et des signaux de commande de mémoire vidéo (RAS, CAS, WB/WE, DT/OE).
  18. Circuit de commande de moniteur suivant la revendication 17, dans lequel les signaux de commande de mémoire vidéo comprennent un signal de reprise d'adresse de colonne (CAS), un signal de reprise d'adresse de rangée (RAS), un signal d'écriture (WB/WE) représentant l'état d'écriture pour l'enregistrement dans le dispositif de mémoire vidéo (4) et un signal de reprise de registre variable (DT/OE) qui permet la reprise d'un mot de données du dispositif de mémoire vidéo (4) dans un registre variable de sortie de celui-ci.
  19. Circuit de commande de moniteur suivant la revendication 18, dans lequel le second dispositif de commande (6) génère lesdits signaux de commande pour le dispositif de mémoire vidéo (4) d'une manière, en fonction de la spécification du dispositif de mémoire vidéo (4) utilisé, telle que l'entrée des mots de données fournis par le dispositif de mémoire 'fifo' (3) sur un collecteur de données (20) destiné au racordement du dispositif de mémoire vidéo (4) se fait suivant le type de commande de mémoire apellé "page mode" (mode par pages), dans lequel le signal d'adresse de ligne (ADR) et le signal de reprise d'adresse de ligne (RAS) pour le dispositif de mémoire vidéo (4) restent inchangés pendant la mémorisation de données sur une ligne du dispositif de mémoire vidéo (4).
EP92107715A 1989-05-12 1990-03-21 Méthode et dispositif de commande d'un moniteur Expired - Lifetime EP0500147B2 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE3915562A DE3915562C1 (fr) 1989-05-12 1989-05-12
DE3915562 1989-05-12
EP90904821A EP0468973B2 (fr) 1989-05-12 1990-03-21 Circuit de commande de moniteur

Related Parent Applications (2)

Application Number Title Priority Date Filing Date
EP90904821.7 Division 1990-03-21
EP90904821A Division EP0468973B2 (fr) 1989-05-12 1990-03-21 Circuit de commande de moniteur

Publications (4)

Publication Number Publication Date
EP0500147A2 EP0500147A2 (fr) 1992-08-26
EP0500147A3 EP0500147A3 (en) 1992-10-14
EP0500147B1 EP0500147B1 (fr) 1996-04-24
EP0500147B2 true EP0500147B2 (fr) 2001-08-22

Family

ID=6380538

Family Applications (2)

Application Number Title Priority Date Filing Date
EP92107715A Expired - Lifetime EP0500147B2 (fr) 1989-05-12 1990-03-21 Méthode et dispositif de commande d'un moniteur
EP90904821A Expired - Lifetime EP0468973B2 (fr) 1989-05-12 1990-03-21 Circuit de commande de moniteur

Family Applications After (1)

Application Number Title Priority Date Filing Date
EP90904821A Expired - Lifetime EP0468973B2 (fr) 1989-05-12 1990-03-21 Circuit de commande de moniteur

Country Status (9)

Country Link
US (1) US5329290A (fr)
EP (2) EP0500147B2 (fr)
JP (1) JP2971132B2 (fr)
KR (1) KR960003396B1 (fr)
AT (2) ATE85858T1 (fr)
DE (3) DE3915562C1 (fr)
DK (2) DK0500147T4 (fr)
ES (2) ES2089283T5 (fr)
WO (1) WO1990013886A2 (fr)

Cited By (1)

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CN102129831A (zh) * 2010-01-14 2011-07-20 韩国恩斯特科技有限公司 定时控制器及利用其进行同步控制的装置

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JPH0573208A (ja) * 1991-09-13 1993-03-26 Wacom Co Ltd 制御装置分離型の表示装置付座標検出装置
US5815208A (en) * 1994-12-09 1998-09-29 Methode Electronics, Inc. VGA to NTSC converter and a method for converting VGA image to NTSC images
DE19546841C2 (de) * 1995-12-15 2000-06-15 Sican Gmbh Mehrfachoverlay mit einem Overlaycontroller
US5796391A (en) * 1996-10-24 1998-08-18 Motorola, Inc. Scaleable refresh display controller
TW583639B (en) 2000-03-24 2004-04-11 Benq Corp Display device having automatic calibration function
JP2003195803A (ja) * 2001-12-27 2003-07-09 Nec Corp プラズマディスプレイ
US20040179016A1 (en) * 2003-03-11 2004-09-16 Chris Kiser DRAM controller with fast page mode optimization
ITCO20110001A1 (it) 2011-01-07 2012-07-08 Giacomini Spa "pannello radiante in cartongesso per controsoffitti e controsoffitto prodotto con detti pannelli radianti"
JP6354866B1 (ja) * 2017-01-06 2018-07-11 日立金属株式会社 二次電池の負極集電体用クラッド材およびその製造方法

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GB1568378A (en) * 1976-01-30 1980-05-29 Micro Consultants Ltd Video processing system
US4511965A (en) * 1983-03-21 1985-04-16 Zenith Electronics Corporation Video ram accessing system
US4851834A (en) * 1984-01-19 1989-07-25 Digital Equipment Corp. Multiport memory and source arrangement for pixel information
DE3425636A1 (de) * 1984-07-12 1986-01-16 Olympia Werke Ag, 2940 Wilhelmshaven Verfahren zur ansteuerung einer raster-aufzeichnungseinrichtung
GB8613153D0 (en) * 1986-05-30 1986-07-02 Int Computers Ltd Data display apparatus
US4796203A (en) * 1986-08-26 1989-01-03 Kabushiki Kaisha Toshiba High resolution monitor interface and related interfacing method
FR2608291B1 (fr) * 1986-12-15 1989-04-07 Locatel Procede et circuit d'adaptation de la carte " graphique " d'un ordinateur a un moniteur fonctionnant suivant un standard de balayage different de celui de ladite carte
JPS63282790A (ja) * 1987-02-14 1988-11-18 株式会社リコー 表示制御装置
JPS63255747A (ja) * 1987-04-13 1988-10-24 Mitsubishi Electric Corp 画像メモリ装置

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Publication number Priority date Publication date Assignee Title
CN102129831A (zh) * 2010-01-14 2011-07-20 韩国恩斯特科技有限公司 定时控制器及利用其进行同步控制的装置

Also Published As

Publication number Publication date
EP0500147B1 (fr) 1996-04-24
KR920701936A (ko) 1992-08-12
ATE85858T1 (de) 1993-03-15
EP0500147A2 (fr) 1992-08-26
DK0500147T3 (da) 1996-05-13
DE59000902D1 (en) 1993-03-25
ES2089283T3 (es) 1996-10-01
DE3915562C1 (fr) 1990-10-31
EP0468973A1 (fr) 1992-02-05
DK0468973T3 (da) 1993-05-10
US5329290A (en) 1994-07-12
ATE137352T1 (de) 1996-05-15
EP0468973B1 (fr) 1993-02-17
JPH04507147A (ja) 1992-12-10
EP0468973B2 (fr) 2001-05-09
KR960003396B1 (ko) 1996-03-09
ES2089283T5 (es) 2002-01-16
EP0500147A3 (en) 1992-10-14
WO1990013886A2 (fr) 1990-11-15
ES2038054T3 (es) 1993-07-01
ES2038054T5 (es) 2001-09-16
DK0500147T4 (da) 2001-10-08
DK0468973T4 (da) 2001-07-30
DE59010304D1 (de) 1996-05-30
WO1990013886A3 (fr) 1990-12-27
JP2971132B2 (ja) 1999-11-02

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