EP0468973B2 - Circuit de commande de moniteur - Google Patents

Circuit de commande de moniteur Download PDF

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Publication number
EP0468973B2
EP0468973B2 EP90904821A EP90904821A EP0468973B2 EP 0468973 B2 EP0468973 B2 EP 0468973B2 EP 90904821 A EP90904821 A EP 90904821A EP 90904821 A EP90904821 A EP 90904821A EP 0468973 B2 EP0468973 B2 EP 0468973B2
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EP
European Patent Office
Prior art keywords
storage device
signal
control circuit
video storage
input
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Expired - Lifetime
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EP90904821A
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German (de)
English (en)
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EP0468973B1 (fr
EP0468973A1 (fr
Inventor
Stefan Schwarz
Ian Cartwright
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SPEA SOFTWARE GmbH
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SPEA Software GmbH
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Application filed by SPEA Software GmbH filed Critical SPEA Software GmbH
Priority to EP92107715A priority Critical patent/EP0500147B2/fr
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/395—Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G1/00—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data
    • G09G1/06—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data using single beam tubes, e.g. three-dimensional or perspective representation, rotation or translation of display pattern, hidden lines, shadows
    • G09G1/14—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data using single beam tubes, e.g. three-dimensional or perspective representation, rotation or translation of display pattern, hidden lines, shadows the beam tracing a pattern independent of the information to be displayed, this latter determining the parts of the pattern rendered respectively visible and invisible
    • G09G1/16—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data using single beam tubes, e.g. three-dimensional or perspective representation, rotation or translation of display pattern, hidden lines, shadows the beam tracing a pattern independent of the information to be displayed, this latter determining the parts of the pattern rendered respectively visible and invisible the pattern of rectangular co-ordinates extending over the whole area of the screen, i.e. television type raster
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/393—Arrangements for updating the contents of the bit-mapped memory

Definitions

  • the present invention is concerned with a Monitor control circuit for the control of a a second pixel frequency operating monitor due to a first pixel frequency digital image signal.
  • Computer monitors are known to be in Depends on the requirements regarding the required screen resolution through graphics cards different categories, the themselves through the horizontal and vertical Resolution, i.e. the number of pixels, in horizontal and vertical direction as well as by the pixel frequencies differentiate.
  • Known graphics card standards are for example MDA (320 x 200 pixels, Black and white, at 16 MHz pixel frequency), CGA (320 x 200 pixels, color, at 20 MHz pixel frequency), HERCULES (740 x 400 pixels, black and white, at 27 MHz pixel frequency), EGA (640 x 350 Pixels, color, at 30 MHz pixel frequency), VGA (640 x 480 pixels, color, at 32 MHz pixel frequency), SUPER-EGA (800 x 600 or 1024 x 768 Pixels, color, at 50 MHz pixel frequency, as well recently the so-called HR (High Resolution) graphics systems with 1024 x 768, 1080 x 1024 as well 1600 x 1280 pixels, color, at pixel frequencies between 60 MHz and 170 MHz.
  • DE-A-38 04 460 already discloses a monitor control circuit for controlling one at a second pixel frequency working monitor a digital one having a first pixel frequency Image signal, with a serial-parallel converter on the input side in the form of a shift register, on the Output connected to a video storage device is, in which the input image signal after its Serial-parallel conversion can be filed. Since it is in the memory only by a shift register Serial-parallel conversion is for that purpose the serial-parallel conversion with the clock of the subsystem after the occurrence of the blank signal of the subsystem is clocked input signal at the frequency of its Subsystem clock in the video storage device registered.
  • the raster elements can be controlled in a predetermined sequence and which has an image memory, between a processor and the recording device to arrange a FIFO memory.
  • an interrupt command interrupts the program running in the processor, whereupon new data written into the FIFO memory are, after the processor is filled interrupted program run again.
  • FR-A-2 608 291 is a circuit for Adaptation of a graphics card to a specific one TV standard to a monitor of another television standard known, one by a video processor Data processing carried out periodically generated strobe in relation to the to be omitted or necessary for the conversion inserted picture lines is interrupted. this makes possible no complete update of the monitor image.
  • Monitor control circuit for the control of a a second pixel frequency working monitor due to a first pixel frequency digital image signals according to the generic term of claim 1 by the in the characterizing Part of claim 1 specified features solved
  • the invention is based on the finding that the control of the with the second pixel frequency working monitors with the first pixel frequency is neither synchronized nor usually in is a fixed, even number ratio, by means of of the image signal of the first pixel frequency is then possible is when the data words of the digital image signal initially cached in a FIFO storage device before going into a video storage device to be filed in synchronization with the operation of the monitor at second pixel frequency in a manner known per se can be read out in order to generate the monitor display.
  • FIG. 1 The embodiment of a monitor control device shown in FIG. 1 according to the present invention, those in their entirety with the reference symbol 1, includes a register device 2, one designed as a FIFO storage device first storage device 3, a video storage device 4, a first control device 5, a second control device 6, an oscillator 7, a Display counter device 8 and a serial Readout control device 9.
  • a register device 2 one designed as a FIFO storage device first storage device 3, a video storage device 4, a first control device 5, a second control device 6, an oscillator 7, a Display counter device 8 and a serial Readout control device 9.
  • the register device 2 is on the input side connected to an input data bus 10 on which data words of a digital image signal with the first Pixel frequency are present.
  • the input data bus 10 can for example become a VGA interface extend.
  • the input data bus 10 comprises one connection each for the three basic colors R, G, B and a connector for a brightness bit I.
  • Each Data word represents a pixel with a depth of 4 bits.
  • the register device 2 is also on the input side with a Clock signal input 11 for a clock signal at the first pixel frequency Mistake.
  • the register device 2 receives from of the first control device 5 selection signals SEL0, SEL1, SEL2, SEL3 via a selection data bus 12, which has four bits.
  • the register device is on the output side 2 via a first data bus 13 Inputs of the FIFO memory device 3 in connection, which also has a reset input 14, which a vertical synchronization signal VS (1) of the first Image signal can be fed. Furthermore, the Fifo storage device 3 from the first control device 5 a write command signal at its write input 15 WF fed.
  • the first control device 5 has a clock input 16 for the first clock signal CLK (1), a blank input 17 for the blank signal BL (1) of the first image signal.
  • the FIFO storage device is on the output side 3 via a second data bus 20 with the video storage device 4 in connection.
  • the display counter device 8 has a clock input 21 for the first clock signal CLK (1), one Blank input 22 for the blank signal BL (1) of the first Image signal, a vertical synchronization input 23 for the vertical synchronization signal VS (1) and a horizontal synchronization input 24 for the Horizontal synchronization signal HS (1).
  • the display counter device is on the output side 8 by means of a third data bus 25 for one Horizontal count HC with the second controller 6 as well as with the serial readout control device 9 in connection. Furthermore, the display counter device stands 8 via a fourth data bus 26 for one Vertical count VC with the serial readout controller in connection.
  • the second control device is on the output side 6 with inputs of the video storage device via a control bus 27 and an address bus 28 in Connection.
  • the control bus 27 comprises one line each for a row address takeover signal RAS, a column address takeover signal CAS, a write command signal WB / WE and a data transmission signal DT / OE for the transfer of a data line from the Video storage device 4 into a (not shown) Read shift registers of the same.
  • the serial readout control device 9 stands on the output side via a second control bus 29 for Control signals SC, SOE for reading out the video memory device 4 with control inputs of the latter in connection.
  • the video storage device 4 is in turn on a fifth data bus 30 with a data input of the serial Readout control device 9, which in turn a vertical synchronization input 31 for the vertical synchronization signal VS (2) of the second, monitor-side image signal, a clock input 32 for a second clock signal CLK (2) with the second Pixel frequency, a blank input 33 for the second Blank signal BL (2) and a horizontal synchronization input 34 for the horizontal synchronization signal HS (2) of the second image signal on the monitor side having.
  • the serial readout control device is on the output side 9 via a sixth data bus 35 the digital-to-analog converter DAC of the (not shown) Monitors in connection. Since the structure of the Monitors which correspond to those customary in the prior art, there is no need for their explanation.
  • the register device 2 carries out a serial-parallel conversion of four in a row Data words with the pixel frequency on the input data bus 10, through, the data words generated four times on the output side Number of bits, i.e. data words with a length of 16 Are bits that are given in parallel on the first data bus 13 become.
  • This implementation of 4-bit data words in 16-bit data words takes place under the controller the first control device 5 by means of the selection signals SEL0, ... SEL3, which after completion of this Implementation of the Fifo storage device 3 Write command signal 15 supplies.
  • the second one goes out Control device 6 supplied flag EF over the empty Memory state of the Fifo memory device, whereby the second control device informs about it will that in the Fifo storage device 3 in the video storage device 4 rewritable data words available.
  • the FIFO storage device is 3 constructed such that in this Data words first read when activated by the read command RF first over the second data bus 20 read into the video storage device 4 become.
  • the second control device pro Write cycle of the video storage device 4 or Fifo memory device 3 read cycle a restore a plurality of data words the first storage device 3 into the video storage device 4, the respectively re-stored Data word count, as will be explained, on a case by case basis Case may vary.
  • Control device 6 for the correct storage of the digital image signals in the video storage device information about the number of pixels per line of the image signals present on the input side, which also required by the serial readout control device 9 which is additionally the number of lines of the image of the input signal for the Readout control required.
  • the display counter device 8 in the shown preferred embodiment by Counting the clock signals CLK (1) between two blank signals BL (1) a horizontal count HC (0 ... 9) and by counting the number of blank signals BL (1) between two vertical synchronization signals VS (1) the number of rows by the first Image signal displayed image as a vertical count VC (0 ... 9).
  • the second control device works on one Time base, which is set by the oscillator 7, being the beginning of a cycle by the occurrence of the vertical synchronization signal VS (1) on Reset input is set. That of the second Control device also supplied second (output) blank signal BL (2) is used only for Control refresh of the dynamic video storage device 4 and for controlling the shift register transfer, that is taking over an entire Memory line from the video storage device 4 into the output shift register (not shown) enables and interrupts cycle control for this purpose for controlling the Fifo storage device 3 and the video storage device 4.
  • the control of the video storage device starts addressing the first line and the first column of the video storage device 4 if the flag EF is not present, the address transfer by the row address takeover signal RAS and the column address strobe CAS can be controlled while during write mode the write command signal WB / WE is "low".
  • the takeover of the data words from the FIFO storage device 3 into the video storage device 4 happens in the so-called "page mode", whereby the row addressing and the row address takeover signal RAS while saving Data words in the different columns of this Line remain unchanged, which makes them known per se Way the write speed of the video memory is increased.
  • the exact sequence of individual control signals depends on the manufacturer's specification the video storage device 4 for the at "page mode" write mode provided for these devices. Details of the addressing are under With reference to FIGS. 9 and 10 explained in more detail.
  • Control of serial readout of the video storage device through the serial readout controller 9 takes place in synchronization with the monitor side present second horizontal synchronization signal HS (2), vertical synchronization signal VS (2), clock signal CLK (2) and blank signal BL (2) in one way known per se.
  • the first control device 5 By the first blank signal BL (1) the first control device 5 becomes an initial state set to when a first clock pulse occurs CLK (1) (with circuit-related Delay) to reset a zero selection signal SEL0 and to set a first selection signal SEL1, with the second clock pulse CLK (1) the first Selection signal reset and the second selection signal SEL2 is set, etc., eventually after after the third pulse, the third selection signal SEL3 is reset and the fifo write signal WF is set, whereupon after the fourth clock pulse, the third selection signal reset and the Fifo write signal after the subsequent first bar is reset.
  • This staggered selection signals SELO to SEL3 used to control the register device 2, their detailed structure below with reference 4 is explained in more detail.
  • the register device 2 comprises three 4-bit registers 36, 37, 38 and a 16-bit register 39, all of them with the clock signal input 11 and with the input data bus 10 communicating.
  • the exits the 4-bit registers 36 to 38 are with inputs of the 16-bit register 39.
  • Registers 36 to 39 are in the order of their reference numerals controlled by the selection signals SELO to SEL3, so that control of the 16-bit register 39 by the fourth selection signal SEL3 four 4-bit data words on the input side into a 16-bit data word on the output side are converted.
  • Fig. 5 shows the temporal Relation of the first horizontal synchronization signal HS (1), the first blank signal BL (1) and of the first clock signal CLK (1).
  • the display counter device includes 8 a horizontal counter 40, the Clock input the first clock signal CLK (1) and its Reset input the first horizontal synchronization signal HS (1) are supplied.
  • the first blank signal BL (1) controls the transfer of the meter reading of the horizontal counter 40 in the register 41 for the horizontal count value HC, which on the output side Bus 25 appears.
  • Fig. 7 shows (of course with one opposite Fig. 1 streamlined time base) the schematic temporal relationship between the first Blank signal BL (1), the first horizontal synchronization signal HS (1) and the first vertical synchronization signal VS (1).
  • Fig. 8 shows the vertical counting or line counting relevant portion of the display counter device 8, which comprises a vertical counter 42, whose clock input the first blank signal BL (1) and the reset input of the first vertical synchronization signal VS (1) are supplied, and the on the output side with a register 43 for the vertical count value VC is connected, its clock input again by the first vertical synchronization signal controlled, and the output side with the fourth data bus 26 is connected, on which the Vertical count VC is pending.
  • FIG. 9 shows the structure of the video storage device 4, four in the example shown Storage levels 44 to 47 is divided. This subdivision the video storage device enables one Reduction of the data flow rate when saving and simplified addressing.
  • each of the memory levels 44 to 47 with 512 x 512 storage spaces each of memory levels 44 to 47 at the horizontal address 256 is divided into two.
  • a storage organization results of 1024 x 1024 seats.
  • Horizontal address counter After reaching this Horizontal address is carried out by the (still to be described) Horizontal address counter jumps to the horizontal address 256, at which the storage level is divided is to continue from this horizontal address value divided up to one around the horizontal count HC increased by the number of storage levels Count value before dropping the second line of the first image signal the third line of the first image signal then into the second line of the Video storage device 44 to 47; 4 is filed.
  • the row address counter is incremented after every second reaching the by the number of Memory levels divided horizontal count HC.
  • a block diagram of the second control device is shown in Fig. 10, and includes one Column address counter 48, a row address counter 49 and a control signal generator for generating the Control signals for the video storage device 4.
  • the Column address counter 48 is at its clock input 51 is clocked by the Fifolesesignal RF and is by the first vertical synchronization signal VS (1) reset at its reset input 52 and is further to the third data bus 25 for receiving of the horizontal count value HC connected.
  • the control signal generator 50 receives the clock signal CLK * from the oscillator 7 at its clock input 54, the flag EF from the fifo storage device 3 at its flag input 55, the control signal TC from the column address counter 48 at its control signal input 56 and the secondary-side horizontal synchronization signal HS (2) at its horizontal synchronization input 57 supplied
  • the generation of the row address takeover signal RAS, the column address takeover signal CAS, the data takeover signal DT / OE for the takeover of data from the video memory device in its output shift register and the write signal WB / WE for the video memory device takes place in accordance with the specification of the video memory device used in each case for its operation in the "page-mode" write mode.
  • the readout signal RF can be generated by ANDing the column address takeover signal CAS and the second horizontal synchronization signal HS (2) by means of a gate 58.
  • a register device is used to register the data words present on the input side with the first Pixel frequency in data words of multiple Bit length for a first divided by the plurality Generate pixel frequency, reducing the requirements to the speed of injection into the Fifo storage device can be lowered.
  • the input register device will then unnecessary if the first image signal has a corresponding one has low data word rate or if one Fifo storage device with a correspondingly high Working speed is used. In this In this case, the first control device is also unnecessary.
  • the storage into the video storage device each starting from a horizontal address 0 and one Vertical address 0, i.e. starting from the left upper corner of the video storage device.
  • the subject matter of the invention is not restricted to a certain number of bits of the data words of the processed image signal and is also on Black and white image signals can be used like color image signals. If, for example, a variety of colors from 256 colors is desired, what input data words of 8 bits corresponds to two circuits 1 are connected in parallel.
  • the monitor control circuit serves essentially for control of a monitor whose pixel frequency is different is that of the digital to be displayed on it Image signal.
  • first Pixel frequency of the image signal and the concept of "Second pixel frequency” of the monitor understood so broadly be that including frequency same or similar signals with different Phase or synchronization fall.
  • the invention does not necessarily work with a FIFO memory, but includes first Storage device all such memories from which first stored data or data groups are readable again first, with the alternative of the data groups is irrelevant in which Order the data within the data groups be read out.

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Claims (17)

  1. Circuit de commande de moniteur pour la commande d'un moniteur affichant une image de moniteur d'un signal vidéo à une seconde fréquence de pixels sur base d'un signal vidéo numérique présentant une première fréquence de pixels,
    dans lequel le signal vidéo à la première fréquence de pixels est amené à une entrée du circuit de commande de moniteur, et
    dans lequel le signal vidéo à la première fréquence de pixels n'est pas synchronisé avec l'affichage d'image de moniteur à la seconde fréquence de pixels,
    avec un dispositif de mémoire 'fifo' (3),
    avec un premier dispositif de commande (5) qui entre dans le dispositif de mémoire 'fifo' (3) le signal vidéo présent à l'entrée du circuit de commande de moniteur avec une fréquence dépendant de la première fréquence de pixels,
    avec un dispositif de mémoire vidéo (4) raccordé à la sortie du dispositif de mémoire 'fifo' (3), et
    avec un second dispositif de commande (6) qui est relié au dispositif de mémoire vidéo (4) et au dispositif de mémoire 'fifo' (3) et qui lit des mots de données du signal vidéo numérique du dispositif de mémoire 'fifo' (3) et les entre dans le dispositif de mémoire vidéo (4) de telle sorte que la lecture du dispositif de mémoire 'fifo' (3) est interrompue pendant la lecture de mots de données du dispositif de mémoire vidéo (4) et que la lecture du dispositif de mémoire 'fifo' (3) est, par ailleurs, interrompue lors de la génération d'un signal (EF) indiquant l'état vide de celui-ci,
    la lecture de mots de données du signal vidéo du dispositif de mémoire 'fifo' (3) étant effectuée par le second dispositif de commande (6) sur base d'une impulsion d'horloge interne (CLK*) du circuit de commande de moniteur,
    de sorte que le nombre de mots de données pouvant être mémorisés du dispositif de mémoire 'fifo' (3) dans le dispositif de mémoire vidéo (4) varie.
  2. Circuit de commande de moniteur suivant la revendication 1, caractérisé par un dispositif de registres (2) relié, du côté de l'entrée, au dispositif de mémoire 'fifo' (3), par lequel les mots de données du signal vidéo numérique reçus à la seconde fréquence de pixels peuvent être transformés en mots de données à nombre de bits multiple basé sur le nombre de bits des mots de données reçus à une première fréquence de pixels divisée par la pluralité.
  3. Circuit de commande de moniteur suivant la revendication 2, caractérisé en ce que le dispositif de registres (2) présente un nombre de premiers registres (36, 37, 38), pour l'enregistrement de chacun des mots de données reçus, inférieur de un par rapport à la pluralité, que le dispositif de registres (2) présente, par ailleurs, un second registre (39), pour l'enregistrement du mot de données au nombre de bits multiple, qui est raccordé, par une partie de ses entrées, à des sorties des premiers registres (36, 37, 38) et, par une autre partie de ses entrées, à un collecteur (10) pour l'enregistrement de l'un des mots de données reçus, et que le premier dispositif de commande (5) commande en séquence chacun des premiers registres (36, 37, 38) et le second registre (39) avec un signal de sélection (SEL0, SEL1, SEL2, SEL3) pour la reprise de mots de données présents du côté entrée.
  4. Circuit de commande de moniteur suivant la revendication 3, caractérisé en ce que le premier dispositif de commande (5) présente une entrée d'horloge (16), à laquelle peut être amené un signal d'horloge (CLK)) de la première fréquence de pixels, et présente une entrée de maintien (17), à laquelle peut être amenée un signal de suppression (BL(1)) du premier signal vidéo, et que le premier dispositif de commande (5) présente un nombre de sorties de sélection (12) correspondant à la pluralité et se présente de telle manière que les signaux de sélection (SEL0, SEL1, SEL2, SEL3) sont, aux sorties de sélection (13), chaque fois décalés d'une première période de pixels l'un par rapport à l'autre.
  5. Circuit de commande de moniteur suivant la revendication 3 ou 4, caractérisé en ce que le premier dispositif de commande (5) présente, en outre, une sortie de commande d'écriture pour engendrer une commande d'écriture (WF) pour le dispositif de mémoire 'fifo' (3), la commande d'écriture (WF) étant décalée, par rapport au signal de sélection (SEL3) pour le second registre (39), d'au moins une première période de pixels, et que le dispositif de mémoire 'fifo' (3) présente une entrée pour commande d'écriture (15) et, lorsqu'une commande d'écrite se présente, enregistre un mot de données présent.
  6. Circuit de commande de moniteur suivant l'une des revendications 1 à 5, caractérisé par un dispositif compteur d'affichage (8) auquel peuvent être amenés le premier signal d'horloge (CLK(1)) de la première fréquence de pixels et le premier signal de suppression (BL(1) du premier signal vidéo, le dispositif compteur d'affichage (8) présentant un compteur horizontal (40, 41) pour le comptage des premiers signaux d'horloge (CLK(1) entre deux premiers signaux de suppression (BL(1)).
  7. Circuit de commande de moniteur suivant la revendication 6, caractérisé en ce que le dispositif compteur d'affichage (8) présente, en outre, un compteur vertical (42, 43) auquel peuvent être amenés les premiers signaux de suppression (BL(1)) et les premiers signaux de synchronisation verticale (VS(1)) et à l'aide duquel peut être déterminé le nombre de premiers signaux de suppression (BL(1)) entre deux premiers signaux de synchronisation verticale (VS(1)).
  8. Circuit de commande de moniteur suivant l'une des revendications 1 à 7, caractérisé en ce que le dispositif de mémoire 'fifo' (3) présente une entrée de temporisation à laquelle peut être amené le premier signal de synchronisation verticale (VS(1)).
  9. Circuit de commande de moniteur suivant la revendication 8, caractérisé en ce que le dispositif de mémoire 'fifo' (3) présente une sortie de drapeau pour un drapeau (EF) indiquant un état libre des zones de mémoire du dispositif de mémoire 'fifo' (3), et que la sortie de drapeau est reliée à une entrée de drapeau du second dispositif de commande (6).
  10. Circuit de commande de moniteur suivant l'une des revendications 7 à 9, caractérisé en ce que le second dispositif de commande (6) présente une sortie de commande de lecture (RF) qui est reliée à une entrée de commande de lecture du dispositif de mémoire 'fifo' et que le dispositif de mémoire 'fifo' (3) se présente de telle manière qu'il transmet, à chaque impulsion de commande de lecture (RF) à son entrée de commande de lecture, un mot de données au dispositif de mémoire vidéo (4).
  11. Circuit de commande de moniteur suivant l'une des revendications 1 à 10, caractérisé en ce que le second dispositif de commande (6) présente une entrée de temporisation à laquelle peut être amené le signal de synchronisation verticale (VS(1)) du premier signal vidéo et que le second dispositif de commande (6) présente, en outre, une entrée d'horloge, à laquelle est raccordé un oscillateur (7).
  12. Circuit de commande de moniteur suivant l'une des revendications 6 à 11, caractérisé en ce que le second dispositif de commande (6) est relié au dispositif compteur d'affichage (8) et reçoit de celui-ci au moins la valeur de comptage (HC) du compteur horizontal (40, 41).
  13. Circuit de commande de moniteur suivant la revendication 11 ou 12, en rapport avec la revendication 10, caractérisé en ce que le second dispositif de commande (6) engendre, pour la commande du dispositif de mémoire vidéo (4), sur la base temporelle du temps donné par l'oscillateur (7), partant d'un état de départ logique lors de la production du premier signal de synchronisation verticale (VS(1)), par temps de lecture, chaque fois une impulsion de commande de lecture (RF) pour le dispositif de mémoire 'fifo' (3). un signal d'adresse horizontale (ADR) pour l'adressage du dispositif de mémoire vidéo (4) et des signaux de commande de mémoire vidéo (RAS, CAS, WB/WE, DT/OE).
  14. Circuit de commande de moniteur suivant la revendication 13, caractérisé en ce que le dispositif de mémoire vidéo (4) présente un registre variable de sortie et que les signaux de commande de mémoire vidéo comprennent un signal de reprise d'adresse de colonne (CAS), un signal de reprise d'adresse de ligne (RAS), un signal d'écriture (WB/WE) représentant l'entrée dans le dispositif de mémoire vidéo et un signal de reprise de registre variable (DT/OE) qui permet la reprise d'un mot de données du dispositif de mémoire vidéo (4) dans le registre variable de sortie.
  15. Circuit de commande de moniteur suivant la revendication 14, caractérisé en ce que le second dispositif de commande (6) engendre lesdits signaux de commande pour le dispositif de mémoire vidéo (4) d'une manière, en fonction de la spécification du dispositif de mémoire vidéo (4), telle que l'entrée des mots de données fournis par le dispositif de mémoire 'fifo' (3) dans le dispositif de mémoire vidéo (4) se fait suivant le type de commande de mémoire apellé "page mode" (mode par pages), dans lequel le signal d'adresse de ligne (ADR) et le signal de reprise d'adresse de ligne (RAS) pour le dispositif de mémoire vidéo (4) restent inchangés pendant la mémorisation de données sur une ligne du dispositif de mémoire vidéo (4).
  16. Circuit de commande de moniteur suivant l'une des revendications 1 à 15, caractérisé en ce que le dispositif de mémoire vidéo (4) est subdivisé en plusieurs plans de mémoire (44 à 47) pouvant, chacun, être simultanément adressés horizontalement et verticalement et pouvant être occupés en écriture ou lus simultanément.
  17. Circuit de commande de moniteur suivant l'une des revendications 1 à 16, caractérisé en ce que le dispositif de mémoire vidéo (4) est divisé, à au moins une adresse horizontale (256), en au moins une première et une seconde zone de mémoire (0 à 255, 256 à 512), que le second dispositif de commande (6) se présente de telle manière qu'il compte tout d'abord l'adresse horizontale, de manière croissante de zéro à la valeur de comptage (HC) du compteur horizontal (40, 41), et, ensuite, après un saut, en continuant à partir de l'adresse horizontale (256) établissant la division horizontale du dispositif de mémoire vidéo (4, 44 à 47), de manière croissante jusau'à l'adresse de division horizontale (256) augmentée de la valeur de comptage (HC) du compteur horizontal (30, 41), et que l'adresse horizontale, qui est engendrée par le second dispositif de commande (6), est retardée par le premier signal de synchronisation verticale (VS(1)).
EP90904821A 1989-05-12 1990-03-21 Circuit de commande de moniteur Expired - Lifetime EP0468973B2 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP92107715A EP0500147B2 (fr) 1989-05-12 1990-03-21 Méthode et dispositif de commande d'un moniteur

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE3915562 1989-05-12
DE3915562A DE3915562C1 (fr) 1989-05-12 1989-05-12
PCT/EP1990/000466 WO1990013886A2 (fr) 1989-05-12 1990-03-21 Circuit de commande de moniteur

Related Child Applications (2)

Application Number Title Priority Date Filing Date
EP92107715A Division EP0500147B2 (fr) 1989-05-12 1990-03-21 Méthode et dispositif de commande d'un moniteur
EP92107715.2 Division-Into 1992-05-07

Publications (3)

Publication Number Publication Date
EP0468973A1 EP0468973A1 (fr) 1992-02-05
EP0468973B1 EP0468973B1 (fr) 1993-02-17
EP0468973B2 true EP0468973B2 (fr) 2001-05-09

Family

ID=6380538

Family Applications (2)

Application Number Title Priority Date Filing Date
EP90904821A Expired - Lifetime EP0468973B2 (fr) 1989-05-12 1990-03-21 Circuit de commande de moniteur
EP92107715A Expired - Lifetime EP0500147B2 (fr) 1989-05-12 1990-03-21 Méthode et dispositif de commande d'un moniteur

Family Applications After (1)

Application Number Title Priority Date Filing Date
EP92107715A Expired - Lifetime EP0500147B2 (fr) 1989-05-12 1990-03-21 Méthode et dispositif de commande d'un moniteur

Country Status (9)

Country Link
US (1) US5329290A (fr)
EP (2) EP0468973B2 (fr)
JP (1) JP2971132B2 (fr)
KR (1) KR960003396B1 (fr)
AT (2) ATE137352T1 (fr)
DE (3) DE3915562C1 (fr)
DK (2) DK0468973T4 (fr)
ES (2) ES2038054T5 (fr)
WO (1) WO1990013886A2 (fr)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0573208A (ja) * 1991-09-13 1993-03-26 Wacom Co Ltd 制御装置分離型の表示装置付座標検出装置
US5815208A (en) * 1994-12-09 1998-09-29 Methode Electronics, Inc. VGA to NTSC converter and a method for converting VGA image to NTSC images
DE19546841C2 (de) * 1995-12-15 2000-06-15 Sican Gmbh Mehrfachoverlay mit einem Overlaycontroller
US5796391A (en) * 1996-10-24 1998-08-18 Motorola, Inc. Scaleable refresh display controller
TW583639B (en) 2000-03-24 2004-04-11 Benq Corp Display device having automatic calibration function
JP2003195803A (ja) * 2001-12-27 2003-07-09 Nec Corp プラズマディスプレイ
US20040179016A1 (en) * 2003-03-11 2004-09-16 Chris Kiser DRAM controller with fast page mode optimization
KR20110083409A (ko) * 2010-01-14 2011-07-20 (주)엠씨테크놀로지 타이밍 제어기, 이를 이용하여 동기를 제어하는 장치
ITCO20110001A1 (it) 2011-01-07 2012-07-08 Giacomini Spa "pannello radiante in cartongesso per controsoffitti e controsoffitto prodotto con detti pannelli radianti"
JP6354866B1 (ja) * 2017-01-06 2018-07-11 日立金属株式会社 二次電池の負極集電体用クラッド材およびその製造方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1568378A (en) * 1976-01-30 1980-05-29 Micro Consultants Ltd Video processing system
US4511965A (en) * 1983-03-21 1985-04-16 Zenith Electronics Corporation Video ram accessing system
US4851834A (en) * 1984-01-19 1989-07-25 Digital Equipment Corp. Multiport memory and source arrangement for pixel information
DE3425636A1 (de) * 1984-07-12 1986-01-16 Olympia Werke Ag, 2940 Wilhelmshaven Verfahren zur ansteuerung einer raster-aufzeichnungseinrichtung
GB8613153D0 (en) * 1986-05-30 1986-07-02 Int Computers Ltd Data display apparatus
US4796203A (en) * 1986-08-26 1989-01-03 Kabushiki Kaisha Toshiba High resolution monitor interface and related interfacing method
FR2608291B1 (fr) * 1986-12-15 1989-04-07 Locatel Procede et circuit d'adaptation de la carte " graphique " d'un ordinateur a un moniteur fonctionnant suivant un standard de balayage different de celui de ladite carte
JPS63282790A (ja) * 1987-02-14 1988-11-18 株式会社リコー 表示制御装置
JPS63255747A (ja) * 1987-04-13 1988-10-24 Mitsubishi Electric Corp 画像メモリ装置

Also Published As

Publication number Publication date
DK0468973T4 (da) 2001-07-30
DK0500147T3 (da) 1996-05-13
JPH04507147A (ja) 1992-12-10
US5329290A (en) 1994-07-12
EP0500147B2 (fr) 2001-08-22
WO1990013886A3 (fr) 1990-12-27
DE3915562C1 (fr) 1990-10-31
EP0468973B1 (fr) 1993-02-17
DE59000902D1 (en) 1993-03-25
JP2971132B2 (ja) 1999-11-02
DK0468973T3 (da) 1993-05-10
ES2089283T3 (es) 1996-10-01
ES2038054T5 (es) 2001-09-16
ATE137352T1 (de) 1996-05-15
KR920701936A (ko) 1992-08-12
ATE85858T1 (de) 1993-03-15
ES2089283T5 (es) 2002-01-16
ES2038054T3 (es) 1993-07-01
EP0500147B1 (fr) 1996-04-24
KR960003396B1 (ko) 1996-03-09
EP0500147A2 (fr) 1992-08-26
DK0500147T4 (da) 2001-10-08
WO1990013886A2 (fr) 1990-11-15
EP0500147A3 (en) 1992-10-14
DE59010304D1 (de) 1996-05-30
EP0468973A1 (fr) 1992-02-05

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