JPS6460894A - Non-volatile semiconductor memory device - Google Patents

Non-volatile semiconductor memory device

Info

Publication number
JPS6460894A
JPS6460894A JP21751287A JP21751287A JPS6460894A JP S6460894 A JPS6460894 A JP S6460894A JP 21751287 A JP21751287 A JP 21751287A JP 21751287 A JP21751287 A JP 21751287A JP S6460894 A JPS6460894 A JP S6460894A
Authority
JP
Japan
Prior art keywords
bits
data
latched
memory cell
latch means
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP21751287A
Other languages
Japanese (ja)
Inventor
Takashi Hasegawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP21751287A priority Critical patent/JPS6460894A/en
Publication of JPS6460894A publication Critical patent/JPS6460894A/en
Pending legal-status Critical Current

Links

Landscapes

  • Read Only Memory (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Memory System (AREA)

Abstract

PURPOSE:To reduce the number of steps of programming at the time of reading and writing the content of a memory, by performing read/write in the inside of an EEPROM by a large number of bits, and performing the interface with the outside of the EEPROM by a few number of bits. CONSTITUTION:In a readout mode, data of N bits from a memory cell 2 is latched by latch means 4 and 5, and the data is taken out in a unit of M bits to an external bus 17. Meanwhile, in a write mode, the data of M bits desired to be written is fetched from the bus after the data of N bits from the memory cell 2 is latched by the latch means 4 and 5, and latched contents in areas of M bits in the latch means 4 and 5 are updated, and are written on the memory cell 2 in a unit of N bits. In such a way, it possible to reduce the number of steps of programming at the time of reading and writing the content of the memory.
JP21751287A 1987-08-31 1987-08-31 Non-volatile semiconductor memory device Pending JPS6460894A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21751287A JPS6460894A (en) 1987-08-31 1987-08-31 Non-volatile semiconductor memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21751287A JPS6460894A (en) 1987-08-31 1987-08-31 Non-volatile semiconductor memory device

Publications (1)

Publication Number Publication Date
JPS6460894A true JPS6460894A (en) 1989-03-07

Family

ID=16705391

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21751287A Pending JPS6460894A (en) 1987-08-31 1987-08-31 Non-volatile semiconductor memory device

Country Status (1)

Country Link
JP (1) JPS6460894A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5685130A (en) * 1979-12-12 1981-07-11 Mitsubishi Electric Corp Rom access circuit
JPS6222297A (en) * 1985-07-22 1987-01-30 Mitsubishi Electric Corp Semiconductor memory device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5685130A (en) * 1979-12-12 1981-07-11 Mitsubishi Electric Corp Rom access circuit
JPS6222297A (en) * 1985-07-22 1987-01-30 Mitsubishi Electric Corp Semiconductor memory device

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