JPH0812753B2 - Dynamic memory - Google Patents

Description

Description: TECHNICAL FIELD OF THE INVENTION The present invention relates to a semiconductor memory, and more particularly to a serial access memory that is a dynamic memory used for an image memory or the like and is serially accessible.

[Technical background of the invention]

For large-capacity memory, it is important to shorten the access time, but there is a strong demand for high-speed data transfer, and the access order does not have to be random for image memory, computer system main memory, etc. , Often serial. In order to meet this demand, it has been put into practical use that a dynamic memory is used in a nibble mode. Figure 3 shows the conventional dynamic random access memory with nibble mode (RA
M) shows a part. That is, A _in is an address signal input, A _ir is a row address signal, A _ic is a column address signal, 1 is a memory cell array, 2 is a row decoder, 3 is a row address buffer, 4 is a sense amplifier, 5 is a column decoder, and 6 Is a column address buffer. Reference numeral 7 denotes a 4-bit shift register for temporarily storing read data read from the sense amplifier 4 in 4-bit parallel and transferring the read data serially to the output buffer 8. It has a function that can be preset by the preset control input. Column address strobe signals ▲ ▼ and 9 are external inputs, respectively.
A ▲ ▼ system timing generation circuit and a ▲ ▼ system timing generation circuit which receive a row address strobe signal ▲ ▼ and generate timing signals for the ▲ ▼ system and ▲ ▼ system of the memory circuit.

FIG. 4 shows the timing of the nibble mode operation of the above memory, and the nibble mode operation will be briefly described below. When the signal () falls, the row address signal A _ir is _fetched by the row decoder 2 and access is started, and one row of data is read from the memory cell array 1 and latched by the sense amplifier 4. Next, the signal ▲
The column address signal A _ic is taken in by the column decoder 5 due to the fall of ▼, and the sense amplifier 4 includes the sense amplifier 4 of the column designated by the column address signal.
4-bit data is transferred from each of the sense amplifiers to the shift register 7, and 1 bit of the address designated by the column address signal A _ic among the 4-bit data is transferred to the output buffer 8 and becomes output data Dout. The 4-bit data is bit data DA _{ic + j} (j = 0 to 3) of a predetermined combination including bit data DA _ic of an address specified by the column address signal A _ic ,
For example, 512 bits in row x 512 bits in column, 256K x 1
In the case of the bit memory is row address signal A 9 bit A _ir and column address signals A 9 bit A _9c is different 4-bit data _ic of _ir. Next, when the signal ▲ ▼ rises and falls again, 1-bit data of the untransferred data stored in the shift register 7 is transferred to the output buffer 8 and becomes the output data Dout. Similarly, every time the signal ▲ ▼ falls, the shift register 7
The untransferred data stored in is transferred bit by bit and output. The transfer order of the 4-bit data DA _{ic + j} thus transferred may be set as DA _ic , DA _{ic + 1} , DA _{ic + 2} , DA _{ic + 3} as shown in FIG. 4, for example. , DA _ic , DA _{ic + 1} , DA _{ic + 2} , DA _ic-1 are set, and are set according to the preset input.

Therefore, according to the above nibble mode operation, the signal ▲
The access time for the first drop of signal ▲ ▼ after the drop of ▼ is the same as the access time for normal memory operation, but the access time for the second and subsequent drops of signal ▲ ▼ is less than the access time for normal memory operation. Is greatly shortened. This is
This is because it is a serial access in which the access sequence for each drop of the signal (2) after the second time is fixed and the output data can be prepared in advance.

[Problems of background technology]

By the way, in the above-mentioned conventional dynamic memory with nibble mode, since only 4-bit data can be serially read for one access by the signal ▲, the average data is considered when the cycle of the signal ▲ is taken into consideration. The transfer speed is not so high. Therefore, it is conceivable to increase the number of bits in the shift register to 8,16, ... so as to read a larger number of bits of data for one access of ▲ ▼, but this is enough. The data transfer speed cannot be obtained.
Furthermore, in order to speed up data transfer, all the data specified by one row address (for example, 64K × 1 bit RAM has 256 bits, and 256K × 1 bit
256 to read (which is 512 bits in RAM)
It is conceivable to provide a shift register of 1-bit or 512-bit, but this is unrealistic because the chip area increases significantly.

[Object of the Invention]

The present invention has been made in view of the above circumstances and is a dynamic memory capable of serially outputting or inputting all data corresponding to one row address at high speed and suppressing an increase in chip occupied area. Is provided.

[Outline of Invention]

That is, in the dynamic memory of the present invention, the external input column address is fetched and 2 ⁿ (n = 1, 2, ...) leave presetting the external input column address to the preset function counter causes the output or input of the bit data performed via the shift register of 2 ⁿ bits, the ▲ ▼ the every 2 ⁿ periods of the signal By incrementing the counter, the internal column address obtained by the counter is fetched in the second and subsequent serial access operations, and the contents of the shift register are updated to output or input 2 ^n- bit data. All data corresponding to the row address should be serially output or input. It is an butterfly.

Therefore, the data transfer rate is determined by the shift register and remains high, and the increase in the chip occupation area due to the addition of a counter is small, and all the data corresponding to one row address can be output or input serially. it can.

Example of Invention

An embodiment of the present invention will be described in detail below with reference to the drawings.

The dynamic memory shown in FIG. 1 is different from the dynamic memory described above with reference to FIG. 3 in that a counter circuit 11, a column address multiplexer circuit 12, and a transfer gate circuit 13 are added, and the others are the same. Therefore, the same reference numerals as in FIG. 3 are given and the description thereof is omitted.

The counter circuit 11 receives the column address signal A _ic from the column address buffer 6 and presets it, and four clock signals generated at the falling timing of the signal ▲ ▼ from the ▲ ▼ system timing generation circuit 9. It consists of a 2-bit down counter 15 that performs an up operation every 4 cycles of the signal {circle around (5)} to advance the binary counter 14. The column address multiplexer 12 receives the column address signal A _ic from the column address buffer 6 and supplies it to the column decoder 5, and then receives the up output CT of the 2-bit down counter 15 to receive the column address signal from the binary counter 14. (A _ic
+ 4n) is supplied to the column decoder 5. The transfer gate circuit 13 outputs 4-bit parallel data read from the sense amplifier 4 based on a timing signal supplied from the timing generator circuit 9 at a predetermined timing (for example, t _{1 in} FIG. 2). The data is transferred to the bit shift register 7.

Next, the serial access operation of the memory will be described with reference to FIG. The signal ▲ ▼ falls, the row address signal A _ir is taken into the row decoder 2, one row of memory cells is selected, and the data is latched by the sense amplifier 4. Next, the signal ▲ ▼ falls, the column address signal A _ic is taken into the column decoder 5 through the multiplexer 12, and the four sense amplifiers 4 including the sense amplifier of the column designated by the column address signal are sensed. An amplifier is selected, the 4-bit data from this sense amplifier is transferred to the 4-bit shift register 7 via the transfer gate circuit 13, and 1 bit of the address designated by the column address signal in this 4-bit data is output buffer. 8 to be output data Dout. In this case, the column address signal A _ic from the column address buffer 6
Is taken into the column decoder 5 and is taken into the binary counter 14 for presetting. Next, when the signal ▲ ▼ rises, the 2-bit down counter 15
Output becomes “H” (high) level, and this up output CT
Causes the binary counter 14 to operate up, and the column address signal A _ic is incremented to generate a new internal column address signal (A _ic
+4) is obtained. Next, when the signal ▲ ▼ falls, one bit of the untransferred data stored in the shift register 7 is transferred to the output buffer 8 and becomes the output data Dout. In parallel with this operation, the column address signal (A _ic +4) from the binary counter 14 is taken into the column decoder 5 via the multiplexer 12 and includes the sense amplifier of the column designated by the new column address signal. The individual sense amplifiers are selected, and the read operation of 4-bit data from these sense amplifiers is started.

Similarly, the untransferred data stored in the shift register 7 is output bit by bit every time the signal ∇ falls. In this case, the transfer order of the 4-bit data in the shift register 7 is high according to the preset order. Then, every time transfer of 4-bit data in the shift register 7 is completed, the contents of the shift register 7 are changed to the old data (column address signal A _ic).
New data (column address signal A _ic +4)
2), the transfer gate circuit 13 is opened at the timing of t ₁ shown in FIG. 2, and 4-bit read data from the sense amplifier 4 is stored in the shift register 7. Signal like this
Data of 1 bit is output from the shift register 7 every cycle of ▼, and the column address inside the memory is stepped up by the binary counter 14 every four cycles of the signal ▲ ▼, and A _ic + 4n (n = 1, 2, ...), the contents of the shift register 7 are updated every time the column address is updated, so that all the data corresponding to one row address are obtained as the output data Dout in the order shown in FIG. 2, for example. .
Here, the output data _{DA ic, DA ic + 1,} DA ic + 2, DA ic + 3 is a set of 4-bit data read out at the time of the column address signal A _ics, subsequently the column address signal A _ics DA _{ic + 4} , DA _{ic + 5} , a set of 4-bit data read when ₊₄ ,
It is represented by DA _{ic + 6} and DA _{ic + 7} .

Although the above embodiment has described the data read operation, the same column address access control as in the read operation is performed for the data write operation. That is, 1 of the external input signal (▲ ▼ in the above example)
Data is output (read operation) or input (write operation) via the shift register every cycle.

Moreover, it is not limited to the 4-bit shift register
²ⁿ bits (n = 1,2, ...) Shift register may be used as in the case of bits, ... In this case, an external input signal (in the above example, ▲
The counter circuit may be operated every 2 ⁿ cycles of ▼) to update the contents of the shift register.

[Effects of the Invention] As described above, according to the dynamic memory of the present invention, all the data in the memory cells corresponding to one row address can be regenerated a predetermined number of times within one cycle. It is possible to serially input or output by repeating. Therefore, ▲ ▼
It is possible to realize a serial access memory in which the average data transfer rate considering the cycle is remarkably improved. Moreover, as compared with the conventional memory, only a counter circuit, a column address multiplexer circuit and the like need to be added, and only a tedious increase in the chip area is required.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of a dynamic memory according to the present invention, FIG. 2 is a timing diagram shown for explaining a serial access operation of the memory shown in FIG. Three
FIG. 4 is a block diagram showing a part of a conventional dynamic memory with nibble mode, and FIG. 4 is a timing diagram shown for explaining the nibble mode operation of the memory of FIG. 1 ... Memory cell array, 4 ... Sense amplifier, 6 ... Column address buffer, 7 ... Shift register, 11 ... Counter circuit, 12 ... Multiplexer, 13 ... Transfer gate circuit, 14 ... Binary counter, 15 ... 2-bit down counter.

Claims (1)

[Claims] 1. A memory cell array, a row decoder for selecting a plurality of memory cells in one row of the memory cell array based on a row address signal Air, and a memory cell connected to each of the plurality of memory cells in the one row, Multiple sense amplifiers that latch read data or write data, and 2 ⁿ (n = 1,2, ...) Of external input signals that specify column selection operation
A first counter that outputs an output signal CT every cycle and a column address signal Aic are preset and
Second counter that advances the column address signal Aic by 2 ⁿ each time it receives the output signal CT of the counter, and the second counter that outputs the column address signal Aic and receives the output signal CT. A multiplexer for outputting the column address signal set to the column address column, and a column decoder for selecting 2 ⁿ sense amplifiers including a sense amplifier for one column selected by the column address signal output from the multiplexer; ^It is connected to ⁿ sense amplifiers, stores 2 ⁿ bits of data, and is an external input signal that defines the column selection operation.
And a shift register for outputting 1 bit of the 2 ^n- bit data for each cycle.