JPS63239676A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To stabilize serial data transferring operation by specifying the number of cycles of a clock signal up to the start of the transfer operation after starting the data transfer cycle to determined timing for starting the transfer operation of reading data to a data register. CONSTITUTION:The number of cycles of a serial clock signal SC from the start of the data transfer operation of reading data after starting a dual port memory is specified by binary display. These cycles are supplied to correspond ing bits of a counter circuit CTR in a timing control circuit TC as internal data io1-io4. The counter circuit CTR can optionally specify a clock signal position for starting the transfer operation in accordance with its count value and a counting-down counter circuit CTR built in the dual port memory can execute transfer operation synchronized with a clock signal. Consequently, the transfer operation of display data can be stabilized.

Description

[Detailed Description of the Invention] [Field of Industrial Application] This invention relates to a semiconductor memory device, for example,
The present invention relates to a technique that is particularly effective when used in dual port memory for image processing, which has both random input and output functions and serial input and output functions.

[Conventional technology]

Regarding the image frame buffer 7 memory for displaying characters or figures on the screen of a CRT (cathode ray tube), for example, see "Nikkei Electronics J," pages 243 to 264, published by Nikkei McGraw-Hill, March 24, 1986.
It is written on the page.

The dual port memory described above has a random access port for inputting/outputting stored data in units of one bit or several bits, and a random access port for serially inputting/outputting stored data in units of word lines of the memory array. A serial access boat is provided for the

[Problem that the invention seeks to solve]

As shown in FIG. 4, in such a dual port memory, in addition to a row address strobe signal RAS, a column address strobe signal ζX1, and a write enable signal -Wl, as control signals supplied from the outside, for example, A data transfer control signal (1), a serial output control signal (3), and a serial clock signal (SC) are provided. In the read data transfer mode in which a serial output operation of read data is performed in a dual port memory, when the row address strobe signal RAS changes from high level to low level, the column address strobe signal TES] and the write enable signal w are is at a high level, and the data transfer control signal /σ is at a low level. At this time, the address AX of the word line to be read in synchronization with the fall of the row address strobe signal RAS is set to the external terminal AO~
A read signal from a memory cell coupled to the selected word line is established on the corresponding data line. In addition, the first column address AY, which is serially output in synchronization with the fall of the column address strobe signal CAS, which is set to low level with a slight delay after the row address strobe signal "τ", is supplied to external terminals AO to Ai. Thereafter, data is transferred. By returning the control signal DT10E to high level, the timing signal φdt for transferring the read data output in parallel to each data line to the data register of the serial access boat is formed, and the serial clock signal SC The new serial data ((AX-AY
) and subsequent data) starts to be output.

The timing at which the data transfer control signal ■/σ1'' is set to low level and then returned to high level to start serial output operation is determined by the horizontal pixel position provided in the external memory control circuit that drives this dual port memory. It is controlled by monitoring the output signal of a counter circuit for counting, i.e., when the memory cells coupled to one word line of the dual port memory are nearing the end of outputting the read data, the dual port memory is The port memory is restarted, and the read data of the memory cell of the new word line is output to the corresponding data line.

Thereafter, the count value of the counter circuit of the memory control circuit becomes a value indicating the end of the serial output operation of read data from the memory cell coupled to the previously selected word line,
At the time when the serial clock signal SC becomes low level, the data transfer control signal DT10E is returned to high level, and the read data from the memory cell coupled to the newly selected word line is transferred to the data register and serially output. The operation begins. As a result, CR
Real-time data transfer is performed in synchronization with T's ton trade.

However, as display technology progresses, high-definition C
With the development of RT, the speed of ton trading in which display data is serially output has become faster.
Starting up in synchronization with C has become the norm. That is, the timing for returning the data transfer control signal 〒/σ to the high level is determined by monitoring the output signal of the counter circuit of the memory control circuit, as described above.

Therefore, the delay time for the counter circuit to step by the serial clock signal SC and the delay time for decoding and monitoring its output signal are equal to the serial clock signal SC.
If the period is relatively large compared to the period of , it becomes difficult to raise the data transfer control signal D T10 E at the same period as the serial clock signal SC. Therefore, as shown by the dotted line in FIG.
The time relationship between T/δ and the serial clock signal SC cannot be matched, and in particular, the rise of the data transfer control signal C/C is delayed with the rise of the serial clock signal SC, resulting in the data being coupled to the newly selected word line. The timing signal φdt for transferring read data from a memory cell to a data register becomes shorter. This causes the serial data transfer operation to become unstable.
This results in the displayed 'vi image being distorted.

An object of the present invention is to provide a semiconductor memory device such as a dual port memory that stabilizes serial data transfer operations.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

Means for Solving Problem C] A brief overview of typical embodiments disclosed in this application is as follows. That is,
When transferring data to dual port memory, the timing to start transferring read data to the data register can be set arbitrarily by specifying the number of clock signal cycles from the start of the data transfer cycle until the start of the transfer operation. This allows the settings to be made as follows.

According to the above means, it is possible to arbitrarily specify the clock signal position at which the transfer operation is started according to the count value of the counter circuit of the memory control circuit at the time of starting the data transfer operation of the dual port memory. , also dual
A countdown counter circuit provided in the port memory allows transfer operations to be performed in synchronization with a clock signal, making it possible to realize semiconductor storage devices such as dual port memories that stabilize display data transfer operations. It is possible.

〔Example〕

Figure 2 shows a dual port system to which this invention is applied.
A block diagram of one embodiment of a memory is shown. Each circuit block in the figure is formed on a single semiconductor substrate such as, but not limited to, single-crystal silicon using known semiconductor integrated circuit manufacturing techniques.

The dual port memory of this embodiment includes a random access port that is accessed in 4-pin units and has a basic configuration of a dynamic RAM, and a serial port that serially inputs and outputs stored data at word ia*.・Access boats will be provided.

This allows the dual port memory to perform a series of serial output operations while simultaneously performing random access port accesses. Furthermore, although not particularly limited, the random input/output circuit RIO included in the random access port is provided with a logic operation circuit for performing rask operations, etc., and a function control circuit FC for controlling this logic operation circuit. provided. The logic operation circuit uses various operation methods such as AND and OR, and which operation is determined by the operation code input via the address signal external terminals AO to A3 in a specific combination of control signals. specified by.

The serial access boat is equipped with a serial input/output circuit S■0, which normally has four serial input/output terminals 31.
01 to 3104, storage data corresponding to the four memory arrays is simultaneously input and output serially. Also,
In a specific combination of operation codes, it can also be used as a memory with a so-called x1 bit configuration in which read data output from four memory arrays is alternately output via the serial input/output terminal 5101.

Dual port memory receives row address strobe signal RAS and column address strobe signal CA used in normal dynamic RAM from an external device.
In addition to control signals such as S and write enable signal W, a data transfer control signal D T10 E used for output control and data transfer control between the random access port and the serial access port, and the serial access - A serial output control signal SOE used for controlling input/output switching of the boat and a serial clock signal SC used as a synchronization signal during serial input/output are input.

Although not particularly limited, the random access port of the dual port memory of this embodiment is provided with four memory arrays M-ARYI to M-ARY4, and sense amplifiers SAI to SAI correspond to the respective memory arrays. S
A4. Column switches C3WI to C3W4 are provided. Furthermore, a random access port column address decoder RCD and a row address decoder RD are provided in common to the memory arrays M-ARYI-M-ARY4. A plurality of these address decoders may be provided depending on the arrangement of the memory array on the semiconductor substrate. FIG. 2 exemplarily shows the memory array M-ARYI and its peripheral circuits.

In FIG. 2, the memory array M-ARY1 has m11 word lines arranged in the vertical direction of the figure, n+1 sets of complementary data lines and these word lines arranged in the horizontal direction of the figure. and the complementary data line (m+1
)x (n+1) memory cells.

The dynamic memory cells constituting the memory array M-ARYI include an information storage capacitor and an address selection M
It is composed of O3FET. n placed in the same row
The gates of the address selection MO3FETs of +1 memory cells are coupled to the corresponding word lines. Each word line is further coupled to a row address decoder RD, and one word line designated by X address signals AXO to AXi is selected and designated.

Row address decoder RD is row address buffer R.
Complementary internal address signal ax□-a supplied from ADB
xi (Here, for example, an internal address signal axQ having the same phase as the X address signal AXO supplied from the outside and an internal address signal 771 having the opposite phase are combined to form a complementary internal address signal a.
xQ (the same applies hereinafter) is decoded, one word line designated by the X address signals AXO to AXi is selected, and set to a high-level selected state. The word line selection operation by the row address decoder RD is performed by the word line selection timing signal φ supplied from the timing control circuit TC.
It is done according to X.

The row address buffer RADB receives the row address signal supplied from the address multiplexer AMX, forms complementary internal address signals (xQ-Xi), and supplies them to the row address decoder RD (J4). In this case, the X address signals AXO to AXi for specifying a row address and the Y address signals AYO to AYi for specifying a column address are so-called addresses that are time-divided and supplied via the same external terminals AO to Ai. It uses a multiplex system.

Therefore, X
Address signals AXO to AXi, /1 (and Y address signals AYO to AYi are applied to external terminals AO to A, respectively, in synchronization with the falling of the column address strobe signal CAS.
i. Furthermore, the dynamic RAM of this embodiment is provided with an automatic refresh mode for reading and rewriting data stored in memory cells within a predetermined cycle, and in this automatic refresh mode, a word line to be refreshed is specified. A refresh address counter REFC is provided for this purpose.

Address multiplexer AMX operates according to timing signal φref supplied from timing control circuit TC.
X address signals AXO to AXi supplied via external terminals AO to Ai and refresher address counter REF
Refresh address signals cxQ~c supplied from C
xi is selected and transmitted to the row address buffer RADB as a row address signal. That is, in a normal memory access mode in which the timing signal φref is set to a low level, X address signals AXO to AXi supplied from an external device via external terminals AO to Ai are selected, and the timing signal φref is set to a high level. In the automatic refresh mode, the refresh address signals cxQ to cxi output from the refresh address counter REFC are selected.

As mentioned above, since the X address signals AXO-AXi are supplied to the external terminals AO-Ai in synchronization with the falling edge of the row address strobe signal RAS, the acquisition of the row address signal by the row address buffer RADB is controlled by the timing control circuit. This is performed in accordance with a timing signal ψar generated by detecting the fall of the row address strobe signal RAS at TC.

On the other hand, the drains of the address selection MO3FETs of the memory cells arranged in the same column of the memory array M-A RY 1 are coupled to the corresponding complementary data lines. Each complementary data line of memory array M-ARY1 is connected on one side to a corresponding switch MO of column switch C3W1.
3FET, and further selectively connects the complementary common data line CDI (here, the non-inverted signal line CD of the complementary common data line
I and the inverted signal line CDI are collectively represented as a complementary common data line DDO. The same applies hereafter).

The column switch C3WI is constituted by a fi+l pair of switches MO3FET each coupled to a corresponding complementary data line. These switches MOS FET
The other terminal of is commonly coupled to a non-inverted signal line CDI or an inverted signal line CDI constituting a complementary common data line.

Thereby, the column switch cswt selectively connects fi+1 sets of complementary data and the common complementary data line CDI. The gates of each pair of two switches MO3FET constituting the column switch C3WI are connected in common, and each is supplied with a data line selection signal formed by a column address decoder RCD for a random access port.

The random access port column address decoder RCD decodes the complementary internal address signals ayQ to ayi supplied from the column address buffer CADB, and selects the data line according to the data line selection timing signal φyr supplied from the timing control circuit TC. A selection signal is formed and supplied to column switches C3WI to C3W4.

Column address buffer CADB receives Y address signals AYO to AYi supplied via external terminals AO to Ai in accordance with a corresponding signal φac generated by detecting the fall of column address strobe signal CAS in timing control circuit TC. Enter and hold, as well as
Column address decoder RC for random access port by forming complementary internal address signals ayQ to ayi
Supply to D.

Each complementary data line of memory array M-ARY1 is coupled on the other hand to a corresponding unit circuit of sense amplifier SAI, and further coupled to a corresponding unit circuit of data register DRI of the serial access port.

Each unit circuit of the sense amplifier SAI has a launch consisting of two cross-connected CMOS inverter circuits as its basic configuration. These sense amplifier unit circuits receive a timing signal φpa supplied from a timing control circuit TC.
The small read signal outputted from each memory cell to the corresponding complementary data line is amplified and converted into a high level/low level binary signal.

A complementary common data line CDI to which complementary data lines designated by Y address signals AYO to AYi are selectively connected is coupled to a random access port input/output circuit RIO. This random access port input/output circuit R
Complementary common data lines CD2 to D4 provided corresponding to memory arrays M-ARY2 to M-ARY4 are similarly coupled to IO.

Random input/output circuit RIO is a random access port of dual port memory! In the write operation mode, the timing signal φrw supplied from the timing control circuit TC brings the input/output terminal I into the operating state.
Write data supplied from an external device via O1 to IO4 is used as a complementary write signal, and a complementary common data line -
〇Transmit to D1 to D4. Also, dual port
In the random access port read operation mode of the memory, the read binary signal of the memory cell is activated by the timing signal φrr supplied from the timing control circuit TC, and is transmitted via the complementary common data lines CDl-CD4. Further amplify and input/output terminal 101
~ Send from r04.

Furthermore, this random input/output circuit RIO includes, but is not particularly limited to, logical operations for performing various operations between data read from memory cells and input data and writing them again using a read/modify/write function. A circuit is provided. This logic operation circuit is provided with various operation modes for performing processing such as rask operation.

The operation mode of the logic operation circuit is specified by the function control circuit FC. The function control circuit FC connects external terminals AO to
The operation code includes a register for holding the operation code supplied via A3 and a decoder for decoding the operation code and selecting/designating the operation mode of the logical operation circuit. In a combination in which the row address strobe signal RAS is set to low level prior to and the write enable signal WE is set to low level at the same time, it is supplied to the dual port memory via external terminals AO to A3. Further, a specific combination of operational codes is used as an internal control signal Sp for making the output of the serial input/output circuit 310 described later into a so-called x1 bit configuration.

As will be described later, the number of cycles of the serial clock signal SC from startup to the start of serial output operation is input to the data input/output external terminals 101-104 in the serial read operation mode of the dual port memory. be done. As a result, the dual port memory of this embodiment can arbitrarily set the timing to start the serial output operation after startup, and uses the serial clock signal SC, which has a short period to accommodate high-speed ton trading.
It is possible to perform stable and synchronized serial output operation. The number of cycles input to the data input/output external terminals 101 to 104 is determined by the internal signal i o l w i o
4, it is sent to the timing control circuit TC.

On the other hand, the serial access port of the dual port memory of this embodiment includes an n+l pit data register DRI-DR4 provided corresponding to the complementary data line of each memory array, and data selectors DSLI to DSL4.
and a pointer PNT provided in common to these four data registers and data selectors, a serial access boat column address decoder SCD, and a serial input/output circuit SIO. Note that a plurality of pointers PNT and serial access boat column address decoders SCD may be provided depending on the arrangement of the memory array on the semiconductor substrate.

The data register DRI includes n + 1 flip-flops for data latch provided corresponding to each complementary data line of the memory array M-ARYI, and the input/output nodes of these flip-flops and the corresponding complementary data line. A switch MO3FET for data transfer is provided between the non-inverted signal line and the inverted signal line, and a timing signal φdt for data transfer is supplied to the gate thereof from the timing control circuit TC.

Each bit of data register DRI is further coupled to a corresponding switch MO3FET of data selector DSLI. The data selector DSLI has the same configuration as the above-mentioned column switch C3WI, and the data register DRI
Each bit and complementary common data line CDS for serial input/output
1 selectively connected. The gates of the switches MO3FET of each pair of data selector DSLI are connected in common, and a register selection signal is supplied from pointer PNT.

The pointer PNT consists of a launch circuit (pointer latch) that holds the serial operation start bit designated by the serial access boat column address decoder SCD, an n+l bit shift register, and an N-channel MOS FET provided between them. It consists of a switch circuit consisting of: The output terminal ps of the last bit of the shift register is coupled to the input terminal of the first bit thereof, and the timing signal φdt is commonly supplied to the gates of these switch MOS FETs. The shift register of the pointer PNT is held in a pointer latch circuit that performs a loop-shaped shift operation in accordance with the shift clock timing signal φC supplied from the timing control circuit TC in the serial input/output mode of the dual port memory. The selection signal is supplied as the initial value of the shift register when the timing signal φdt is set to high level.

The serial access port 1 column address decoder SCD receives complementary internal address signals supplied from the column address buffer CADI3.

~Decode the Y address signal AYO~AYi
Only the bit of pointer PNT corresponding to the first bit of serial input/output specified by is set to logic "1". In other words, in serial input/output mode, a word line is selected by X address signal AXO"AXi, and Y address The first column address to be serially input/output is specified by signals AYO to AYi.
1” signal is sent to the pointer P according to the timing signal φC.
It is shifted in a loop within the NT. By shifting this logic "1" signal, the data selector D3L
1 are sequentially supplied with high-level register selection signals,
Each bit of data register DRI is connected one after another to complementary common data line CDSL for serial input/output. As a result, the dual port memory of this embodiment can start serial input/output of stored data from any column address, and can speed up scroll processing in the image memory, for example.

From the above, in the dual port memory serial read operation mode, the memory array M-ARY
The read data of n+1 bits output from the n+1 sets of complementary data lines of 1 is taken into the data register DRI by setting the timing φdt to a high level. At the same time, pointer PNT receives timing signal φd.
The selection signal held in the pointer latch by the high level of t is transferred to the shift register as an initial value.

The read data is sent to the serial input/output circuit SIO via the complementary common data line CDS1 for serial input/output according to the register selection signal sent one after another from the pointer PNT.
sent to. On the other hand, in the dual port memory serial write operation mode, serial input/output terminal 5
Write data serially input from IOI via serial input/output circuit 510 is sequentially input to corresponding bits of data register DRI according to register selection signals successively sent from pointer PNT.

The write data held in the data register DRI is
By setting the timing φdt to high level,
It is written all at once into n+1 (11) memory cells coupled to the selected word line of memory array M-ARYI.

The serial input/output circuit 310 includes four main amplifiers, a data input buffer, and a data output cover sofa provided corresponding to the complementary common data lines CD51 to CD54 for serial input/output and the serial input/output terminals 3101 to 5104. The data output buffer of circuit 310 is configured to perform timing control in the dual port memory read data transfer mode. The read data is activated by the high level of the timing signal φ3r supplied from the 1IJa circuit TC, and is outputted via the corresponding serial input/output complementary common data lines CDS1 to CD54 and amplified by the corresponding main amplifier. Output to external devices from serial input/output terminals 5IOI to 5I04. Further, the data manual buffer of the serial input/output circuit 310 is put into an operating state by the high level of the timing signal φaH supplied from the timing control circuit TC in the serial write operation mode of the dual port memory, and the Serial input/output terminal 5I01-
The write data supplied from an external device via 3104 is made into a complementary write signal, and is transmitted to the corresponding serial input/output complementary common data lines -〇DSI to CD54.

Serial input/output operations on data stored in the serial input/output circuit S20 are performed in the timing control circuit TC according to a timing signal -C formed based on a serial clock signal SC supplied from the outside.

In the dual port memory of this embodiment, the serial output signal of the normal serial input/output circuit SIO is output simultaneously in 4 bits via the four serial input/output terminals 5101 to 5IO4 as described above. However, if you want to realize a serial memory with even larger storage capacity, you can combine this dual port memory with four memory arrays M-AR.
It can be used as a memory having a so-called x1 bit configuration in which read data outputted from YI to M-ARY4 is serially outputted via one serial input/output terminal. In this case, as mentioned above, the random input/output circuit RI
One of the combinations of operation codes for controlling the operation mode of the logic operation circuit of O is the internal control signal 3p for making the serial output have a ×1 bit configuration. When the internal control signal sp supplied from the function control circuit FC becomes high level, the serial input/output circuit S10 outputs read data serially through four sets of complementary common data lines for serial input/output CD31 to DS4. Data is sequentially selected by a multiplexer provided in the serial input/output circuit SIO, and one serial input/output terminal 1ro
1 to an external device. Since this serial output is performed according to the timing signal φG supplied from the timing control circuit TC, the data rate of each input/output terminal is Same data rate.

The timing control circuit TC forms the above-mentioned various timing signals using the row address strobe signal R supplied as a control signal from the outside, and supplies them to each circuit. In addition, a timing signal φ for synchronizing serial input/output operations is provided using a serial clock signal SC supplied externally.
C is formed and supplied to the serial input/output circuit 510.

The operation mode of the dual port memory is specified by appropriate combinations of control signals. For example, first, the row address strobe signal RAS becomes low level, and then the column address strobe signal στ茗 becomes low level. If the write enable signal WE is at a high level at this point, the normal random access port read operation mode is set. If the write enable signal WE is at a low level at the time when the row address strobe signal RAS goes to a low level and then the column address strobe signal CAS goes to a low level, the normal random access port write operation mode or arithmetic write operation mode is set. Ru. Further, when the write enable signal WE is at high level and the data transfer control signal TE/6I- is at low level at the falling edge of the row address strobe signal RAS, the read data of the memory array is transferred to the data registers DRI to DR4. The mode is read data transfer mode for serial reading.

As mentioned above, in the read data transfer mode of the dual port memory of this embodiment, the data input/output external terminals 101 to 104 are activated and then activated in synchronization with the fall of the row address strobe signal RAS to the low level. The number of cycles of the serial clock signal SC until the data transfer operation of the serial read data starts is specified. For this reason, the timing control circuit TC is provided with a counter circuit CTR for taking in the number of cycles input through the data input/output terminals 101 to 104 and counting down according to the serial clock signal SC.

The read data output to each data line is transferred to the data registers DRI-DR4 by the timing signal φdt, which is generated when the count value of the counter circuit CTR of the timing control circuit TC becomes “0”, and is further transferred to the data register DRI-DR4 by the timing signal φC. According to the serial input/output circuit SlO
From serial input/output terminals 3101 to S! It is output to the outside via 04.

Next, when the data transfer control signal DT10E and the write enable signal W1 are at a low level and the serial input/output control signal D3 is at a high level at the falling edge of the row address strobe signal RAS, the timing control circuit TC performs a dual・Set the port memory to serial write operation mode and connect serial input/output terminals 5lots~
Serial write data supplied via 3104 is input to data registers DRI to DR4. Furthermore, at the falling edge of the row address strobe signal RAS, the write enable signal WE is at a low level together with the data transfer control signal DT10E, and the serial input/output f11
When the control signal SOE is at a low level, the write data transfer mode is set, and the transfer timing signal φdt is generated. As a result, the transfer switches MO3FETs of the data registers DRI to DR4 are turned on, and the data register D
The write data sent to RI to DR4 is input all at once to the fi+l bit memory cells coupled to the selected word line of the memory array.

A serial write operation using a serial access port of a dual port memory is realized by executing the above-described serial write operation mode and then executing the write data transfer mode in combination.

On the other hand, when the column address strobe signal CAS changes from high level to low level prior to the falling of the row address strobe signal 1τ, the so-called C
The AS before RAS refresh mode is set. Furthermore, if the write enable signal WE is at a low level at one point when the row address strobe signal RAS falls,
This is an arithmetic mode setting cycle, and the arithmetic code supplied via the external terminals AO to A3 is taken into the register in the function control circuit FC.

In each operation mode except for the above operation mode setting cycle, X address signals AXO to AXi for specifying a word line are supplied to external terminals AO to Ai in synchronization with the falling of the row address strobe signal π■. , and in an operation mode that requires a column address, the Y address signal AYO for specifying the complementary data line is synchronized with the falling edge of τ1 by the column address strobe signal.
~AYi is supplied to external terminals AO~At.

FIG. 1 shows a circuit diagram of a part of the timing control circuit TC in the dual port memory of FIG. 2. In FIG.

As mentioned above, in the dual port memory of this embodiment, the row address strobe signal As becomes low level and the dual port memory is activated, and then the read data is transferred via the data input/output external terminals 101 to 104. The number of cycles of the serial clock signal SC until the data transfer operation starts is specified in binary notation. These cycle numbers are based on internal data iol~io4
The signal is supplied to the corresponding pin of the counter circuit CTR of the timing control circuit TC.

The counter circuit CTR is supplied with a timing signal φcs, which is generated in synchronization with the falling edge of the row address strobe signal RAS, from another timing generation circuit provided in the timing control circuit TC. Further, a stepping timing signal φcp formed within the timing control circuit TC shown in the figure is supplied.

Inverted output signal 01-C of each pin of counter circuit CTH
8 are respectively input to the four input terminals of the AND gate circuit AGI. Output signal c of AND gate circuit AGI
tro is the inverted output signal 01 to C of the counter circuit CTR.
8 are all logic "0", that is, when the count value of the counter circuit CTR is "O", it is set to high level.

The output signal ctro of the AND gate circuit AGI is supplied to one input terminal of the Nandt gate circuit NAGI, inverted by the inverter circuit N3, and supplied to one input terminal of the AND gate circuit AG2. The other input terminal of the Nant gate circuit NAGI receives the column address strobe signal σX when the row address strobe signal RAS falls from the high level to the low level.
The output signal srm of a flip-flop (not shown), which is set when the read and write enable signal W1 is set to high level and the data transfer control signal DT10E is set to low level, is output to an appropriate delay means (for example, an even number of inverter circuits) D. Supplied via. In other words, the output signal srm of this flip-flop is a dual-port
It is used as a mode signal to specify the memory read data transfer cycle. As a result, the output signal of the Nant gate circuit NAG1 is changed to the output signal of the AND gate circuit AGI.
It becomes low level when the output signal ctrQ and mode signal srm are high level. Nant gate circuit NAGl
On the one hand, the output signal is delayed by a suitable delay means, further inverted by an inverter circuit N4, and then input to one input terminal of the NOR gate circuit N0CI. Further, the output signal of the NOR gate circuit NAG1 is directly inputted to the other input terminal of the NOR gate circuit N0G1. The output signal of the NOR gate circuit N0GI is sent to the pointer PN as a timing signal φdt.
supplied to T. In other words, this timing signal φdt is used in the read data transfer mode of the dual port memory in which the mode signal srm is at a high level.
When the output signal cLrQ of the AND gate circuit AGI is set to a high level, it is temporarily set to a high level for a predetermined period.

On the other hand, the other input terminal of the AND gate circuit AG2 has
A serial clock signal SC is supplied via inverter circuits N1 and N2. As a result, the output signal of the AND gate circuit AG2 is such that the output signal ctrQ of the AND gate circuit AGI is at a low level, the output signal of the inverter circuit N3 is at a high level, that is, the count value of the counter circuit CTR is not 0'', and the serial clock signal SC is at a low level. In other words, the output signal of the AND gate circuit AG2 becomes the sidewalk timing signal φcp for counting down the counter circuit CTR until the count value of the counter circuit CTR reaches 103.

Further, the serial clock signal SC passing through the inverter circuits Nl and N2 becomes the timing signal φC.

FIG. 3 shows a timing diagram of an embodiment for explaining the operation of the dual port memory including the timing control circuit TC of FIG. 4 in the read data transfer mode. This diagram shows that the dual
An overview of the port memory read transfer mode will be explained.

In FIG. 3, this dual port memory is activated by changing the row address strobe signal RAS from high level to low level. Prior to the falling of the row address strobe signal RAS, the column address 10E° is set to a low level. Further, external terminals AO to AI are supplied with X address signals AXO to AXi for specifying word lines, and data input/output external terminals 101 to 104 are supplied with read data serially from the falling edge of the row address strobe signal RAS. Serial clock signal SC until output operation starts
The number of cycles ctrz is supplied.

This cycle number ctrz is determined according to the count value of a counter circuit included in a memory control circuit provided outside the dual port memory and for controlling the horizontal pixel position of CTH. That is, when the count value corresponding to the last bit of the read data for l word lines is N1, and the count value at the time when the row address strobe signal RAS falls is N2, the number of cycles ctrz is cLrz-Nl-N2. It is required as. This number of cycles ctrz is determined to be an appropriate value within a range that satisfies the above equation and exceeds the time required until read data is established at the random access port of the dual port memory.

The column address strobe signal σAS changes from high level to low level with a slight delay from the fall of the row address strobe signal RAS.Prior to the fall of the column address strobe signal CAS, the serial output is output to external terminals AO to Ai. The address of the data line that should be output first in operation is the Y address signal AYO~
Supplied as AYi. Row address strobe signal RAS, column address strobe signal σAS.

Write enable signal WE and data transfer control signal DT
10E is returned to high level after the count value of the counter circuit CTR becomes "0" and serial output operation is started.

In a dual port memory, the X address signal %A is triggered by the fall of the row address strobe signal RAS.
XO to AXi are taken into the row address buff 7RADB, and a word line selection operation is performed. Furthermore, with the fall of the row address strobe signal RAS, the mode signal srm is set to high level, and the timing signal φCa is generated, and the external terminals 101 to 101 for data input/output are generated.
(2) Number of cycles supplied to o4 (ctrzl) <ly Counter-[3 Taken into CTR. As a result, the output of the counter circuit CTr2 becomes a value other than "0", and the output signal ctrQ of the AND gate circuit AGI in FIG. Due to the high level of the output signal, the output signal of the AND gate circuit AG2, that is, the increment timing signal φ of the counter circuit CTR
cp is formed. The counter circuit CTR starts counting down from the captured cycle number ctrz toward 0'' in response to the fall of the timing signal φcp.

While the counter circuit CTH is counting down the serial clock signal SC, the word line selection operation in the dual port memory is completed, and the n11-valent memory cells connected to the selected word line are read data are established on respective complementary data lines. Furthermore, when the column address strobe signal CAS falls, the Y address (=signs AYO to AYi) is taken in, and the data line selection operation by the column address decoder SDC for the serial access port is started. Timing signal φys is generated at the timing when the decoding process by the column address decoder SCD is completed, and the pointer PN
Logic 11'' is set to the focus corresponding to the Y address signal AYO-AYi of T.

As the countdown by the counter circuit CTR progresses and the count value reaches '0'', the output signal ctrQ of the AND gate circuit AGI becomes high level. As a result, the output signal of the inverter circuit N3 becomes low level,
The increment timing signal φcp of the counter circuit CTR is stopped. Further, a timing signal φdt is generated, and read data established on each data line is transferred to data registers DRI to DR4. In addition, the timing signal φ
sr is formed in synchronization with the serial output control signal SOE that 1iJWs the data output buffer DOB of the serial input/output circuit SIO.

Due to the high level of the timing signal φ3r, the serial input/output terminals 5lot to 5104 are in a high impedance state!
The level corresponds to the read data at the start address specified by the Y address signals AYO to AYL from aHz. This starts the read data output operation.

In the timing control circuit 'rc, a shift timing signal φC synchronized with the serial clock fn SC is formed by the mode signal arm and the high level of the output signal ctrO of the AND gate circuit AGI, and is sent to the serial input/output circuit 310 and the pointer PNT. Supplied. As a result, by the selection operation of the serial access boat column address decoder SCD, the logic 11' signal sent to the pin point corresponding to the Y address signals AYO to AYi of the pointer PNT is shifted in a loop, and the data registers DRI to AYi are shifted in a loop. The read data held in DR4 is transferred to serial input/output complementary common data lines CD5I to CD54.
and is output to serial input/output terminals 5IOI to 5IO4 via the serial input/output circuit 310. The shift operation of the pointer PNT by the timing signal φC is performed in synchronization with the rise of the timing signal from low level to high level. Further, in the pointer PNT, the leading pulse of the timing signal φC is ignored, and the output time width of the leading data is ensured.

The serial output operation of the read data based on the timing signal φC progresses, and when the output of the last read data is completed, the serial output control signal SOE is returned to the high level. Due to the high level of the serial output control signal SOE, the mode signal Srm is set to a low level, and the timing signal φsr for serial output is set to a low level in synchronization with the rise of the serial clock signal SC. As a result, the serial output operation of the dual port memory is stopped, and the serial input/output terminal S! 01 to 3104 are in a high impedance state.

As described above, in the dual port memory of this embodiment, in the read data transfer mode, read data is serially output from the falling edge of the row address strobe signal XK in synchronization with the falling edge of the row address strobe signal RAS. The number of cycles ctrz of the serial clock signal SC until the start of operation is specified. This number of cycles ctrz is determined by the timing control circuit T
It is initially set in the counter circuit CTR provided in C,
A countdown will take place. When the countdown by the counter circuit CTR is completed and the count value reaches "O", the serial output operation of the read data is started. For this reason, even though the CTR provided externally has been refined and the ton trading of display data has become extremely fast, the serial clock signals SC and
Dual mode reliably synchronizes with the TR scan timing.
A serial output operation of the port memory is performed, and a stable display image can be obtained.

As shown in the above embodiment, when the present invention is applied to a semiconductor storage device such as a dual port memory used as an image processing memory, the following effects can be obtained. That is, (1) in the read data transfer mode of the dual port memory, in synchronization with the start control signal, specify the number of cycles of the serial clock signal from startup until the start of serial output operation of read data. By counting down by the counter circuit provided in the timing control circuit TC, it is possible to obtain the effect that the serial output operation of read data can be started at a stable timing in synchronization with the serial clock signal.

(2) Due to item (1) above, even though the externally provided CTR has become highly refined and the ton trading of display data has become extremely fast, the serial clock signal S
The real-time transfer of read data can be performed reliably in synchronization with the C and CTR scan timings, resulting in the effect that a stable display image can be obtained.

Although the invention made by the present inventor has been specifically explained above based on examples, it goes without saying that this invention is not limited to the above-mentioned examples, and can be modified in various ways without getting the gist of the invention. Nor. For example, in the timing control circuit TC shown in FIG. 1, timing alignment is performed by counting down the counter circuit CTR. is counted up, and the counter circuit CT
Output of R and number of cycles set in register ctrz
Alternatively, after decoding the cycle number ctrz and setting logic "1" to the corresponding bit of a separately provided shift register, the serial clock signal SC It is also possible to shift the shift register by ct and start the serial output operation when this logic "1" reaches a predetermined position.In this embodiment, the number of cycles ct
Although rz is supplied in synchronization with the falling edge of the row address strobe signal RAS, it may be supplied in synchronization with the falling edge of the column address strobe signal CAS. Furthermore, the dual port memory in FIG. 2 may be configured by one memory array, or the input/output circuit R of the random access port
Various embodiments can be adopted, such as not providing a logical operation circuit in the IO, a blank configuration, and a combination of control signals. The field of dual bow I.
- Although the case where the present invention is applicable to memory has been described, the present invention is not limited thereto, and can also be applied to various other multi-board memories having serial input/output functions, for example.

The present invention is applicable to at least a semiconductor memory device whose serial output operation is controlled by a control signal and a clock signal supplied from the outside.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. In the read data transfer mode of the dual port memory, the number of cycles of the serial clock signal from startup to the start of the data transfer operation of read data is specified, and it is provided in the timing control circuit TC. By counting down with a counter circuit that uses a serial clock signal, it is possible to start serial output operation of read data at a stable timing in synchronization with the serial clock signal. No. and C'r R
It is possible to perform real-time fm transfer of read data in synchronization with the scan timing of , and to obtain a stable display image.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a part of a timing control circuit of a dual port memory to which the present invention is applied, and FIG. 2 is a circuit diagram of a dual port memory including the timing control circuit of FIG. FIG. 3 is a block diagram showing an embodiment of the memory; FIG. 3 is a timing diagram showing an embodiment of the read data transfer mode in the dual port memory of FIG. 2; FIG. Read data transfer mode 1 of dual boat memory developed by
- FIG. TC...timing control circuit, CTR...counter circuit, AGI-AC3...and gate circuit, N A
G1...Nandt gate circuit, N1-N4...Inverter circuit. M-ARYl...Memory array, SAI...Sense amplifier, C3WI...Column switch, RCD...
Column address decoder for random access port, SCD...column address decoder for serial access port, RADB...row address buffer, AMX...address multiplexer, CADB...
・Column address buffer, REFC...Refresh address counter, DRI...Data register, D
SLI...data selector, PNT...pointer, RIO...input/output circuit for random access port, FC...function control circuit, 310...input/output circuit for serial access port . Figure 1 Figure 2 Figure 3 ω, X-AY) Summary 4th section

Claims (1)

[Claims] 1. A serial-to-parallel conversion circuit that receives a plurality of read data output in parallel via a plurality of data lines constituting a memory array and outputs the data serially in accordance with a clock signal supplied from the outside; The clock includes a timing control circuit that controls the serial output operation of the serial-to-parallel conversion circuit, and the clock is used from when the serial output operation is started by an externally supplied activation control signal to when the serial output operation is started. 1. A semiconductor memory device characterized in that the number of cycles of a signal can be arbitrarily set by specifying the number of cycles of a signal. 2. The timing control circuit includes a counter circuit that takes in the number of cycles supplied from the outside in synchronization with the activation control signal and counts down in accordance with the clock signal, and an output signal of the counter circuit whose all bits are logic "0".
3. The semiconductor memory device according to claim 1, further comprising a timing generation circuit that detects that the serial output operation occurs and forms an internal clock signal for performing a serial output operation. 3. The semiconductor memory device described above is a dual port memory, and the number of cycles is supplied via a plurality of data input terminals for a random access port. The semiconductor storage device described above.