JP3323882B2 - Clock synchronous memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention comprises a mode register for setting an operation mode, and a clock synchronous system for setting an operation mode of a burst length, a wrap type and a CAS latency in accordance with the contents set in the mode register. The present invention relates to a technology effective for a memory (performing data input / output in synchronization with a clock input).

[0002]

2. Description of the Related Art In recent years, as the operating frequency of a microprocessor has been improved, a memory which can be accessed at a high speed has been required. In order to meet this demand, a clock synchronous memory such as a synchronous DRAM has been developed. The synchronous DRAM is provided with a mode register for setting an operation mode, and by setting a burst length, a wrap type, and a CAS latency in the mode register, an optimum operation of the system can be performed. Here, the burst length is the number of data to be continuously input and output, and is, for example, 1, 2, 4, 8
And full page. The wrap type is burst access (continuous input / output)
The method of changing the internally generated column address at the time of, for example, selecting one of a sequential method in which the column address is continuously changed in the same bank and an interleave method in which the column address is scrambled Can be. Further, the CAS latency is the number of clocks until the first data can be read after the input of the read command, and can be selected from, for example, 1, 2, and 3.

FIG. 2 shows a schematic configuration diagram of a synchronous DRAM.

In the figure, reference numeral 21 denotes a memory cell array, 2
2 is a row decoder, 23 is a column decoder, 24 is a row address buffer, and 25 is a column address buffer.
A buffer 26, a data control circuit, a data input / output buffer 27, a control logic 28, and a mode setting unit 29 including a mode register. SS is an output signal of the mode register in the mode setting unit 29 and is input to the control logic 28.

[0005] The mode setting in the synchronous DRAM is realized by inputting a code (command) indicating a necessary operation to an input-only pin. Normally, a chip select signal CS / and a row address strobe signal RAS
/, The column address strobe signal CAS /, and the write enable signal WE / are set to the “Low” level, and the address terminals A0 to A6 are used as data input terminals.

FIG. 3 shows a simplified configuration of the mode setting section.

The mode register 31 includes 3-bit D flip-flops 32, 33 and 34. The outputs of the D flip-flops 32, 33 and 34 are respectively
It indicates a burst length, a lap type, and a CAS latency. Actually, one burst is provided for each of the burst lengths of 1, 2, 4, 8, and full-length, and the same applies to other modes, but is simplified in FIG.

The AND gates 35, 36 and 37 are all opened by the mode register set signal MRS, and the output is determined by the values of the 7-bit addresses A0 to A6.
The mode register set signal MRS is supplied to the AND gate 38.
And the chip select signal CS /, the row address strobe signal RAS /, the column address strobe signal CAS /, and the write enable signal WE / are all set to the “Low” level, and at the same time, the predetermined address values A0 to A6 , An appropriate operation mode can be set in the mode register 31.

[0009] The mode setting in the mode register is performed by an initialization routine before memory access. Before accessing the memory, the user sets the contents of the mode register in accordance with the specifications and usage of the memory access.
Among the operation modes specified by the mode register, the CAS latency means the number of clocks from reception (latch) of a CAS address (column address) of a memory access to input / output of first data. Therefore,
If the CAS latency is set to “2”, the CAS latency
The first data is taken in and out two clocks after receiving the address.

In general, a semiconductor memory such as a DRAM requires a certain period of time after the power is turned on until the power supply potential Vcc stabilizes at a predetermined potential and the internal circuit stabilizes. It is necessary to set an appropriate operation mode. For this reason, the time from when the power is turned on until the access becomes possible becomes longer. Also, after power-on and before accessing the memory, it is necessary to set a mode by an initialization routine or the like.

As a means for solving such a problem, in a synchronous DRAM, an initial value of a mode register is set by a nonvolatile switch element such as a laser fuse or an electric fuse, and after a power supply is turned on, a power supply potential is reduced. It has been proposed to detect the rising edge and automatically set an initial value in a mode register to reduce the complexity of mode setting by an initialization routine or the like (Japanese Patent Application Laid-Open No. 7-1995).
93970).

[0012]

The specifications of the same device, such as the power supply potential and access time, are changed. However, in general, the higher the power supply potential, the shorter the access time of the memory. Can be reduced (shortened). In this case, if the contents of the mode register are fixed in advance as described above, it is impossible to set a latency optimized for the power supply potential.

Further, preparing devices of different operation modes in advance for each device specification becomes extremely complicated in terms of manufacturing and product management.

The present invention has been made to solve such a technical problem.

[0015]

SUMMARY OF THE INVENTION A clock synchronous memory according to the present invention includes a mode register for setting an operation mode.
In a clock synchronous memory that performs data input / output (including only data output) in synchronization with a clock input, a power supply potential detection circuit includes a plurality of mode registers in which different operation modes are set, and a power supply potential detection circuit. A mode register selection circuit for selecting a predetermined mode register from the plurality of mode registers in accordance with a power supply potential detection signal from the detection circuit.

The clock-synchronized read-only memory of the present invention includes a mode register for setting an operation mode, and a clock for outputting data in synchronization with a clock input in the operation mode set in the mode register. A synchronous read-only memory, comprising: a plurality of mode registers in which different operation modes are set; and a power supply potential detection circuit, wherein the plurality of mode registers are provided in accordance with a power supply potential detection signal from the power supply potential detection circuit. And a mode register selection circuit for selecting a predetermined mode register among the above mode registers, wherein the contents of each mode register are set when code data is written into a memory cell.

Further, in the clock synchronous read only memory according to the present invention, the mode register includes a MOS transistor, and the content of the mode register is set in a channel portion of the MOS transistor different from the channel type of the MOS transistor. The impurity ions are selectively implanted, and the implantation of the impurity ions is performed using the same mask as that for writing the code data.

According to the present invention, a plurality of mode registers are provided, an operation mode such as a predetermined latency is set in advance, and any one of the mode registers is selected according to the power supply potential. Optimal latency and the like can be set according to the potential. In addition, since it is not necessary to prepare a plurality of types of devices each having a different operation mode for each device specification, it is only necessary to prepare a single type of device. Is eliminated.

[0019]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a schematic configuration diagram of a synchronous DRAM which is an embodiment of a clock synchronous memory according to the present invention.

In the figure, reference numeral 11 denotes a memory cell array, 1
2 is a row decoder, 13 is a column decoder, 14 is a row address buffer, 15 is a column address buffer.
A buffer, 16 is a data control circuit, 17 is a data input / output buffer, 18 is control logic, and 19 is a mode setting unit including a mode register. SS is an output signal (operation mode signal) of the mode register in the mode setting unit 19 and is input to the control logic 18. Thus, the operation in the set mode is performed.

FIG. 4 shows the synchronous DRAM shown in FIG.
FIG. 2 is a configuration diagram showing a simplified configuration of a mode setting unit 19 in FIG.

The mode setting section 19 has n mode registers 411, 412,..., 41n, and different operation modes are set in the respective mode registers. Reference numeral 42 denotes a mode register selection circuit. The selector 43 is controlled by a selection signal Sn from the mode register selection circuit 42 to output an output signal (operation mode signal) MD1 from one of the n mode registers. , Or MDn is selected, and the selected output signal SS is input to the control logic 18. Thus, the operation in the operation mode set in the selected mode register is performed.

FIG. 5 shows a simplified configuration of each mode register.

In the present invention, the "mode register" is only required to have a function of storing the operation mode, and is not limited to a register including a flip-flop register. As will be apparent from the following description, for example, a device including only a fuse element is also included.

The mode register 51 includes D flip-flops 52, 53 and 5 each having a 3-bit set / reset terminal.
4 is provided. D flip-flops 52, 53 and 5
The outputs of 4 represent the burst length, the wrap type, and the CAS latency, respectively. Actually, the burst length includes one flip-flop for each of 1, 2, 4, 8, and full-length, and the same applies to other modes, but is simplified in FIG.

Each D flip-flop 52, 53 and 54
The switch elements 55 to 60 are connected to the set terminal (S) and the reset terminal (R), respectively. The other ends of the switch elements 55 to 60 are commonly connected, and the reset signal RST is supplied when the power is turned on. The output is connected to the output of the reset signal generation circuit 61. The switch element is constituted by, for example, a fuse element which can be blown by a laser or electrically, and is selectively blown according to a mode to be set in a manufacturing process. Or,
The switch element may be a wiring pattern whose connection / non-connection is selected in the layout design.

According to the above configuration, each switch element is turned on / off by the reset signal RST output when the power is turned on.
The initial value according to the OFF state is determined by each D flip-flop 5
2, 53 and 54 are automatically set.

The mode register shown in FIG. 5 is provided with a circuit similar to that shown in FIG. 3 so that an operation mode setting signal is inputted from the outside via an address terminal, and a setting based on the signal is performed. The value is taken into each of the D flip-flops 52, 53 and 54 by the clock signal CK. Thus, the operation mode can be changed. That is, when it is desired to update the contents of the mode register without using the initial value of the mode register, CS /, RA
S /, CAS /, and WE / are set to “Low” level,
By using the address terminals A0 to A6 as data input terminals, the contents of the mode register can be arbitrarily set.

As described above, in the mode register shown in FIG. 5, the mode register can be rewritten. However, when it is not necessary to rewrite the contents of the mode register, only the setting by the switch element is sufficient. This eliminates the need for input from the address terminal to each flip-flop, thereby simplifying the configuration. FIG. 6 shows a configuration diagram of the mode register in this case.

The mode register 71 has D flip-flops 72, 73 and 7 each having a 3-bit set / reset terminal.
4 is provided. D flip-flops 72, 73 and 7
The outputs of 4 represent the burst length, the wrap type, and the CAS latency, respectively. Actually, one burst flip-flop is provided for each of the burst lengths of 1, 2, 4, 8, and full-length, and the same applies to other modes, but is simplified in FIG.

Each D flip-flop 72, 73 and 74
The switch elements 75 to 80 are connected to the set terminal (S) and the reset terminal (R), respectively. The other ends of the switch elements 75 to 80 are commonly connected, and the reset signal RST is supplied when the power is turned on. The output is connected to the output of the reset signal generation circuit 81. The switch element is constituted by, for example, a fuse element which can be blown by a laser or electrically, and is selectively blown according to a mode to be set in a manufacturing process.

According to the above configuration, each switch element is turned on / off by the reset signal RST output when the power is turned on.
The initial value corresponding to the OFF state is determined by each D flip-flop 7.
2, 73 and 74 are automatically set. However, in this case, the setting contents of the mode register are fixed, and the contents of the D flip-flops 72, 73 and 74 cannot be rewritten.

FIG. 7 shows a mode register configuration diagram when the configuration is simplified and the flip-flop is omitted.

The mode register 91 includes six switch elements 92 to 97. The switch elements 92 and 93 form a set. One end of each of the two switch elements is connected to a power supply potential and a ground potential, respectively, and the other end is commonly connected to output a burst length. The switch elements 94 and 95 form a pair. One end of each of the two switch elements is connected to the power supply potential and the ground potential, and the other end is connected in common to form a wrap type output. I have. Further, switch elements 96 and 97 form a pair. One end of each of the two switch elements is connected to a power supply potential and a ground potential, respectively, and the other end is connected in common to provide a CAS latency output. I have.

Next, the configuration of the mode register selection circuit 42 will be described.

The mode register selection circuit 42 is a circuit that detects the power supply potential of the memory and outputs a selection signal Sn corresponding to the level of the power supply potential.

FIG. 8 is a configuration diagram showing one configuration example of the mode register selection circuit when the number of mode registers is "3".

Table 1 below shows the operation of the mode register selection circuit shown in FIG.

[0040]

[Table 1]

As shown in Table 1, when the power supply potential Vcc is
cc <Vb1 (first determination potential), Vb1 <Vcc <Vb
2 (second determination potential) and the mode register to be selected is switched in each case of Vcc> Vb2.

In FIG. 8, reference numeral 101 denotes a power supply potential Vcc.
Is a first power supply potential detection circuit which detects whether or not the power supply potential Vcc exceeds the second determination potential Vb2 and outputs a detection output signal VD1.
1 to detect whether the output signal VD2 exceeds
Is a second power supply potential detection circuit that outputs the same. Detection output signals VD from the two power supply potential detection circuits 101 and 102
1 and VD2 are decoded by the three AND gates 103, 104 and 105, so that any one of the selection signals S1, S2 or S3 is output according to the level of the power supply potential.

FIG. 9 is a circuit diagram of the power supply potential detection circuit.

As shown in the figure, k N-type MOS transistors TN1,..., TNk have their gates and drains connected, and their sources and drains are connected in series between the ground potential GND and the node Va. Have been. A resistor R is connected between the power supply potential Vcc and the node Va, and the node Va is connected to an input of the inverter INV. The output signal of the inverter INV is the detection output signal VD.

Next, the operation of the power supply potential detection circuit will be described.

FIG. 10 is an explanatory diagram of the operation of the power supply potential detection circuit.

As the power supply potential Vcc rises, the node Va
Has k potentials of N-type MOS transistors TN1 to TNk
And saturates. On the other hand, inverter I
The inversion potential of NV rises as shown in FIG.
When cc rises to the determination potential Vb, the relationship between the potential of the node Va and the inverted potential of the inverter INV is inverted,
The level of the output signal VD is inverted, and changes from “Low” level to “High” level. Therefore, the present detection circuit outputs a "Low" level detection output signal VD when the power supply potential Vcc is equal to or lower than the determination potential Vb. On the other hand, when the power supply potential Vcc exceeds the determination potential Vb, A "High" level detection output signal VD is output. An arbitrary judgment potential Vb can be set by adjusting the number of stages of the N-type MOS transistor TN or the resistance value of the resistor R in FIG.

Finally, the configuration of the selector 43 will be described.

FIG. 11 is a diagram showing the configuration. As shown in the figure, it is composed of three N-type MOS transistors 111, 112 and 113 which are selectively turned on in accordance with a selection signal Sn (S1 to S3) from the mode register selection circuit 42. Incidentally, in FIG.
And MD3 are output signals from each mode register shown in FIG. 4, and SS is an output signal to the control logic 18. For example, when the power supply potential Vcc is Vcc
At <Vb1, only the selection signal S1 goes to the “High” level, whereby only the N-type MOS transistor 111 conducts, and the output signal MD1 of the mode register 411 is used as the output signal SS of the selector 43 as the control signal. Logic 18 is provided.

For example, the first determination potential V in the present memory
b1 is 2.7 V, and the second determination potential Vb2 is 4.
If the access time is 0 ns and the access time is 30 ns at a power supply potential of 2.5 V, 20 ns at 3.0 V, and 10 ns at 5.0 V, the clock frequency becomes 100 ns.
MHz (period 10 ns), the mode register 411
(3) is added to the CAS latency of (MD1).
The CAS latency of the mode register 412 (MD2) is set to "2", and the mode register 413 (MD3)
Are initially set to "1" for the CAS latency. When this memory is used at a power supply potential of 2.5 V, the mode register selection circuit 42 sets the selection signal S1 to "High" level, and the mode register 4
11 (MD1) is selected by the selector 43 and CA
The S latency is set to “3”. Similarly, when the present memory is used at the power supply potential of 3.0 V, the mode register 412 (MD2) is selected, the CAS latency is set to “2”, and when the memory is used at the power supply potential of 5.0 V, the mode is set to When the register 413 (MD3) is selected, C
The AS latency is set to “1”. in this way,
The optimum CAS latency is automatically set according to the power supply potential without the need for setting in the initialization routine.

The operation will be described below with reference to the operation timing chart of FIG.

A rise of the power supply potential Vcc generates a reset signal RST, and an initial value is set in each mode register. Then, with the stable power supply potential Vcc,
One of the selection signals S1, S2, and S3 goes to a "High" level. At a power supply potential of 2.5 V, the selection signal S1 becomes "
When the power supply potential is 3.0 V, the selection signal S2 is at the “High” level, and when the power supply potential is 5.0 V, the selection signal S3 is at the “High” level. After the register is selected and the column address strobe signal CAS / transitions to the "Low" level, the column address AY is input, and after the CAS latency of the selected mode register, the data D is output.
0 to D3 are output.

In the above description, the case where the number of mode registers is three is taken as an example, but it is needless to say that the number of mode registers can be set to an arbitrary number of two or more.

FIG. 13 is a schematic configuration diagram of a clock synchronous mask ROM which is another embodiment of the clock synchronous memory of the present invention.

In the figure, 121 is a memory cell array,
122 is a row decoder, 123 is a column decoder,
124 is a row address buffer, 125 is a column address buffer.
Address buffer, 126 is a data control circuit, 127
Is a data input / output buffer, 128 is control logic, and 129 is a mode setting unit including a mode register. SS is an output signal (operation mode signal) of the mode register in the mode setting section 129, and is input to the control logic 128. Thus, the operation in the set mode is performed.

FIG. 14 is a simplified block diagram showing the configuration of mode setting section 129 in the clock synchronous mask ROM shown in FIG.

The mode setting section 129 has n mode registers 1411, 1412,..., 141n, and different operation modes are set in the mode registers. 142 is a mode register selection circuit,
The selector 143 is controlled by the selection signal Sn from the mode register selection circuit 142, and the output signal (operation mode signal) M from any of the n mode registers is output.
, Or MDn is selected and the selected output signal S
S is input to the control logic 128. Thus, the operation in the operation mode set in the selected mode register is performed.

The clock synchronous mask RO of this embodiment
In M, the initial values of the mode registers 1411 to 141n are set in the step of writing the code data of the memory cells. Generally, writing of code data of a mask ROM is performed by implanting impurity ions of the same conductivity type as the substrate (well) into the channel portion of the memory cell transistor. For example, a NOR type N-channel MO
In the SFET memory cell, the memory cell is turned on / off depending on whether boron (B) ions, which are P-type impurities, are implanted.
Turn off.

The mode register in this embodiment has the same configuration as that shown in FIG. 6 or FIG. 7 (note that it may have the same configuration as that shown in FIG. 5). ), The configuration of the switch element is different. That is, in the present embodiment, the switch element is the same MOSFET as the MOSFET constituting the memory cell of the mask ROM.
T, which is selectively turned on / off according to the initial value of each operation mode. That is, at the time of writing the code data in the memory cell, the on / off setting of each switch element is performed simultaneously (with the same mask) by selectively implanting impurity ions into the channel portion of the transistor constituting the switch element. It is what is being done.

The mask ROM is provided according to the specifications of the user.
Code data is written in the manufacturing process. Normally, at the time of this writing, the usage form such as the operating frequency of the mask ROM is determined, so that the optimum latency according to the power supply potential or the like can be set. Also, the mask RO
In M, since a write operation is not normally performed, if a system capable of setting a mode register by an initial routine is used, the circuit may be complicated. Therefore, the system and the memory configuration can be simplified by the configuration in which the mode register is not set by the initial routine in the present invention.

The configurations of the mode register selection circuit 142 and the selector 143 in the present embodiment are the same as those in the above-described embodiment.

[0062]

As described in detail above, the clock synchronous memory of the present invention has the mode register for setting the operation mode, and operates in synchronization with the clock input in the operation mode set in the mode register. In a clock synchronous memory that performs data input / output by using a plurality of mode registers in which operation modes different from each other are set, and a power supply potential detection circuit, the power supply potential detection circuit A mode register selection circuit for selecting a predetermined mode register from the plurality of mode registers. According to the clock synchronous memory of the present invention, the plurality of mode registers Operation modes such as a predetermined latency are set in advance, and any one of the mode registers is selected according to the power supply potential. By, according to the power supply potential, in which it is possible to set such an optimum latency. In addition, since it is not necessary to prepare a plurality of types of devices each having a different operation mode for each device specification, it is only necessary to prepare a single type of device. Is eliminated.

The clock-synchronized read-only memory of the present invention has a mode register for setting an operation mode, and a clock for outputting data in synchronization with a clock input in the operation mode set in the mode register. A synchronous read-only memory, comprising: a plurality of mode registers in which different operation modes are set; and a power supply potential detection circuit, wherein the plurality of mode registers are provided in accordance with a power supply potential detection signal from the power supply potential detection circuit. And a mode register selection circuit for selecting a predetermined mode register among the above-mentioned mode registers, wherein the contents of each of the mode registers are set at the time of writing the code data in the memory cell. According to the clock-synchronized read-only memory, a plurality of mode registers are provided,
By setting a predetermined operation mode such as latency in advance, and selecting one of the mode registers according to the power supply potential, it is possible to set the optimum latency etc. according to the power supply potential. It is. In addition, since it is not necessary to prepare a plurality of types of devices each having a different operation mode for each device specification, it is only necessary to prepare a single type of device. Is eliminated. Furthermore, the mode register can be set without increasing the number of new manufacturing steps, and an increase in chip cost can be suppressed.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram of a synchronous DRAM which is an embodiment of a clock synchronous memory according to the present invention.

FIG. 2 is a schematic configuration diagram of a conventional synchronous DRAM.

FIG. 3 is a configuration diagram of a mode setting unit in a conventional synchronous DRAM.

FIG. 4 shows a synchronous DRA according to an embodiment of the present invention.
FIG. 4 is a configuration diagram of a mode setting unit in M.

FIG. 5 is a configuration diagram showing a configuration example of a mode register in the mode setting unit.

FIG. 6 is a configuration diagram showing another configuration example of the mode register in the mode setting unit.

FIG. 7 is a configuration diagram showing still another configuration example of a mode register in the mode setting unit.

FIG. 8 is a configuration diagram showing a configuration example of a mode register selection circuit in the mode setting unit.

FIG. 9 is a configuration diagram of a power supply potential detection circuit included in the mode register selection circuit.

FIG. 10 is an operation explanatory diagram of the power supply potential detection circuit.

FIG. 11 is a configuration diagram showing a configuration example of a selector in the mode setting unit.

FIG. 12 is an operation timing chart in the synchronous DRAM which is one embodiment of the clock synchronous memory of the present invention.

FIG. 13 is a schematic configuration diagram of a clock synchronous mask ROM which is another embodiment of the clock synchronous memory of the present invention.

FIG. 14 is a configuration diagram of a mode setting unit in the clock synchronous mask ROM.

[Explanation of symbols]

 19 Mode setting section 411-41n Mode register 42 Mode register selection circuit 43 Selector 129 Mode setting section 1411-141n Mode register 142 Mode register selection circuit 143 Selector

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G11C 11/407

Claims (3)

(57) [Claims] 1. A clock synchronous memory which has a mode register for setting an operation mode and performs data input / output in synchronization with a clock input in the operation mode set in the mode register. A mode register including a plurality of mode registers in which modes are set and a power supply potential detection circuit, and selecting a predetermined mode register among the plurality of mode registers in accordance with a power supply potential detection signal from the power supply potential detection circuit A clock synchronous memory comprising a selection circuit. 2. A clock-synchronous read-only memory having a mode register for setting an operation mode and outputting data in synchronization with a clock input in the operation mode set in the mode register. A mode including a plurality of mode registers in which operation modes are set, and a power supply potential detection circuit, and selecting a predetermined mode register among the plurality of mode registers according to a power supply potential detection signal from the power supply potential detection circuit A clock synchronous read-only memory, comprising: a register selection circuit, wherein the contents of each of the mode registers are set when code data is written to the memory cell. 3. The mode register includes a MOS transistor, and the contents of the mode register are set by the MOS transistor.
This is performed by selectively implanting impurity ions of a type different from the channel type of the MOS transistor into the channel portion of the transistor, and the impurity ions are implanted using the same mask as that for writing the code data. 3. The clock-synchronous read-only memory according to claim 2, wherein: