JPH0289291A - Static random access memory - Google Patents

Abstract

PURPOSE:To write '0' or '1' into every memory cells at one cycle by making into a static random access memory (SRAM) to which a clear function circuit is added. CONSTITUTION:An address decoder is inhibited in response to a clear signal, every memory cells are activated, and a clear function circuit 9 to write same data into every memory cells is provided. When a clear signal CLR is made into '1', the OR circuit 21 of the clear function circuit 9 inhibits every signals of word lines from a row decoder 16 and a column coder 17, makes a word line 6 into '1', and every transfer gates of a memory cell 15 are turned on. On the other hand, in a circuit 7 consisting of an AND circuit 22, a NOT circuit 23 and an OR circuit 24 in the clear function circuit 9, D11 passing through a write circuit 18 is inhibited, a node 3 is made into '0' and a node 4 is made into '1'. Thus, every memory cell 15 can be written '0' or '1' in one cycle.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to static random access memory (hereinafter referred to as
(referred to as SRAM).

[Prior Art] In a conventional SRAM, when write data in the bit direction is all "0" or "1" regardless of the word, the data is written for each word.

[Problems to be solved by the invention] Therefore, even if you want to clear all memory cells to "0", all words are sequentially decoded and written. (
The disadvantage is that it takes a time equal to (writing cycle) x (number of words).

[Differences between the invention and the prior art] In contrast to the above-mentioned conventional SRAM, the present invention sets all memory cells to "0" or "0" in a write cycle for one word.
Clear to 1.

[Means for Solving the Problems] The static random access memory of the present invention has a plurality of memory cells and an address decoder that selects an arbitrary memory cell from among the memory cells. The present invention is characterized by having a clear function circuit that inhibits the address decoder in response to a signal to activate all of the memory cells and writes the same data to all of the memory cells.

[Embodiment] FIG. 1 shows an embodiment of an SRAM circuit with a clear function according to the present invention. AO, AI, ...Ai is the address signal,
\VEN is the write enable signal, D.

1 to DOj are output read data signals, and DIl to DIn are input ride data signals. CLR is a clear signal added in the present invention. The clear function circuit portion added in the present invention is a portion 9 surrounded by a chain line in the figure. This circuit 9 is an example in which "0" is written into all memory cells 15 of a large number of memory cells 15 arranged in a matrix.

The operation of this embodiment will be described. When the clear signal CLR becomes "1", the OR circuit 21 of the clear function circuit 9 inhibits all the word line signals from the row decoder 16 and column decoder 17, sets the word line 6 to "1", and clears all the memories. Transfer gate 10 of cell 15 is turned on. On the other hand, the AND circuit 22 and N in the clear function circuit 9
In the circuit 7 consisting of the OT circuit 23 and the OR circuit 24,
The Dll that has passed through the write circuit 18 is inhibited, and the node 3 becomes "0" and the node 4 becomes "1".

The column selectors 20 are all open because the column decoder 17 is inhibited, and the digit lines di and d2 are "0" and the digit lines di and d2 are "1", respectively.
Therefore, “0” is written to all memory cells 15. In other words, node 11 is "0", node 1
2 becomes “1” and each word has “0” “0” “0”
... is written. In addition, the write enable signal＼
VEN will also be inhibited if CLR becomes "1".

Further, the column selector in the figure has a 4-1 selector configuration. Further, circuit 7 and circuit 8 indicate the same circuit.

FIG. 2 shows a circuit for writing "1" into all memory cells 15, and corresponds to the circuit 7 in FIG. 1. , to ND
Outputs of circuit 22 and OR circuit 24 and digit lines di and d2
. . 2 cloves, ■ . . . Which connections are opposite to the example shown in FIG. If this circuit is placed in each bit, "1", "1", "1", etc. will be written in each word.

In addition, if the circuit 7 in FIG. 1 and the circuit in FIG.
” can be written in one cycle.

FIG. 1 shows an SRAM with a clear function according to an embodiment of the present invention.
FIG. 2 is a circuit diagram of an SRA according to another embodiment of the present invention.
FIG. 2 is a circuit diagram showing the main parts of M.

AO, AI, .

CLR・・・・・ 'vVEN　・　・・・・ DOI, DOj DTl,DI,i 7, 8 ・ ・ ・ ・ 9　・　・　・　ψ　・・ ...address signal, ・・Clear signal, write enable signal, lead data, light data, "0" writing circuit, Clear function circuit.

[Effects of the Invention] As explained above, the present invention makes it possible to write "0" or "1" to all memory cells in one cycle by providing an SRAM with a clear function circuit added.

Claims (1)

[Claims] In a static random access memory having a plurality of memory cells and an address decoder that selects an arbitrary memory cell from among the memory cells, the address decoder is inhibited in response to a clear signal so that all of the memory cells are disabled. A static random access memory characterized by having a clear function circuit that activates and writes the same data to all of the memory cells.