JPS6379299A - Semiconductor memory - Google Patents
Semiconductor memoryInfo
- Publication number
- JPS6379299A JPS6379299A JP61225363A JP22536386A JPS6379299A JP S6379299 A JPS6379299 A JP S6379299A JP 61225363 A JP61225363 A JP 61225363A JP 22536386 A JP22536386 A JP 22536386A JP S6379299 A JPS6379299 A JP S6379299A
- Authority
- JP
- Japan
- Prior art keywords
- row
- column
- decoder
- address
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 13
- 230000015654 memory Effects 0.000 abstract description 9
- 230000002226 simultaneous effect Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000006870 function Effects 0.000 description 1
Landscapes
- Semiconductor Memories (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体メモリ特に、読み出し％ｉ＠込み可能
な半導体メモリに関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to semiconductor memories, and in particular to readable and writable semiconductor memories.
従来、この種の半導体メモリの４き込み動作は一回で１
つのアドレスに対して行わｎる＝うになっていた。Conventionally, this type of semiconductor memory has four write operations at one time.
It was done for one address.
〔発明が）Ｖ４決しょうとする問題点〕一方、最近、半
導体メモリの高速化にともない。[Problems that the invention is trying to resolve with V4] On the other hand, recently, semiconductor memories have become faster.
半専体メモリ％−記憶装置としてではなく、機能の変更
が任意な時に可能な論理回路として使用する用途が広が
りつつある。この工うな用途では、電源投入後、半導体
メモリの内容が不定であるために初期化ｒ行う必要があ
るが、従来Ｑ半４体メそりでは、−回の書き込み動作で
１つのアドレスに対して誉き込み勿行う九め、すべての
アドレスを初期化するためには、多数回の省き込み動作
を行う必要があり、１００間がかかるという欠点がある
。Semi-dedicated memory % - It is increasingly being used not as a storage device, but as a logic circuit whose function can be changed at any time. In this unconventional application, since the contents of the semiconductor memory are undefined after the power is turned on, it is necessary to initialize the semiconductor memory, but in the conventional Q half-quadram system, one address can be written in - times. Ninth, in order to initialize all the addresses, it is necessary to perform the saving operation many times, which has the disadvantage that it takes about 100 minutes.
ま九、初期化を行うための回路も複雑となる。Also, the circuit for initialization becomes complicated.
本発明の目的に、この工うな欠点全除去し、短時間で容
易に初期化が可能な半導体メモＩＪ ’ｌｚ提供するこ
とにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory IJ'lz that completely eliminates these disadvantages and can be easily initialized in a short time.
〔問題点ｌ１ｌ−解決するための手段〕本発明に孟る半
導体メモリは、すべてのアドレスに対し、同時に同一デ
ータの書き込み七行う手段七備えることにＬり構成さ牡
る。[Problem 11l - Means for Solving] The semiconductor memory according to the present invention is configured to include means for simultaneously writing the same data to all addresses.
以下に、１面を用いて本発明忙説明する。 The present invention will be explained below using the first page.
第１図は、本発明による半導体メモリの−実施例七示す
ブロック図であるｏｌは行デコーダ、２は列デコーダ、
３はメモリ素子、４はトランスファゲート、５はゲート
回路である０外部から入力さｎるアドレス情報は１行ア
ドレス６と列アドレス７に分割さｎｌそｎぞｎ行デコー
ダ１１列デコーダ２に入力される。データ入出力信号８
はトランスファゲート４に通して、すべての列入出力信
号９と接続することが可能になっている０行デコード出
力１０、列デコード出力１１はそｎ−ｔＪｎ行デコーダ
１、列デコーダ２の解読結果が出力さｎ１行アドレス６
、列アドレス７で選択さｎる１つの出力だけが能動状態
となる。ゲート回Ｗ＆５は２つの入力のうち少なくとも
どちらか一方の入力が能動状態となり九時、出力を能動
状態にするＬう栴取されており、−力の入力には、行デ
コード出力１０、あるいは列デコード出力１１が接続さ
ｔし、他方の入力には、同時選択指定信号１２が縁続式
ｎており、出力は行選択信号１３ろるいはトランスファ
ーゲート４のゲート入力に接続さｎている０回時選択指
定信号１２が受動状態の時には、行選択信号１３のうち
１つだけが能動状態となり、トランス７アゲート４も１
つだけがオン状態となり。FIG. 1 is a block diagram showing a seventh embodiment of a semiconductor memory according to the present invention. ol is a row decoder, 2 is a column decoder,
3 is a memory element, 4 is a transfer gate, and 5 is a gate circuit. 0 Address information input from the outside is divided into 1 row address 6 and column address 7 and input to each row decoder 11 column decoder 2. be done. Data input/output signal 8
can be passed through the transfer gate 4 and connected to all column input/output signals 9.0 row decode output 10 and column decode output 11 are the decoding results of n-tJn row decoder 1 and column decoder 2. outputs n1 line address 6
, only one output selected by column address 7 is active. The gate circuit W & 5 is connected to the output when at least one of the two inputs is active and the output is active. The decode output 11 is connected to the other input, and the simultaneous selection designation signal 12 is connected to the other input, and the output is connected to the row selection signal 13 or the gate input of the transfer gate 4. When the time selection designation signal 12 is in the passive state, only one of the row selection signals 13 is in the active state, and the transformer 7 agate 4 is also in the active state.
Only one is on.
列入出力信号９のうち１つだけデータ入出力官号８に接
続さｎ１交点にあるメモリ素子３０１つだけに対してデ
ータの入出力を行うことができる０回時選択指定信号１
２が能動状態の時には、行デコード出力１０、列デコー
ド出力１１の状態にかかわらず、すべての行遍択信号１
３が能動状態とナク、スべてのトランスファゲート４が
オン状態となり、すべての列入出力信号９とデータ入出
力信号８が接続さｎた状態になり、データ入出力信号８
に加えらｎｆｃデータｔすべてゐメモリ素子３に書き込
むことが可能となる０
〔発明の効果〕
以上説明し７′ＣＬうに１本発明による半導体メモリは
、同時選択信号を能動状態にし次状態で１回のデータＷ
き込みで行うことにＬり、すべてのアドレスに対して同
一のデータｔ−ｉｔき込むことができ、内容の初期化が
非常に短時間で容易に行うことが可能となる。Only one of the column input/output signals 9 is connected to the data input/output code 8, and data can be input/output to only one memory element 30 at the n1 intersection.0 time selection designation signal 1
2 is in the active state, all row selection signals 1 are
3 is in the active state, all transfer gates 4 are in the on state, all column input/output signals 9 and data input/output signals 8 are connected, and the data input/output signal 8 is in the active state.
In addition to this, all NFC data t can be written into the memory element 3. [Effects of the Invention] As explained above, the semiconductor memory according to the present invention makes the simultaneous selection signal active and writes 1 in the next state. times data W
Since this is done by reading, the same data t-it can be written to all addresses, making it possible to initialize the contents easily in a very short time.
ｊｇ１図は本発明の一実施例のブロック−であるＯｌ・
・・・・・行デコーダ、２・・・・・・タリデコーダ、
３・・・・・・メモリ素子、４・・・・・・トランスフ
ァケート％ ５・・・・・・ゲート回路、６・・・・・
・行アドレス、７・・・・・・列アドレス、８・・・・
・・データ入出力信号、９・・・・・・タリ入出力信号
、１０・・・・・・行デコード出力、１１・・・・・・
列デコード出力％１２・・・・・・同時選択指定信号、
１３・・・・・・行選択信号０Figure jg1 is a block diagram of an embodiment of the present invention.
...Row decoder, 2...Tari decoder,
3...Memory element, 4...Transfer rate 5...Gate circuit, 6...
・Row address, 7...Column address, 8...
...Data input/output signal, 9...Tari input/output signal, 10...Row decode output, 11...
Column decode output %12...simultaneous selection designation signal,
13...Row selection signal 0
Claims (1)
みを行う手段を備えることを特徴とする半導体メモリ。A semiconductor memory characterized by comprising means for simultaneously writing the same data to all addresses.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61225363A JPS6379299A (en) | 1986-09-22 | 1986-09-22 | Semiconductor memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61225363A JPS6379299A (en) | 1986-09-22 | 1986-09-22 | Semiconductor memory |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6379299A true JPS6379299A (en) | 1988-04-09 |
Family
ID=16828169
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61225363A Pending JPS6379299A (en) | 1986-09-22 | 1986-09-22 | Semiconductor memory |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6379299A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0289291A (en) * | 1988-09-27 | 1990-03-29 | Nec Corp | Static random access memory |
-
1986
- 1986-09-22 JP JP61225363A patent/JPS6379299A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0289291A (en) * | 1988-09-27 | 1990-03-29 | Nec Corp | Static random access memory |
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