JPS59231791A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To simplify an input operation of address information by designating only the head one of the addresses which receive continuous accesses. CONSTITUTION:An input terminal 10 for address information is provided together with an address information decoder 15, a memory cell array 17 for storage of information, an input/output circuit 16 for memory information, a logical circuit which controls the input and output of memory information, and an address counter 31 which supplies the output signal of an address terminal 11 to the decoder 15 in the form of the set/reset signal. When the memory information is read out from and written to the cell 17 for continuous addresses, only the head address of the memory cell with which the reading or writing action is carried out is designated to perform the continuous reading/writing actions.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a set/reset signal between an address terminal and a decoder, in which an address signal from the address terminal is used as a set/reset signal, and an output signal is used as an input signal of the decoder.
The present invention relates to a semiconductor memory device equipped with a resettable counter (hereinafter referred to as an address counter).

FIG. 1 shows a conventional synchronous semiconductor memory device having a configuration of 1024 words x 4 bits. FIG. 2 is a timing chart of the semiconductor memory device shown in FIG. The operation of the semiconductor memory device shown in FIG. 1, particularly the read operation, will be explained below using FIG. 2.

10 in FIG. 1 is an address terminal, the signal of which is input to the address latch circuit 14. This latch circuit is the i terminal 12
The address information is latched at the falling edge of the signal. 21 shows the address information inputted from the address terminal 10, and 22 shows the aX signal inputted to the 0Σ terminal 12. The address information is valid only for a certain period of time before and after the fall of the i signal, and may be either no or low at other times. Address information is transmitted from the latch circuit 14 to the row decoder 15 and column decoder 16, and four memory cells in the memory cell array 17 are selected. Next, the storage information stored in the selected memory cell is outputted to the data input/output terminal 11 through the input/output circuit 16. FIG. 24 shows the stored information output to this data input/output terminal 11. Terminal 13 of FIG. 1 is a four-terminal and is held high during read operations, as indicated by signal 26.

In such a conventional semiconductor memory device, when reading storage information at several consecutive addresses, address information must always be input to the address terminal 11 before reading storage information at each address. did not become. This has made inputting address information complicated. Furthermore, conventional semiconductor memory devices have the same drawbacks as in read operations when writing storage information to several consecutive addresses.

The present invention eliminates these drawbacks of conventional semiconductor memory devices. Therefore, an object of the present invention is to provide a memory in which a read operation or a write operation is performed when storing information is successively read from memory cells at consecutive addresses or when storing information is continuously written to those memory cells. An object of the present invention is to provide a semiconductor memory device that enables continuous read or write operations by specifying only the starting address of a cell.

The present invention provides a terminal for inputting address information, a decoder for decoding the address information, a memory cell array for storing memory information, an input/output circuit for writing or reading the memory information, and a decoder for decoding the address information. In a semiconductor memory device, an address signal from the address terminal is used as a set/reset signal between the address terminal and the decoder, and an output signal is used as a set/reset signal between the address terminal and the decoder. An object of the present invention is to provide a semiconductor memory device equipped with an address counter that receives an input signal.

The present invention will be described in detail below based on an embodiment. FIG. 3 is an embodiment of the present invention. Circuits that are the same as those in FIG. 1 are given the same numbers. Figure 4 is Figure 3 Address Counter 3
1, and FIG. 5 shows a small timing chart of the address counter. FIG. 6 is a timing chart of the read operation of this embodiment. The operation of this embodiment will be explained below using these figures.

When performing a read operation, the /7 terminal 13 is kept high as shown at 61, and the signal 60 is input to the address terminal. Address information input to the address terminal is latched into the address counter 31 at the rising edge of the signal 50 at the address ride enable bar i terminal 30. Also n
Signal 51 must go from high to low before AWE signal 50 rises. FIG. 6 Address signal 60 is A
This indicates that only address information for a certain period of time before and after the rise of the WF+ signal 50 is valid. The address 1 set in the address counter 31 in this manner is input to the row decoder 15 and column decoder 16. After that, the address information is decoded and the memory cell array 17
Four memory cells are selected from among them, and stored information is outputted to the data input/output terminals as shown in FIG. 662.

In order to read the memory information at the next consecutive address,
First, the terminal 12 is changed from low to high. At this time, the address counter 31 is updated. A signal 33 in FIG. 3 serves as a clock signal for the address counter 31.

By keeping OE high for a certain period of time and then setting it low again, the stored information at the next address is read out to the data input/output terminal after a certain period of time. In this case, unlike reading the first address, there is no need to input address information to the address terminal 1D (the AWB terminal remains high).

The stored information from the sixth address onwards can also be read out in the same way as reading from the next address. Regarding the write operation, 1,
The only difference is that the 4-terminal 16 is set low and storage information is input to the data input/output terminal, and the other operations are exactly the same as the read operation.

FIG. 4 is an example of an address counter, and the figure shows a 3-bit counter. 32°36 is Fig. 3 3
This is the same signal as 2.33.

40 is a set/resettable flip-flop. 32 controls writing of address information to this flip-flop 40. When signal 62 is low, address information is written to seven flip-flops 40. 33 is a clock signal of this address counter, and 41, 42, 45 are output signals. Fifth
Figure 50 #52 corresponds to Figure 4'' and 2.55, respectively.
53, 54. , 55 correspond to 41.42.43, and 51 is the 01 signal. When accessing the memory cell at the first address, a low pulse is input to the signal 50 in order to write address information into the address counter.

When accessing the memory cell at the next address or later, there is no need to write address information to the address counter, so the signal 50 is kept high. This update of the address counter is performed at the rising edge of the n signal 51.

FIG. 7 shows another embodiment of the present invention, which is an asynchronous semiconductor memory device having a configuration of 1024 words x 4 bits. FIG. 8 is a timing chart at the time of reading in this embodiment.

In this embodiment, the clock signal at the terminal 70 is used as the clock signal for the address counter 61. The signal 80 input to the n terminal 12 is kept low during the read state, and the address counter is updated at the rising edge of the signal 81 (6). In this embodiment as well, by specifying only the first address, the stored information from the next address onwards can be read out continuously by simply inputting a low pulse to one signal. Address information at the first address is input at the rising edge of the m signal 50, and only address information for a certain period of time before and after this is valid. When accessing a memory cell at the next address or later, the m signal 50 is kept at no/y, and the address signal may be high or low. Furthermore, the stored information is output to the data input/output terminal 11 after a certain period of time after the OL signal 81 falls.

Although the embodiments of the present invention have been described above, the present invention is not limited to these embodiments. In the embodiment, only bit random access memory was mentioned in 4, but the present invention can also be applied to random access memory, read-only memory, etc., which have a storage capacity other than pits.

According to the present invention, when accessing several consecutive addresses, there is no need to input address information before accessing each address. By specifying only the first address of addresses to be accessed consecutively, it is only necessary to input a bipulse to the clock signal 33 of the access path address counter from the next address onwards. Therefore, the input operation of address information, which has been complicated up to now, is greatly simplified. As described above, the semiconductor memory device of the present invention is much easier to use than conventional semiconductor memory devices.

[Brief explanation of drawings]

Figure 1 shows a conventional semiconductor memory device. 10...Address terminal 11...Data input/output terminal 12...N terminal 13...Event terminal Figure 2 shows the timing of the semiconductor memory device shown in Figure 1. chart. 3 and 7 show embodiments of the present invention. 31...Address counter 32...Address information input control signal 33...
...Address counter clock signal 70...
. . .ol terminal 71 . . . Address counter clock signal FIGS. 6 and 8 are timing charts of the embodiment. Figure 4 shows an example of an address counter. FIG. 5 is a timing chart of the address counter shown in FIG. Above father-in-law 11 figure name 71 beat 41 sucrose -

Claims (1)

[Claims] (Re) A terminal for inputting address information (hereinafter referred to as an address terminal), a decoder for decoding address information, and a memory cell array for storing storage information,
In a semiconductor memory device comprising an input/output circuit for writing or reading out the storage information, and a control circuit for controlling the input/output of the storage information, the A semiconductor memory device comprising a set/resettable counter whose address signal from an address terminal is used as a set/reset signal and whose output signal is an input signal of the decoder. (2) As the clock signal of the counter, a signal from a terminal (hereinafter referred to as a chip enable bar i terminal or a chip enable OF terminal) that controls the operating state and standby state of this semiconductor memory device is used; The semiconductor memory device according to item 1, wherein the counter is counted up or down at the rising edge or falling edge of a signal. (3) Using a signal from a terminal other than the i terminal or the OE terminal as the clock signal of the counter,
2. The semiconductor memory device according to claim 1, wherein the counter is counted up or down at the rising edge or falling edge of this signal.