JPH04205785A - Semiconductor information storing device - Google Patents

Abstract

PURPOSE:To accomplish high speed access by providing a circuit which generates a signal for inhibiting access to the outside till a refresh reset time elapses since a part of address signal is changed. CONSTITUTION:An address decoding part 16 decodes the high-order address of the address signal which is given from an external device and generates a signal for selecting one of plural PSRAM chips M1-M8. A refresh control circuit 15 generates a refresh selection signal to the PSRAM chip which is not selected by the signal. In the case of accessing the PSRAM chip which is in a cell refresh state, a signal is outputted from an inverted BUSY signal terminal 10 till the refresh reset time Trfs elapses since the high-order address is changed. During this period, the access is inhibited. Meanwhile, in the case of consecutively accessing the same PSRAM chip, a signal for securing the refresh reset time Trfs is not outputted.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor information storage device, and more specifically, a pseudo SRAM (hereinafter referred to as PSRAM) as a storage element.
The present invention relates to a semiconductor information storage device using.

[Prior Art] Some semiconductor information storage devices such as memory cards and memory cartridges use PSRAMs as storage elements.

1) While RAM requires a glue circuit to prevent data volatilization, PSRAM requires a memory element γ
Since the refresh circuit is integrated on the same chip, there are advantages such as a simpler circuit configuration.

FIG. 4 is a block diagram showing an example of a conventional conductive information storage device using PSRAM.

The decoder 11 selects one of the addresses received from the external device.
Decode the L address (for example, -1-3 bits) and write °L to one of the ends fst-ss accordingly.
Output ゛°.

Here, the ends F81 to S8 are the enable signal terminals CEI to CE8 of the PSRAM chip M chip 8, respectively.
It is connected to one input terminal of logic gates 9a to 9h, which have output terminals connected to. The input terminal of each logic gate is connected to a chip enable signal line CE. For example, when "L" is output to terminal S1, an external device sends a chip enable signal to signal line CE.
When °L is output, the chip enable signal terminal F-CEI of the PSRAM chip M1 becomes "L", and the PSRAM chip 1 is selected as the memory chip to be accessed.

The output of the decoder 11 is also sent to the frequency control circuit 15. Output terminals RFI to RF8 of the refresh control circuit 15 correspond to output terminals 81 to 88 of the decoder 11, respectively, and 'PSRA
It is connected to the refresh enable i'iJ signal terminals of M chips M1 to M8, respectively.

If the output terminal of the decoder 11 is "H", the refresh control circuit 15 sets the output terminal of the corresponding refresh control circuit to "L9".
Set it to 1. Therefore, the fresh permission signal terminal Y of the PSRAM chip that is not the target of access is “L”.
, I9 is input.

-On the other hand, for the output terminal of the decoder 11 that is "L", only when the RFSH signal line is "L", the output terminal of the corresponding RIF 7 control circuit is "L".
Make it 11. Therefore, refreshing the PSRAM chip being accessed 1. 'shii 4. '
"J end r" is usually "HI+", but RFS
It becomes "L' only when the H signal line becomes "+L".

PSRAM chips (Ml to M8) are refresh enabled.
■When the signal terminal is “L” or “H”, it becomes a self-refresh state.In the self-refresh state, PSR
After sequentially selecting and activating memory cells by the operation of the timer circuit and refresh circuit in the AM chip, a minute signal from the memory cell is amplified by a sense amplifier,
A refresh process of returning this to the memory cells is performed for all memory cells in the chip in a period of several tens of microseconds (refresh time), and this process is repeated at a period of about several lTl5.

・On the other hand, if the refresh enable signal terminal is “H”, P
The SRAM chip becomes accessible when the chip enable signal terminal becomes "L".

In this state, writing is performed when the signal line WE becomes "L11", and reading is performed when the signal line OE (not shown) becomes "L".・When accessing a PSRAM chip, the external device interrupts the access and outputs "L" to the RFSH signal line to refresh the chip in order to prevent the data stored in the chip from volatilizing. At this time, the reflex/source control circuit 15 controls the PSR.
"L I9" is output to the refresh enable signal terminal r of the AM chip, and after the completion of the refresh r, the refresh selection signal terminal γ is set to H again.

FIG. 5 is a diagram showing a timing chart of the semiconductor information storage device of FIG. 4.

At time a', the external device is accessing the PSRAM chip M1 seven times, and regarding the output of the decoder 11, Sl is "L" and 82 to S8 are "t Ht". Regarding the outputs, RFI is "H" and RF2 to RF8 are "L11".

At time point b', the chip enable signal line is set to "L" at E.
” is output, the chip enable signal terminal CE1 of the PSRAM chip M1 becomes “L 91”, and the PSRAM
Chip M1 becomes accessible. Then, the signal line WE becomes "l, TI" and writing is performed on this chip.

At time C', the address changes and the external device
The M chip M2 will be accessed.

The decoder 11 decodes the low address and terminal S1
to "H" and terminal S2 to "L".

At this time, the refresh enable signal line RFI changes to "L", and the PSRAM chip M1 enters the self-refresh state.--The collar signal line RF2 changes to "HH".

Then, the PSRAM chip M2 rises from the self-refresh state and prepares for access.

-ょ- Here, when accessing the PSRAM during self-refresh, the PSRAM chip requires a refresh reset time Trfs, and a time 'l'rfs has elapsed since the refresh refresh permit 11J signal line becomes "H". Access is prohibited until then.

Therefore, the external circuit does not bring the chip enable signal line CE to "L" immediately after time C', but instead
Wait until the refresh reset time Trfs has elapsed, and then set the signal line CE to "L" (at time d'
).

[Problems to be Solved] However, such conventional %l/conductor information storage devices have the following problems.

The external device secures the time Trfs each time it accesses, regardless of whether or not the P S RAM chip to be accessed has changed. This caused a reduction in access speed.

The present invention is intended to solve the problems of the prior art, and uses PSRAM chips as storage elements to provide semiconductor information with high-speed access. To achieve this purpose, the semiconductor information storage device of the present invention has a plurality of PSRAM chips and a part of the address signal (10th address) applied from an external device is decoded to one of the plurality of PSRAM chips. In a semiconductor information storage device that has a decoder that generates a signal to select one PSRAM chip, and a refresh control circuit that generates a refresh selection signal to cause all PSRAM chips not selected by that signal to perform self-refresh, A circuit that generates a BUSY signal to prohibit access to an external device from the time the address changes until the refresh reset time Trfs elapses, and a BUSY signal terminal that outputs this BUSY signal to the external device. It is equipped with r.

[Operation] When accessing a PSRAM chip in a self-refresh state, a BUSY signal is output from when the - address changes until the refresh reset time T rfs, and access is prohibited during this period.

On the other hand, when accessing the same PSRAM chip continuously, the 1st address does not change, so
A BUSY signal for securing the refresh reset time T rfs is not output. In this case, the external device is
Access can be performed without waiting for the elapse of time Trfs (by setting the chip enable signal line CE to "L11").

[Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of a semiconductor information storage device of the present invention. Here, the same components as in Figure 4 are:
Represented by the same symbol.

What differs from FIG. 4 in FIG. 1 is the configuration of the circuit section that records the old address and selects one of a plurality of PSRAM chips, and is composed of a conventional decoder 11 and logic gates 9a to 9h. 19 = The former part becomes the address record section 16, and the BUSY signal terminal -J' is used to output the BUSY signal that prohibits access from the address record section 16 to external devices.
10 has been added.

FIG. 2 is a block diagram showing an example of a specific circuit configuration of the address record section 16.

In the figure, high address signal lines 12a, 12b, 1
2c are XOR gates 18a118b and 18c, respectively.
is connected to one input terminal of the XOR gate 18
The other terminal of all 8 bs 18 c is connected to the -L address signal line 12 at l 2 b 112c via delay circuits 17a and 17b 117c, respectively. The delay circuit delays the signal by the refresh reset time Trfs, and can be created by, for example, cascading 2n inverters (n is a natural number). 18 at 18 bll
The output terminals fA1B, C of each XOR gate 8c are connected to the input terminal r of an AND gate 19 whose output terminal r is connected to the BUSY terminal 10.

When the 11th address changes, the signal on at least one of the upper address signal lines changes, so the output of the XOR gate connected to that upper address signal line remains unchanged until time Trfs has elapsed since the signal changed. During this period, "L11" is output to the output terminal.

Therefore, during the period from when the 1st address changes until the refresh reset time Trfs elapses, the end J
'A1B, C at least one "L!
, 11 are output. As a result, access from external devices is prohibited.

The logic gate 20 is connected to the BUSY signal terminal 10 and the signal line R.
When FSH is not "I I, I" and receives the chip enable signal from the external wJ table device, the logic gate 9
Open the gates a to 9h and output the decoder 11 (St to
S8) is output to the chip enable signal terminal -r- (CE1 to CE8) of each PSRAM chip. Therefore, when the PSRAM chip to be accessed switches and the external device erroneously outputs a chip enable signal even though BUSY (; P accessed with
Signal line RFS to refresh SRAM chip
If a chip enable signal is erroneously output even though "L+1" is output to H, access is prevented.

FIG. 3 is a diagram showing an example of a timing chart of the μ conductor information storage device of the present invention.

At time a and time 2, the same operations as at time a' and time b' in FIG. 5 are performed, respectively.

At time C, the upper address changes and the PSRAM chip to be accessed switches from M1 to M2. At this time, the terminal A and terminal T-B in FIG. 2 change to "L". Therefore, the output of the gate 19 (ANr) becomes "L", and the output of the BUSY signal becomes significant (35 )
.

The decoder 11 decodes the upper address and outputs the terminal S1.
is changed to "H" (31), and the terminal S2 is changed to "L" (32). At this time, the refresh permission signal line RFI is “
33), and the PSRAM chip M1 enters a self-refresh state. On the other hand, the signal line RF2 is “
Changes to Htt (34). Then, the PSRAM chip M2 wakes up from the self-refresh state and prepares for access.

At time d, when the refresh reset time Trfs has elapsed from time C, the outputs of the delay circuits 17a117b become equal to the -L address signal lines 12a112b, the output terminals FA and B of the XOR gate return to "H11," and the BUSY signal is output. (36).As a result,
Access is now possible, and the external device outputs a chip enable signal (37). At this time, since both the BUSY signal terminal and the RFSH signal line are "°H",
The logic gate 20 outputs "L", and the PSRAM chip M
2, the chip enable terminal J'CE2 changes to "L". Thereafter, the external device outputs "L" to the WE signal line and writes data to the PSRAM chip 2.
゛After this write process is completed, the chip enable cable C
After E returns to "HIt" (40), when the external device continuously writes to the PSRAM chip M2, the BUSY signal is not output because there is no change in the upper address.

Therefore, the external device has a refresh reset time T
At time e, without waiting for the elapse of rfs, a chip enable signal is output to the signal line CE (41). Then, the output of the logic gate 20 becomes "L 11", and the PSR
Chip enable signal terminal CE2 of AM chip M2 is
“L It becomes. After this, the external device connects the WE signal line.”
"L" and write to PSRAM chip M2.

1. In the embodiment described above, a delay circuit in which 2n inverters are connected in series and an XOR gate are used to set the refresh reset time Trf after the upper address changes.
The circuit that outputs BUSY signal is configured by s, but
It is also possible to adopt a circuit configuration that uses a timer circuit or the like to determine the timing for outputting the BUSY signal.

In addition, in the embodiment, the same PSRAM is used continuously for a certain period of time.
When a chip is accessed, in order to prevent the data stored in the chip from volatilizing, "L++" is output to the external device or the RFSH signal line to cause the chip to refresh. Management does not necessarily have to be performed by an external device, and may be performed within the semiconductor information storage device. For example, the address decoding unit 16 may have a built-in timer circuit, and the address decoder 16 may have a built-in timer circuit to change the upper address for a certain period of time. The PS being accessed when there was no
1. Set the output terminal r of the decoder corresponding to the RAM chip to H11 to refresh the PSRAM chip and output a BUSY signal to prohibit access. +1 ability.

In this case, the PSRAM chip that is being accessed during the period from when the 1st address changes until the refresh reset time 'l' rfs elapses, and when the L address does not change for a certain period of time. A BUSY signal is output each time the .

In the embodiment, the number of PSRAM chips built into the semiconductor information storage device is eight, and accordingly, the L-order three digits of the address signal are the first address. The number of digits is not limited to this, and it goes without saying that the number of digits of the upper address may be determined as appropriate depending on the number of PSRAM chips.

[Effects of the Invention] As can be understood from the following explanation, in the microconductor information storage device of the present invention, when accessing a PSRAM chip that is in a self-refresh state, the upper address changes and then refresh is performed. Reset time 'l'r
A BUSY signal is output until fs, and access is prohibited during this period.

- On the other hand, when accessing the same PSRAM chip continuously, the -L address does not change, so
The BUSY signal for securing the refresh reset time T rfs is not output.

Therefore, when the external device continuously accesses the same PSRAM chip, it is possible to output the chip enable signal and access the same PSRAM chip without waiting for the refresh recent time to elapse. As a result, faster access speed can be achieved.

Also, since everything other than the PSRAM chip being accessed is in a self-refresh state with low power consumption,
The effect of low power consumption can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of a semiconductor information storage device of the present invention, FIG. 2 is a block diagram showing an example of a specific circuit configuration of an address record section, and FIG. 3 is a block diagram of an embodiment of a semiconductor information storage device of the present invention. FIG. 4 is a block diagram showing an example of a conventional semiconductor information storage device using PSRAM, and FIG.
FIG. 3 is a diagram showing a timing chart of the semiconductor information storage device shown in the figure. 9a+ 9bt 9c, 9d, 9e, 9L 9.
g. 9h...Logic gate, 10...BUSY signal terminal,
11... Decoder, 12... Address signal line, 13
...Data credit line, 14...Connector, 15...
Refresh control circuit, 16...Address decoding section, 17a, 17b, 17c...Delay circuit, 18a,
18b, 18cmXOR gate, ■9...AND
Gate, 20...Logic gate. Patent applicant [Representative of Maxell Co., Ltd. Patent attorney Nobu Kaji Yama] - Tomi Yamaki 1-Male

Claims (1)

[Claims] (1) A plurality of pseudo SRAM chips, a decoder that decodes a part of an address signal applied from an external device and generates a signal for selecting one of the plurality of pseudo SRAM chips, and a decoder that generates a signal for selecting one of the plurality of pseudo SRAM chips; In a semiconductor information storage device having a refresh control circuit that generates a refresh selection signal for causing all unselected pseudo SRAM chips to perform self-refresh in response to a signal for selecting one, a part of the address signal What is claimed is: 1. A semiconductor information storage device comprising: a circuit that generates a signal to the outside that prohibits access from when the value changes until a refresh reset time elapses.