JPH01237735A - Trace memory - Google Patents

Abstract

PURPOSE:To decrease the number of parts for a memory device by using a memory cell array composed of the memory cell of large capacity to a bit width at the time of parallel data writing for a memory cell unit as voluminous parallel data storing means. CONSTITUTION:A counter 1 is cleared and when a mode signal 15 is caused to be H next, the H input signal of the inverted signal 15 is inputted to a selector 9 and the selector 9 outputs the output signal of the counter 1 to decoders 4 and 5. Similarly, since the H input signal of the signal 15 masks signals 17, 18 and 20 to be H, the output control of buffers 7 and 10 becomes inactive and the trace address value outputted from the counter 1 and data to be outputted to an internal data bus are not outputted to input and output data 11. In such a condition, the data, which are desired to be stored, are continuously set to the input/output data 11 and the pulse signal of negative logic having a certain width is inputted to a trace timing signal 14. Thus, a data storing address is automatically generated and successively stored in a memory cell array 2.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a trace memory, in particular, a trace function such as an in-circuit emulator, which sequentially stores multi-bit width data every certain cycle, and when reading data, a constant bus width is used. Regarding the trace memory read by .

[Conventional technology]

There are two main types of in-circuit emulators that are generally used when developing application programs and systems for applied products using microcomputers.
There are two functions.

One is a function that runs a created application program, and then stops the execution of the application program under certain specified conditions, such as matching access addresses or data.The other is a function that starts the application program. This function sequentially stores the execution process of the application program being executed, such as execution bus cycles and various CPU statuses, and displays the stored contents on an output device such as a CRT after the storage operation is completed. Generally, the former is called the break function of an in-circuit emulator, and the latter is called the trace function.

By using the break and trace functions of such an in-circuit emulator, it becomes possible to divide a program into modules using the in-circuit emulator and verify the execution results, resulting in efficient program development. I can do things.

Now, in order to realize the tracing function of the in-circuit emulator, while the application program is running,
When a bus cycle occurs, the values of the address bus, data bus, and bus status at that time or the internal status value of the CPU may be sequentially stored in the memory, and after the storage operation is completed, the contents of the memory may be read out and displayed sequentially.

During the execution of an application program, the amount of data that must be stored in memory in parallel for each bus cycle that occurs is 100 in recent microcomputers.
It's getting a bit close. Furthermore, the depth of the trace, that is, the vertical capacity of the memory, is generally about 4 words.

Therefore, during trace operation, a memory capacity of approximately 4k×100 bits is required. Further, after the trace operation is completed, the trace data is read out by the CPU via a data bus, which is usually 8 or 16 bits wide, in order to display the trace data.

In this way, the memory device required to implement the trace function of an in-circuit emulator generally has a bit configuration of approximately word depth x 100 bits when writing data, and an arbitrary bit configuration when reading data. R with a special bit configuration of depth x 8/16 bit configuration
AM is required.

In addition, in order to generate a storage address for the parallel data group to be stored in the memory when a bus cycle occurs, a dedicated address generation circuit must be provided that increments the address by +1 according to the write timing signal output when a bus cycle occurs. In addition to the data storage address generation function, the generation circuit also holds the last address value of the trace data accumulated after the trace operation is completed.
It has a function that allows you to use this value to display a trace from the trace start point to the end point.

Conventional trace memories of this type consist of an address generation counter, a dozen or so general-purpose RAMs each having a several kilobyte x 8- to 16-bit configuration, and a plurality of general-purpose RAMs for reading data.
Several address decoders for general-purpose RAM chip selection were required to select 16 bit data.

[Problem to be solved by the invention]

In the conventional trace memory described above, since there is no multi-bit wide general-purpose RAM as a means of storing a large number of parallel data, it is necessary to use a large number of 8-bit wide general-purpose RAMs connected in parallel, including the control circuit. The disadvantage is that the number of components of the memory device increases.

In contrast to the conventional trace memory described above, the present invention uses a memory cell array composed of large-capacity memory cells in which each memory cell unit corresponds to the bit width when writing parallel data as a large number of parallel data storage means, Another difference is that by using a single memory cell array, peripheral circuits such as an address generation counter and a data selector for selecting a specific bit width when reading data can be configured in one device.

[Means to solve the problem]

The trace memory of the present invention is a trace memory in which multi-bit width data is sequentially written in a trace mode and read out with a constant width in a read mode, and includes a clearable address generation counter that operates in the trace mode. , a selector that selects the counter output or an address value input from the outside in response to a mode signal, a memory cell array in which the cell unit accessed simultaneously corresponds to the bit width at the time of the write, and the data at the time of the read. It is characterized by having a data selector that selects an array of constant width.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram of the first embodiment of the present invention, in which a counter 1.4 has a word x 64 bit memory cell array 2.
, two selectors 3 and 9, two decoders 4 and 5. The input/output controller 6 has three buffers 7, 8 and 10 other gates.

In the trace mode, the counter 1 counts up at the trailing end of the trace timing signal 14, which is a negative logic pulse, and can generate a word address value of up to 4. The selector 9 accepts the outputs of the counter 1 in the trace mode and of the address bus 12 in the read mode, and outputs them to the decoders 4 and 5. Decoder 4 and decoder 5 select six of the outputs of selector 9.
Receives and decodes each bit bit by bit, and sends it to memory cell array 2.
Outputs the row address and column address of , and selects one of the words in 4.

The input/output controller 6 inputs the output data of the buffer 8 to the internal data bus 23 to the memory cells indicated by the decoder 4 and the decoder 5, and also outputs the output data of the memory cell array 2 to the internal data bus 23. Take control. These input and output controls are controlled by the logic levels of trace timing signal 14 and read timing signal 20, respectively.

The selector 3 outputs 8-bit data selected by the address bus 13 out of the 64-bit output data output to the internal data bus 23 to the lower 8 bits of the input/output data 11 through the buffer 10.

Further, by setting the trace address read signal 17 to a low level, the output data of the counter 1 can be outputted through the buffer 7 to the lower 12 bits of the input/output data 11.

Buffers 7.8 and 10 are both three-state buffers, and are used for count address output, data input, and data reading, respectively.

Next, the operation of the circuit shown in FIG. 1 will be explained.

As mentioned in the prior art section, this memory device first sequentially stores a large amount of parallel data in each cycle, such as when a bus cycle occurs, and then sequentially reads out the accumulated data again in a certain bit width. This is the main usage method. Therefore, before performing the first parallel data storage operation, the counter 1 is cleared in order to initialize the data storage address starting point.

The clearing operation of counter 1 can be performed as follows. When the mode signal 15 is set to a low level, the negative logic trace timing signal 14 is masked to a high level by the mode signal 15 whose logic is inverted, so that the counter 1 cannot be counted up. In this state, by setting the negative logic clear signal 16 to a low level, the clear terminal of the counter 1 becomes a low level, and the output of the counter 1 becomes "0". When the counter clear operation is completed, the clear signal 16 is returned to Heil Bell.

Next, immediately before starting the parallel data storage operation, the mode signal 1
5 is considered a high level. Since the high level input signal of the mode signal 15 masks the negative logic clear signal 16 to a high level, the counter 1 cannot be cleared again in this state. Further, the high level signal of the inverted mode signal 15 is input to the selector 9, and the selector 9 outputs the output signal of the counter 1 to the decoder 4.5. Similarly, the high level input signal of the mode signal 15 is the negative logic trace address read signal 17. In order to mask the trace data read signal 18 and the data read timing signal 20 to high level, the output control of the buffers 7 and 10 becomes inactive, and the trace address value output by the counter 1 and the internal data bus 23 are output. No data is output to the input/output data 11.

64 that you want to store in the input/output data 11 in the above state
By setting the bit width data and keeping the trace timing signal 14 at a low level for a certain period of time, the output control of the buffer 8 becomes active and the input/output data 11 is input to the internal data bus 23.

The 64-bit width write data inputted to the internal data bus 23 is transferred to one memory cell with an address value "0" obtained by decoding the output data "0°" of the counter 1 by the decoders 4 and 5, and then sent to the input/output controller. Set through 6.

Next, the trace timing signal 14 returns from the low level to the high level, but at the rising edge of the signal at that time, the count value of the counter 1 is increased by 1, and at the same time, the output control of the buffer 8 becomes inactive, and the input/output data 1
1 is no longer output to the internal bus 23. Further, the input/output controller 6 also ends the write operation to the memory cell because the trace timing signal 14 becomes inactive.

In this way, by sequentially setting the data to be stored in the input/output data 11 and inputting a negative logic pulse signal with a certain width to the trace timing signal 14, a data storage address is automatically generated. , are sequentially stored in the memory cell array 2.

When all necessary data storage processing is completed, the mode signal 15 is returned to the low level again. In this state, the trace timing signal 14 is masked to a high level by the logically inverted mode signal 15, so that the write operation described above cannot be performed.

Next, the operation of sequentially reading data sequentially accumulated in the memory cell array 2 will be described.

As mentioned in the conventional technology, reading data is usually done using C
Since the PU performs this, the bit width that can be read at one time is
This is determined by the data bus width of the CPU on the reading side. In this memory device, the bit width at the time of reading is 8 bits.

As mentioned above, the memory cell array 2 is composed of 64-bit cells, so when reading, specific 8 bits out of 64 bits are selected, and the lower 8 bits of the input/output data 11 are
Must be output in bits.

The read operation can be performed as follows.

With the aforementioned mode signal 15 set to a low level, the trace address signal 17 of negative logic is set to a low level in order to read and store the address value after the write operation is completed. Chip select 19 and read timing signal 2
By setting 0 to low level, the output data of counter 1,
That is, the address value passes through the buffer 7 to the input/output data 11.
This value can be read externally because it is output to the lower 12 bits. Next, when the trace address read signal 17 is returned to high level, the buffer 7 becomes inactive and the output data of the counter 1 becomes the input/output data 11.
is not output to .

The read operation of stored data is performed as follows.

As mentioned above, since the mode signal 15 is at a low level, the selector 9 inputs the data on the address bus 12, which has a word address space in 4, to the decoders 4 and 5.
A specific memory cell in units of 64 bits is selected.

Next, chip select 19 and read timing signal 2
By setting 0 to low level, the input/output controller 6
is output-controlled, and 64-bit cell data is output to the internal data bus 23 and input to the selector 3. At this time, specific 8-bit data among 64 bits is output to the buffer 10 according to the 3-bit value of the address bus 13 for select data designation, which is input to the selector 3 at the same timing as the address bus 12.

The above input data of the buffer 10 is sent to the chip select 19.
Since the read timing signal 20 and the read timing signal 20 are both at low level, they are output to the lower 8 bits of the input/output data 11.

In this way, the address space of four words input to the address bus 12 and the specific eight of the data in units of 64 bits are
By using a 3-bit address on the address bus 13 that specifies bits, all cell data in the memory cell array 2 can be read out as a memory having a pseudo bit configuration of 32 words x 8 bits.

FIG. 2 shows a circuit according to a second embodiment of the present invention, in which a selector 22, a buffer 24, and a gate for controlling these are added to the first embodiment.

Since the basic operation of this embodiment is the same as that of the first embodiment, only the points different from the first embodiment will be explained in this section.

The selector 22 selects the 64 bits output to the internal data bus 23.
Select specific 16-bit data from the bit-width data. Further, the buffer 24 outputs the 16-bit data output from the selector 22 to the lower 16 bits of the input/output data 11. It is a buffer with output control.

The operation of clearing the counter of this memory device, the operation of writing data to the memory cell array 2, and the operation of outputting the counter value to the outside are the same as in the first embodiment.

As described above, since the data read operation is performed by the CPU, the bit width of data that can be read at one time is determined by the data bus width of the CPU on the read side.

In this memory device, the bit width at the time of reading is set to 8 bits or 16 bits depending on the logic level of the read width designation signal 21.
Bit width can be selected arbitrarily.

When reading data from the memory cell 2, if the read width designation signal 21 is at a low level, the output control of the buffer 10 becomes active and the output control of the buffer 24 becomes inactive. In this state, the same operation as in the first embodiment is performed.

Next, if the read width designation signal 21 is at a high level, the output control of the buffer 10 becomes inactive, and the buffer 2
4 output control becomes active.

At this time, among the 64-bit read data output to the internal data bus 23, specific 16 bit data selected by the selector 22 by the 2-bit select data input of the address bus 13 are input to the input/output data 11.
is output to the lower 16 bits. In other words, a pseudo bit configuration of 16 words x 16 bits is created using the address space of 4 words input to the address bus 12 and the 2-bit address value of the address bus 13 that specifies specific 16 bits of data in units of 64 bits. All cell data in the memory cell array 2 can be read out.

〔Effect of the invention〕

As explained above, the present invention uses a single memory cell array composed of large-capacity memory cells whose memory cell unit corresponds to the bit width when writing parallel data as a means for storing a large number of parallel data. This eliminates the need to use a large number of general-purpose RAMs that were previously required, and by using a single memory cell array, peripheral circuits such as an address generation counter and a data selector for selecting a specific bit width when reading data can be saved. Since the memory device can be configured with one device including the memory device, there is an effect that the number of parts of the memory device can be reduced.

[Brief explanation of the drawing]

FIG. 1 shows a circuit diagram of a first embodiment of the invention, and FIG. 2 shows a circuit diagram of a second embodiment of the invention. 1... Counter, 2... Memory cell array, 3, 9
゜22... Selector, 4.5... Decoder, 6...
・Input/output controller? , 8.10.24...Buffer, 11...I/O data, 12.13...Address bus, 14...Trace timing signal, 15.
...Mode signal, 16...Clear signal, 17...Trace address read signal, 18...Trace data read signal, 19...Chip select, 20...
- Read timing signal, 21... Read width designation signal, 23... Internal bus.

Claims (1)

[Scope of Claims] In a trace memory in which multi-bit width data is sequentially written in a trace mode and read out with a constant width in a read mode, a clearable address generation counter that operates in the trace mode; a selector that selects the counter output or an address value input from the outside in response to a mode signal; a memory cell array in which the cell unit accessed simultaneously corresponds to the bit width at the time of writing; A trace memory characterized by having a data selector for selecting an array of a constant width.