JP2000285686A - Write-in circuit of non-volatile memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent an erroneous rewriting. SOLUTION: When the contents of a prescribed one block in a flash memory 1 is rewritten, the states of 128 flags inside of a flag circuit 7 corresponding to each address of page buffers 5, 6 in one to one is detected by a flag detecting circuit 8. That is, when all flags are not varied to a prescribed logical value, rewriting operation is performed again by a control section 9 conforming to a detected signal IDALL of a logical value '0' from the flag detecting circuit 8. Thereby, rewriting data can be surely realized.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a write circuit for a nonvolatile memory.

[0002]

2. Description of the Related Art FIG. 2 is a general block diagram showing a write circuit of a nonvolatile memory.

In FIG. 2, a flash memory (10
1) has a non-volatile characteristic capable of electrically erasing data and writing / reading data, and is used for a program memory, a data memory and the like of a microcomputer. The flash memory (101) is divided into a plurality of blocks 1 to n each having a fixed storage capacity, and has a structure in which a data rewriting operation is performed for each block. For example, one block of the flash memory (101) is 128 bytes (= 1 page)
It is. The page buffer (102) has a storage capacity for one block of the flash memory (101). When rewriting the contents of one predetermined block of the flash memory (101), the page buffer (102)
New data of 8 bytes is stored.

When all contents are rewritten in units of one block, external bytes are stored in all bytes of the purge buffer (102).
The new data of 128 bytes is stored from a ROM writer or the like (step 1). The entire contents of one predetermined block to be rewritten out of the n blocks of the flash memory (101) are erased (step 2). Flash memory (10
Page buffer (102) for a given block of 1)
The new data of 128 bytes is written (step 3). It is necessary to execute three processing steps.

[0005]

However, conventionally, there is no means for confirming the storage state of the page buffer (102).
That is, some factor acts and the page buffer (10
Even if all 128 bytes of new data cannot be stored in 2), there is no way to detect this state. Therefore, there is a disadvantage that data different from the user's will is written into the rewrite target block of the flash memory (101).

[0006]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and has a characteristic capable of electrically erasing data and writing / reading data. A non-volatile memory consisting of blocks,
A buffer circuit having a storage capacity for one block constituting the nonvolatile memory and storing rewrite data of a predetermined block, and a flag corresponding to each address constituting the buffer circuit on a one-to-one basis; A flag circuit for setting a flag corresponding to the rewritten data stored address in the buffer circuit to a predetermined logical value, a flag detection circuit for detecting a state of the flag circuit, and rewriting of all addresses of the buffer circuit. According to the detection result of the flag detection circuit when not executed,
And a control circuit for re-executing a data storage operation for all addresses of the buffer circuit.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The details of the present invention will be specifically described with reference to the drawings.

FIG. 1 is a block diagram showing a write circuit of a nonvolatile memory according to the present invention.

In FIG. 1, a flash memory (1)
Has a non-volatile characteristic in which data can be electrically erased in a specific block unit and data can be repeatedly written and read, and is equal to the first storage area (1a: LEFT ARRAY) and the second storage area (1b: RIGHTARRAY). Divided. The flash memory (1) stores program data, table data, and the like for causing the microcomputer to perform various logical operations. The first and second storage areas (1a) and (1b) of the flash memory (1) have a total storage capacity of, for example, 64 Kbytes (a unit representing one word = 8 bits), and an even-numbered block EV in a 64-byte unit.
EN and odd-numbered block ODD are alternately repeated (even-numbered block EVEN represents 0, 2, 4,..., And odd-numbered block ODD represents 1, 3, 5,...).

The row decoder (2) includes a first or second storage area (1a) (1
b) is selected, and an even block or an odd block of 64 bytes is selected from the storage area on the selected side. The first column decoder (3)
This is to select only one predetermined byte in one even-numbered or odd-numbered block of 64 bytes specified in the storage area (1a). The second column decoder (4) selects only one predetermined byte in one even-numbered or odd-numbered block of 64 bytes specified in the second storage area (1b).

The page buffers (5) and (6) are 64
It has a storage capacity of bytes, that is, it has the same storage capacity as the even and odd blocks constituting the first and second storage areas (1a) and (1b). The flag circuit (7) has 128 flags corresponding one-to-one to 64-byte storage positions in the page buffers (5) and (6). When new data is stored in the page buffers (5) and (6) from a state where all the 128 flags in the flag circuit (7) are set to the logical value "0", the new data storage positions correspond one-to-one. Flag changes to a logical value “1”. The flag detection circuit (8) is in a state where all 128 flags of the flag circuit (7) have become the logical value "1", that is, the page buffer (5)
In response to (6), a state where 128 bytes of new data is stored is detected, and a detection signal IDALL having a logical value of "1" is output. The control unit (9) re-executes a 128-byte new data storage operation for the page buffers (5) and (6) when the detection signal IDALL having the logical value "1" is supplied from the flag detection circuit (8). It is.
The sense amplifier (10) is a column decoder (3) (4)
Is to amplify the current of 1-byte data selectively output from. The IO block (11) inputs and outputs data D7 to D0.

16-bit address data A15 to A0
Is a flash memory (1) and a page buffer (5)
This is data for addressing (6). The first storage area (1a) has a total of 5 in which 256 even-numbered blocks EVEN and 256 odd-numbered blocks ODD are alternately arranged.
It consists of 12 blocks. The second storage area (1b) also includes 512 blocks. That is, the row decoder (2)
Is supplied between the first and second storage areas (5) and (6) by supplying the address data A15 to A8.
A total of four blocks including a pair of even blocks and a pair of odd blocks are selected, and one of a pair of even blocks or a pair of odd blocks is selected by supplying address data A6. The column decoders (3) and (4) supply the address data A5 to A0 to supply the first and second storage areas (1) selected by the row decoder (2).
a) A predetermined one byte in each one block in (1b) is selected. However, the column decoders (3) and (4)
Alternatively, since the address data A7 for selecting one of the second storage areas (3) and (4) is also supplied, when the address data A7 has the logical value "0", the predetermined value of the first storage area (1a) is determined. One byte is selectively output, and when the address data A7 has the logical value "1", a predetermined one byte of the second storage area (1b) is selectively output.

The storage order of the page buffers (5) and (6) differs depending on which of the contents of the first and second storage areas (1a) and (1b) is rewritten. That is, when rewriting the contents of the first storage area (1a), new data is written in the order of the page buffers (5) and (6), and when rewriting the contents of the second storage area (1b), the page buffer (6) ( Write new data in the order of 5). Therefore,
Since the two page buffers (5) and (6) need to be regarded as one page buffer having a storage capacity of 128 bytes, address data A6 to A0 are supplied.
Address data A7 is supplied to determine the storage order of the page buffers (5) and (6).

An operation for rewriting the entire contents of one predetermined page of the flash memory (1) will be described. For example, assume that the entire contents of a pair of adjacent even-numbered and odd-numbered blocks (hatched lines) in the second storage area (1b) are to be rewritten. First, a 128-byte new data storage operation is performed on the page buffers (6) and (5) in the order of the page buffers (6) and (5). At this time, if all the flags of the flag circuit (7) have not changed to the logical value “1”, the flag detection circuit (8) sends the page buffers (6) and (5)
It is determined that all the new data for the byte has not been stored, and the control unit (9) is informed of the detection signal IDA of the logical value "0".
Supply LL. The control section (9) causes the storage operation to the page buffers (6) and (5) to be executed again in accordance with the detection signal IDALL having the logical value "0". On the other hand, when all the flags of the flag circuit (7) change to the logical value "1", the flag detection circuit (8) stores all new data of 128 bytes in the page buffers (6) and (5). And supplies the control unit (9) with the detection signal IDALL having the logical value "1". The control section (9) detects the detection signal IDA of the logical value “1”.
The process proceeds to the next rewrite sequence according to LL. That is, the entire contents of the pair of even and odd blocks in the second storage area (1b) are erased. Next, new data of 64 bytes stored in the page buffer (6) is written into the even-numbered block EVEN (hatched) in the second storage area (1b). Next, the page buffer (5)
64 bytes of new data stored in the IO bus (1
2), sense amplifier (10), IO block (11),
The data is stored in the page buffer (6) through the IO bus (12). Next, another 64-byte new data stored in the page buffer (6) is written to the odd-numbered block ODD (hatched) in the second storage area (1b). As described above, the operation of writing all data for one page to the second storage area (1b) is completed.

According to the embodiment of the present invention, new data can be reliably written to one predetermined block of the flash memory (1).

[0016]

According to the present invention, when rewriting the contents of a predetermined block in the nonvolatile memory, the state of the flag corresponding to each address of the buffer circuit on a one-to-one basis is detected, and all the flags are determined in advance. Since the rewriting operation is re-executed when the logical value has not changed, the advantage that the data rewriting can be surely realized is obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a write circuit of a nonvolatile memory according to the present invention.

FIG. 2 is a block diagram showing a write circuit of a conventional nonvolatile memory.

[Explanation of symbols]

 (1) Flash memory (5) (6) Page buffer (7) Flag circuit (8) Flag detection circuit (9) Control unit

Claims (1)

[Claims] 1. A non-volatile memory having a characteristic capable of electrically erasing data and writing / reading data, comprising a plurality of blocks of a fixed storage capacity, and a storage capacity of one block constituting the non-volatile memory. A buffer circuit for storing a predetermined block of rewritten data; and a flag corresponding to each address constituting the buffer circuit on a one-to-one basis, and a flag corresponding to the rewritten data stored address in the buffer circuit. A flag circuit for setting to a predetermined logical value, a flag detection circuit for detecting a state of the flag circuit, and a detection result of the flag detection circuit when all addresses of the buffer circuit have not been rewritten. A control circuit for re-executing a data storage operation for all addresses of the buffer circuit. The write circuit of the nonvolatile memory, wherein.