JPH0610821B2 - Micro computer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a microcomputer having a plurality of PROMs therein.

[Conventional technology]

2. Description of the Related Art Conventionally, some microcomputers have a plurality of read-only memories (hereinafter, referred to as ROMs) for storing different information such as table data for instructions and displays. However, since the contents of the ROM are stored in the microcomputer in which the ROM is incorporated at the manufacturing stage, the contents of the ROM cannot be changed after the product is completed. So that the contents of ROM can be rewritten, ROM
Instead, there is a microcomputer having a built-in electrically writable read-only memory (hereinafter referred to as PROM).

FIG. 2 is a block diagram showing a conventional example of a main portion of a PROM portion of a microcomputer including two PROM arrays.

When data is stored in the circuit of FIG. 2, the control signal 20 is set to the first level by setting the selection signal 18 to, for example, “0” level.
After making it possible to write to PROM13 of
11 to control circuit 20, write circuit 12 to data bus 11
The above-mentioned command data, for example, is stored in the first PROM 13. Next, after the control circuit 20 is made writable in the second PROM 14 by setting the selection signal 18 to, for example, "1" level, the data bus 11 is passed through the control circuit 20 and the write circuit 21 to the data bus 11 , For example, table data is stored in the second PROM 14.

When reading data, first PROM 13 and second PR
The OMs 14 operate independently of each other, and when reading instruction data, the instruction data is latched in the instruction register 16 from the first PROM 13 through the read circuit 15. When reading the table data, the table data is latched in the data register 17 from the second PROM 14 through the reading circuit 22.

[Problems to be solved by the invention]

Conventionally, as shown in FIG. 2, the first PR for storing instructions
In a microcomputer including a plurality of sets of PROMs such as a second PROM for storing OM and table data, each PROM needs to have an independent write circuit and read circuit, and as a result, the chip area increases. There is a drawback that.

[Means for solving problems]

The microcomputer of the present invention includes a first PROM and a second PROM.
In a microcomputer including an array, data writing means shared by the first and second PROM arrays and writing data in a selected PROM array of the first and second PROM arrays Data writing means and data reading means shared by the first and second PROM arrays, the data reading means reading data from a PROM array selected from the first and second PROM arrays. And the first and second
First and second registers respectively provided in correspondence with the PROM arrays of the
Of the PROM array is selected to store the read data from the first PROM by the data reading means, and the second register is set to the second PROM.
When the array is selected, it is activated to store the read data from the second PROM by the data read means.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a main part of an embodiment of a microcomputer of the present invention. In this embodiment, two PROMs are incorporated as in the conventional example shown in FIG.

The first PROM 3 and the second PROM 4 are commonly connected to the data line for inputting data, and the data on the data bus 1 is written by the write circuit 2 and written via the read circuit 5. Data is read and data bus 1
Is output to. The address control circuit 9 is the first PROM 3
An address signal designating a predetermined address PROM cell of the second PROM 4 is generated, and a predetermined address signal is generated at the time of writing and reading. Further, the address control circuit 9 is controlled by a selection signal 8 for selecting either the first PROM 3 or the second PROM 4, and for example, in the case of performing writing or reading at a predetermined address of the first PROM 3, the selection signal 8 Is "0" (low level), and the selection signal 8 is "1" when writing to or reading from a predetermined address of the second PROM4.
Control to (high level). The instruction register 6 latches the data on the data bus 1 when the selection signal 8 is “0”,
The data register 7 latches the data on the data bus 1 when the selection signal 8 is "1".

Next, the operation in this embodiment, that is, the data write and read operations will be described.

(1) When writing data When the selection signal 8 is "0", the address control circuit 9 selects the first PROM 3, the writing circuit 2 writes an instruction on the data bus 1, and the selection signal 8 is " When it is "1", the second PROM 4 is selected by the address control circuit 9, and the data on the data bus 1 is written through the write circuit 2.

(2) When reading data When the selection signal 8 is "0", the first PROM 3 is accessed by the address control circuit 9, and at the same time the instruction register 6 is accessed.
Is read by the read circuit 5 and is latched by the instruction register 6 via the data bus 1. When the selection signal 8 is "1", the second PROM 4 is accessed by the address control circuit 9, and at the same time, the data is read by the read circuit 5 in a state in which the data register 7 can be accepted, and the data register 7 is sent via the data bus 1. Latched on.

In this way, by providing the address control circuit 9 and switching the selection signal 8, the first PROM 3 and the second PROM 3
4, the write circuit 2 and the read circuit 5 can be shared.

Although the present embodiment is an example of a microcomputer having two PROMs built therein, the present invention is also applicable to a microcomputer having three or more PROMs built therein.

〔The invention's effect〕

As described above, the present invention makes it possible to reduce the chip area by sharing the write circuit and read circuit of a plurality of PROMs and latching the read data in a predetermined register in response to a selection signal when reading data. .

[Brief description of drawings]

FIG. 1 is a block diagram of a main part of an embodiment of a microcomputer according to the present invention, and FIG. 2 is a block diagram of a main part of a conventional example of a microcomputer including two PROM arrays. 1: data bus, 2: write circuit, 3: first PROM, 4: second PROM, 5: read circuit, 6: instruction register, 7: data register, 8: selection signal, 9: address control circuit.

Claims (1)

[Claims] 1. A microcomputer having first and second PROM arrays built-in, wherein the first and second PROM arrays are data writing means shared by the first and second PROM arrays. Data writing means for writing data to a selected PROM array of the first and second PROM arrays, and data reading means shared by the first and second PROM arrays of the first and second PROM arrays. Data read means for reading data from the selected PROM array, and first and second registers provided corresponding to the first and second PROM arrays, respectively, the first register being the When the first PROM array is selected, it is activated to store the read data from the first PROM by the data read means, and the second register is stored in the second PROM. Microcomputer, characterized in that it is activated when the ray is selected to store the data read from the second PROM by said data reading means.