JPS5899840A - Control storage device - Google Patents

Abstract

PURPOSE:To compensate characteristics of an ROM, and to elevate the performance, by providing a data selector, an instruction register, etc. on a control storage, and designating an address in a branch destination block, through a selector, by a branch control bit and a branch address in the instruction register. CONSTITUTION:The first and the second control storage blocks 31, 32 which are capable of accessing simultaneously by access of once, and a block address of these blocks 21, 32 is generated from a program counter 33. A block designating bit and an address from this counter 33 are selected by data selector 35-37, and information from the blocks 31, 32 is read out. A microinstruction read out from these blocks 31, 32 is stored in an instruction register 34, and by branch control bits 342, 343 and a page bit 344 in this register 34, a branch destination block and a branch destination address in the blocks 31, 32 are designated through the selectors 35-37, characteristics in the storage element in the blocks 31, 32 are compensated, and the performance is elevated.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a control storage device installed in a microprogram controlled subtraction machine.

In a computer using a microprogram control system, microprograms are stored in a control memory, and the computer is controlled by sequentially reading and executing the microprograms. Normally, one microinstruction is read each time the control memory is accessed, but since only one block of memory elements is operating at the same moment, the control memory has the characteristic of low power consumption when not in operation ( Measures are taken to reduce the power consumption of the entire control memory by using memory elements with a standby function (this is called a standby function). The standby function of such a memory element is controlled by a chip select terminal of the memory element, but in the case of a ROM (read only memory) that operates at high speed, there are problems as described below. Next, the first prisoner, (6)
Explain using. (2) Figure 07 is a program diagram of the ROM [4KX1 bits], and Figure 03) is its operation time chart. In the diagram, (1) is the memory cell array, C) is the row decoder, (3) is the column decoder, (4) is the column input circuit, A...All is the address input, DxN is the data input, I) otyt is the Data output, n is a chip select signal, and Wl is a write enable signal. Also (6
) In the figure, tAcc is the access time from address data output, t(0 is the access time from hatch select n to output, tOFF is the time when chip select n is not performed. Now, if tOFF is large enough, , address or chip select (operation mode specification) is determined first, the maximum value of tAcc or tco guaranteed by ROM characteristics is almost the same value.However, tOFF is larger than tACC and tCO. If the FF is very small, the disadvantage is that the tCO preserved due to the characteristics of the ROM will be longer than in the above case. It is slow at 80n1.

In general, control memory is configured, for example, in two blocks, as shown in FIG. is as shown in Figure 2 (6). The first block (21J) and the second block are each specified by a part of the address bits, and these bits are passed through the decoder (to) to the chip select signal C81 of each block.
, C82. The normal selector C'4) selects the program counter (A), and the 1st. The address is output to the second block (1), but in the case of a branch as shown in the figure (5), the selector (2) selects the branch destination address penalty side address from the program counter (C) by the address control signal (C). . Immediately after this selection switching, an unstable state may occur in the chip select signals (C8I, C82) depending on the characteristics of the decoder @. This corresponds to the condition described in the above-mentioned ROM characteristics when 9tOFF is very small, and as a result, the access time of the control memory at the time of branching becomes long. (In the case shown in Figure 81, the block number is also directly specified by the program counter counter or the branch destination address @, so the chip select signal is unstable. Unless it is possible to distinguish between branches where the block number changes or not, all branch instructions, including branches within the same block, must be delayed by the increased access time of the control memory, which reduces overall processing speed. In addition, in general, it is common practice to deal with such an increase in access time in control memory only in the case of branch instructions. there were.

The present invention has been made in view of the above, and provides a control storage device that compensates for the disadvantageous characteristics of ROM and makes full use of its performance when applying ROM with a standby function to control storage. The purpose is to provide.

The present invention will be explained in detail below using examples.

FIG. 3 is a block diagram showing one embodiment of the present invention. In this figure, koji is the control memory (H□Ml) of the first pump.
), control memory (ROM2) of @ company's second block, (to) ROM 1 ell), program counter that generates the read address of ROM2C1, (331), (3
32) is one dibit to specify each block, (
(341) is control data, (342) and (343) are branch control bits, and (344) is a branch address. (To) to (To) are data selectors, (To) and @ are chip select signals C8 output from the data selectors (To) and (To), respectively. The page bit (331) of the program counter (to) and the branch control bit (342) of the instruction register (to) are input to the data selector (to). The data selector @ contains the page bit (332) of the program counter (to) and the branch control bit (to) of the instruction register (to)
(343) is input. The data selector has an address field (333) for the program counter (to).
and the branch address (344) of the instruction register (to) are input. The above-mentioned data selectors (to) selectively output one of the information according to the address control signal, and the ROM 1611. Output to ROM2 (to). It was,
Branch control pin) (342) and ni-gibiy) (3
31) When the car yp*ss the ROMIc11)'
The chip select signal ``0#'' is output, and the R signal is output from the branch control bit (343) and page bit (332).
When OM2 (2) is accessed, the chip select signal port n of "K" is output.Next, the operation shown in Figure 3 will be explained.l) In the case of normal microprogram execution, the microprogram's microphone The party instruction address is specified by the program counter 03.The program counter (to) consists of a field (333) that specifies the address within the block, a bit (331) (332) that specifies the block number, and a field (333) that specifies the address within the block.
Each bit and field of (331) to (333) is transferred to the ROMIC via data selectors (to) to (goods).
(υ and 2 (to) K sent 0 Normally, (to) to (goods) are address control signals (not shown) K and the siprogram counter is selected. (to), at the output of C1[9 A certain chip select signal (to), @ is the ROMI that is in operation
Only those connected to C1B and RQM2tsIJ are ON
state, and the other state is dOFF. ROM161),
2CID The microinstruction read from any operating control memory is stored in the instruction register C! It is stored in 4. If it is not a branch instruction, the microinstruction stored in the instruction register (b) is sent to each register, gate, and arithmetic control section, and the microinstruction is executed. H) In the case of a branch instruction, if the branch instruction is read from ROMIC (1) or 2 (to) to instruction register CI4, the instruction register (
bits (342) and (343) of the bits (342 and 343) are branch control bits that specify and control the branch destination block (ROM).

If a branch instruction is detected, the data selector (to)
- (branch) selects data from the instruction register (b) side.

Therefore, the above bits (342) and (343) become the chip select signal (to) or (to) via the data selector (to) or (to).
supplied to Before, the branch address (344) is sent to ROMI@υ or ROM2C via the data selector (branch).
QK is supplied, addressed and ROM 1 (11
Or, the branch destination microinstruction is read from 2@. At this time, the chip select signal (to) or (to) is
) is used in the circuit of 9-like decoder (2).
+ L or L - + H level changes smoothly,
The unstable operation as shown in Figure 2 @ does not occur.In parallel with reading the above microinstruction, the value added to the branch address (344) is added to the program counter (towards ) field (333)
K is taken in, the chip select signal (to), and @ is the page register (331).

(332). As a result, the microinstructions corresponding to the branch destination microinstructions are sequentially read out from the ROMI or 2 to the instruction register (b) under the control of the counter (to).

Although the above description has been made regarding a RAMK having a standby function, the present invention can be similarly applied to a ROM (read only memory) K having characteristics similar to such a RAM.

The present invention is as described above, and it is possible to configure a control description that takes full advantage of the performance (speed, low power consumption, etc.) of the memory element, and it is possible to allocate the address of the control memory only by one person. Since it is an improved version of the conventional method, it has the advantage that the timing control circuit can be the same as the conventional one.

[Brief explanation of drawings]

Figure 1 is a block diagram showing conventional control memory.
6) is an operation waveform diagram of Fig. 1 (2), Fig. 2 is a block diagram showing an example of control memory composed of two blocks,
FIG. 6 is an operational waveform diagram of FIG. 2, and FIG. 3 is a block diagram showing an embodiment of the present invention. 31.32...Control storage block 33--Program counter, 34--Instruction register, 35.36.37--Data selector, 331.33
2 - page bit specifying control storage block, 3
33...Field specifying the address within the block, 342, 343--Branch control bits. Agent Patent Attorney Mr. Inoue Figure 1 Figure 2 Figure 3

Claims (1)

[Claims] It has a standby function, has page-based address assignment, and controls memory for multiple blocks consisting of a group of storage elements that can be read simultaneously in one access, and specifies a bit that specifies the block and an address within the block. a program counter that specifies the address of the microinstruction created from the field; a data selector that selectively transfers the block designation bit and address output from the program counter to the control memory; an instruction register that stores and outputs microinstructions read from the control memory; and a branch control bit and branch address contained in this instruction register that are sent to a branch destination block and block via the data selector. If! is equipped with a means for specifying an address within and reading a branch destination microinstruction. A control storage device named fgIL.