JPS61272856A - Processor control system - Google Patents

Abstract

PURPOSE:To speed up a controlling by setting control word that controls an external device in the controlling register of an interface control section. CONSTITUTION:One of memory addresses of a controlling memory is allotted to a flip-flop (FF) 10, and set to an by a write instruction. Following operation is made when the FF 10 is off. An instruction following above-mentioned write instruction is fetched from the controlling memory 3 as an action according to an ordinary instruction execution sequence, the read data are checked by a selector circuit and a non-operation instruction is transferred to an MPU 1. The read data are transferred to the controlling registers 7-9 of an interface controlling section 6. When the contents of the read data is madeto control word and the memory address is made equal to an address allotted to the controlling registers 7-9, one of them is loaded. By repeating above-mentioned operation, the loading is completed at every fetch of instruction.

Description

[Detailed Description of the Invention] [Summary] A control method for a microprocessor, etc., configured to load a control word into a control register of an interface control unit and control an external device connected to the control unit.

Once a predetermined control mode is set and a control word is fetched as an instruction, it is loaded into a designated control register.

When executing the command, it is forcibly regarded as a no-action command. This configuration speeds up loading of control registers. This control mode reset is via control bits within the control word.

[Industrial application field]

The present invention relates to a processor control system for a microprocessor or the like configured to control an external device connected to an interface control section by setting a control word in a control register of the interface control section.

Relatively small microprocessors for various types of control often have an interface control unit for connecting the external device in order to control the external device, and when appropriate control data is set as a control word in the control register, the corresponding Control is performed by transferring data to a predetermined external device.

Normally, in that case, the processor would set the above registers by executing a program configured to read data from the control memory etc. word by word and load it into the control register. Requires long processing time.

[Prior art and problems to be solved by the invention] FIG. 3 is a block diagram of an example of the configuration of a microprocessor system.

Microprocessor (hereinafter referred to as MPU)
specifies the storage address of the control memory 3 using the address la2, reads an instruction word or a data word from the control memory 3 onto the read data line 4, loads it into a register in the MPUI, or loads the data in the register. , can be sent to the write data line 5 and written into the control memory 3.

The interface control unit 6 has, for example, three sets of control registers 7, 8, and 9, and is configured to control an external device (not shown) according to the contents set in these control registers.

The MPUI controls the control register 7 of the interface control unit 6.
Control registers 7-9 to load control words into ~9.
A part of the storage address of the control memory 3 is allocated to the control memory 3.

In a write operation, when the storage address is specified, data sent from the MPUI to the write data line 5 is configured to be loaded into the corresponding register of the control registers 7 to 9.

Therefore, when writing the data word in the control memory 3 to the control registers 7 to 9, for each write to one control register, the instruction is read, the control word and the operand address specifying the control register are read, and the address Since it requires four to five control cycles consisting of reading out a control word by , and writing the read control word (loading it into a control register), there is a problem in that it requires a relatively long processing time.

[Means for solving problems]

FIG. 1 is a block diagram showing the configuration of the present invention.

In the figure, 10 is a flip-flop that displays the control mode, 11 is a decoder for the address assigned to the flip-flop 10, 12 is a selection circuit for switching between read data and a no-operation instruction, and 14 is a bit string representing a no-operation instruction. This is a register to hold.

[For production]

Flip-flop 10 is assigned one of the storage addresses of the control memory and is set, for example, on by a suitable write command.

When flip-flop 10 is off, the system is in normal operating mode, but when it is on, it operates as follows.

That is, when the instruction following the above write instruction is controlled to be fetched from the control memory 3 as an operation according to the normal instruction execution sequence, the read data is transferred to the selection circuit 1.
2, and instead a no-action command (in the following,
NOP command) is transferred to the MPUI.

Further, the read data is transferred to the control registers 7 to 9 of the interface control section 6.

Therefore, if the content of this read data is a control word and its storage address is the same as the address assigned to control registers 7-7, then the control word is 1 of control registers 7-9.
loaded into.

If consecutive addresses are assigned to the control registers 7 to 7, by repeating the above operations, loading of one control word will be completed in every control cycle of instruction fetch, resulting in faster control.

By using the control bit provided in the control word as a reset input of the flip-flop 10 via the control bit line 13, the control mode is reset to the normal mode.

〔Example〕

Control registers 7 to 9 of the interface control unit 6 in FIG.
For example, the storage address 'n+3' of the control memory 3 is
Assume that "n+5" is assigned.

When loading a control word into the control registers 7 to 9, as shown in FIG.
Control words to be loaded into each control register are stored in advance in 3' to 'n+5'.

Furthermore, a write command consisting of three words for setting the flip-flop 10 on is placed at storage addresses 'n° to 'n÷2°. For example, the first word is a write command, the second
The word is the address of the write data (in this case, it points to the next address after this word), and the third word is the write data (in this case, it points to the next address after this word).
In order to generate a signal to turn on the flip-flop 10, only the last bit is 1' (data).

By placing a so-called return instruction to return from the subroutine to the calling program at memory address ゛n+6゛, it is possible to move from memory address 〛n'' to °nn+6.
The steps up to ゛ constitute one subroutine.

Here, for example, one bit at the end of each control word is set to control bit 15, and its value is set to only the control bit 15 of the last control word, for example, °1°, and for all other control words, it is set to "0°". shall be.

After making the above preparations, when MPLll loads a control word into the interface control unit 6, it executes a branch to the subroutine at address n' by a known method.

Therefore, the write commands for storage addresses 'n' to 'n+2' are sequentially fetched to the MPUI via the selection circuit 12 and executed in, for example, four control cycles, thereby turning on the flip-flop 10.

The ON output of the flip-flop 10 causes the selection circuit 12 to
Thereafter, the NOP instruction stored in the register 14 is switched to pass, and the interface control section 6 is placed in a state where the control registers 7 to 9 are loaded.

In this state, the MPUI reads address "n+3" following the write command as the next command.

The information on the read data line 4 is transferred to the interface control section 6 and loaded into a control register designated by address "n+3", for example, control register 7.

Since the read data is not transferred to the MPUI and the NOP command for the register 14 is input from the selection circuit 12,
The MPUI performs normal control at the next address °n+4"
Begins fetching as an instruction.

As a result, the data at the storage address "n+4' is loaded into the control register 8, and then the data at the storage address "n+5°" is loaded into the control register 9 under the same control as described above.

In the conventional control, the control bit 15 at the end of the control word from storage address "n+3" to "n+5°" is connected as the control bit line 13 to the reset side input of the flip-flop 10, but the first two Since the control bit value is °0'' in the word, no reset occurs and reading the third control word causes the flip-flop 10 to
is reset off and restored to normal control mode.

Therefore, when the next return instruction is fetched from address "n+6", this instruction directly passes through the selection circuit 12, is input to the MPUI, and is executed as a return instruction.

With the above configuration, loading of the control registers 7 to 9 is executed at high speed.

Note that in the above explanation, storage addresses in the control memory are assigned to specify control registers 7 to 9, but for example, a control register specification part may be provided in each control word, and the value of the control register specification part may be provided in each control word. may be selected, and it is easy to change the configuration described above in this way.

This has the disadvantage that the actual control data portion of the control word is reduced, but has the advantage that the storage address of the subroutine described above is no longer fixed by the address of the control register.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, when a microprocessor or the like loads a control word into an interface control unit for controlling an external device, the processing speed is increased. There is a significant industrial effect of improving the performance of the system.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is an explanatory diagram of a subroutine configuration, and FIG. 3 is a block diagram of a conventional configuration example. In the figure, 1 is an MPU, 2 is an address line, 3 is a control memory, 4 is a read data line, 5 is a write data line, 6 is an interface control section, 7 to 9 are control registers, 10 is a flip-flop, 11
is a decoder, 12 is a selection circuit, 13 is a control bit line, 14 is a register, and 15 is a control pit supple sequence and F! @Zusa 2 concave

Claims (1)

[Claims] Control registers (7, 8,
9), a processor (1) configured to control an external device by setting a required control word is provided with a flip-flop (10) for displaying a control mode; In the case of the state of
The control word stored in the storage device (3) is read as a no-operation command and set in the control register (7, 8, 9), and when the specific bit of the read control word is a predetermined value, A processor control method characterized in that the flip-flop (10) is reset to the other state.