JPH0828119B2 - Semiconductor memory device - Google Patents

Description

The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device capable of selecting at least one memory cell array among a plurality of memory cell arrays.

[Conventional technology]

Conventionally, this type of semiconductor memory device (hereinafter referred to as RAM)
Is a method of inputting all addresses at once and a method of inputting addresses twice (address multiplex).
There are different types of address input methods. When accessing the memory from the CPU now, both of the above-mentioned two types of address input methods have given an address corresponding to the memory capacity to perform reading and writing. For example, when accessing a 64K (65536bit) bit memory, it was necessary to input an address of 65536 = 2 ¹⁶ to 16 bits. In addition, it was necessary to put the number of addresses determined by the memory capacity and the address input method out of the RAM. For example, a 64-Kbit RAM requires 16 addresses in the case of inputting an address once, and 8 addresses in the case of address multiplexing in which an address is input twice.

[Problems to be solved by the invention]

When the conventional semiconductor memory device described above is connected to the CPU C
It is necessary to output all addresses from the PU according to the memory capacity, and there is a drawback in that it is not possible to access RAM that has more memory capacity than the addresses output from the CPU without an external circuit. Further, the above-mentioned semiconductor memory device has a drawback that the capacity is increased, the number of addresses is increased, and the number of pins of the package is increased.

[Means for solving problems]

A semiconductor memory device of the present invention has a plurality of memory cell arrays, and in a semiconductor memory device capable of reading / writing each memory cell array by accessing an arbitrary address, the semiconductor memory device can be accessed at a specific address and the arbitrary address It has an upper address and an address register and a plane decoder which select a memory cell array by the upper address.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows an embodiment of the present invention. In FIG.
One embodiment of the present invention has a plurality of memory cell arrays 105 to 108, and these memory cell arrays include an address buffer 103 and a row decoder 104 for supplying addresses A _{0 to} A ₇ , and A _{8 to} A ₁₅ . Address buffer 111 for supplying an address, column decoder 110 and sense switch 109
And are connected. Each of the memory cell arrays 105 to 108 is, for example, a 512 Kbit memory cell array, and is composed of a first plane 105, a second plane 106, a third plane 107 and a fourth plane 108 for convenience of description, and includes a row decoder 104 and a column. Commonly connected to the decoder 110.
Further, the memory cell arrays 105 to 108 are address registers 101.
The plane decoder 102 is connected to the plane decoder 102, and the plane is selected by the data set in the address register 101 being decoded by the plane decoder 102.

Further, this embodiment has an input / output data control circuit 112, which is connected to the row decoder 104, the column decoder 110, the sense switch 109 and the address register 101, and also the data lines I / 01 to I / 08 and the control line ▲. ▼ line, ▲
Connected to ▼ and ▲ ▼ lines.

The input / output data control circuit 112 selects the address register 101 when the 0 address is designated in the address buffers 103 and 111 (when it is input to A _{0 to} A ₁₅ ), and the data in the address register 101 is I / 01, I / It can be rewritten using 02. As for the address for selecting the memory cell array (plane), the addresses A _{0 to} A ₁₅ are 0
It does not have to be an address, and the data line for accessing the address register does not have to be I / 01 or I / 02. For example, the data lines I / 05, I / 06, I / 07, I / 01, I / 03, or any other bit may be used. Furthermore, the present embodiment uses 2 bits for selecting four planes, but if the number of planes increases, the number of bits of the register may be increased accordingly.

The specific operation of this embodiment will be described next. If it is desired to access address FFFF (16) of the first plane, the chip enable signal ▲ ▼ is activated in the first cycle and the write enable signal ▲ ▼ is activated. Enter the address (write mode) 0000 (16) into A _{0 to} A ₁₅ . In this cycle, data can be written in the address register 101 and "0" data is input to I / 01 and I / 02. As a result, the address “00” of the address register is changed to the plane decoder 102.
, And the first plane 105 is selected.

In the next cycle, if the address FFFF (16) is input to A _{0 to} A ₁₅ and write or read is determined, the sense switch 109
Is activated and 00 is set in the address register 101, so that the address FFFF (16) of the first plane 105 can be accessed (written or read). By repeating this procedure, it is possible to access any address in the first to fourth planes.

The total capacity of this embodiment is, for example, 2 Mbit (20971
52 bits), and its structure can be said to be a 4-plane structure of 64 Kword × 8 bits, but address input is A _{0 to} A ₁₅
16 64Kbits are enough.

〔The invention's effect〕

As described above, according to the present invention, even if the memory capacity is increased by having the address register and the plane decoder, the number of address inputs does not increase, the number of address outputs from the CPU does not increase, and there is no external circuit.
Can be accessed, and the number of pins in the package does not increase, which is an effect.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention. 101 ... Address register, 102 ... Plane decoder,
103 ... Address buffer, 104 ... Row decoder, 105
... Memory cell array (first plane), 106 ... Memory cell array (second plane), 107 ... Memory cell array (third plane), 108 ... Memory cell array (fourth plane), 109 ... Sense switch, 110 ...
… Column decoder, 111 …… Address buffer, 112 ……
Input / output data control circuit, ▲ ▼ …… Chip enable signal, ▲ ▼ …… Output enable signal, ▲ ▼ …… Write enable signal, I / 01 to I / 08…
... data input and output, A ₀ ~A ₁₅ ...... address input.

Claims (1)

[Claims] 1. A plane decoder having a plurality of planes composed of a plurality of memory cell arrays and selecting one of the plurality of planes based on plane selection information stored in an address register for plane selection, and this decoder. A semiconductor memory device having means for executing data read / write via a data input / output terminal based on memory cell selection address information supplied from an address decoder to a memory cell in a plane selected by Means for detecting that the address information has a specific value and selecting an address register as a destination of the address information; and means for writing the plane selection information into the selected address register via the data input / output terminal. Is provided and the plane selection information should be changed by changing the plane selection information. The semiconductor memory device characterized by changing the memory cell array.