JPH09320259A - Semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve a block write operation speed by switching a level of a segment write mode at a block write operation time. SOLUTION: At the block write operation time, a block write mode decision signal 109 outputted from a control circuit 1 becomes an H-level, and a segment mode decision signal 110 is outputted at an L level to be inputted to a column address selection circuit 5. Then, the block write mode decision signal 109 and the segment mode decision signal 110 are made active, and the write-in of the color register data is simultaneously performed for a memory cell array 4 by segment division. At this time, an address length to be block written is varied by 2<n> or 2<2n> , and the block write operation speed at a segment write mode time is improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a block write function.

[0002]

2. Description of the Related Art In general, a block write function applied to a semiconductor memory device having a block write function uses a mask register data and a color register data which have been set in advance. This means that the data in the color register can be written simultaneously to a plurality of column addresses when all the data is set to the write operation state. The block write operation of the conventional semiconductor memory device having the block write function will be described.

FIG. 7 is a block diagram showing the structure of a conventional semiconductor memory device having a block write function. Figure 7
As shown in FIG. 3, in the conventional example, the row address strobe signal 101, the column add strobe signal 102,
Write enable signal 103, special function enable signal 104 and addresses A ₀ , A
_1, ..., a control circuit 20 which receives the A _7, control the row address select control signals 107 and the row address is output from the circuit 20 XA _0, XA _1, ..., enter the XA _7, the word line Selection signals 108-0, 108-2, ...
..., the row address selection circuit 2 for outputting 108-255
1, the block write mode determination signal 109 and the column addresses YA ₀ , Y which are also output from the control circuit 20.
A ₁ , ..., YA ₇ and column mask signals MA ₀ , M
Digit line selection signal 1 by inputting A ₀ , ..., MA ₇
The column address selection circuit 24 that outputs 11-0 to 111-255, the input of the word line selection signals 108-0, 108-2, ..., 108-255, and the digit line selection signals 111-0 to 111-255. In response, the memory cell array 23 for writing / reading data to / from the corresponding memory cell
It is connected by the write bus 112 and amplifies and outputs the data input signal 105 at the time of data writing (writing),
Further, at the time of data reading (reading), it is configured to include a read / write amplifier 22 that amplifies the data output from the memory cell array 23 and outputs it as a data output signal 113. This is a configuration example in which the color register data is simultaneously written corresponding to the 8 column address during operation.

In FIG. 7, when writing / reading data in the normal operation, a row address / strobe signal 101 and a column address / signal are externally supplied.
Strobe signal 102, write enable signal 103
And special function enable signal 1
04 and the addresses A ₀ , A ₁ , ..., A ₇ are input to the control circuit 20. From the control circuit 20, the row address selection control signal 107 and the row addresses XA ₀ , XA.
₁ , ..., XA ₇ is output and the row address selection circuit 2 is output.
Input to 1. The row address selection circuit 21 receives these signals and addresses and receives word line selection signals 108-0, 108-1, 108-2, ...
The word line selection signal corresponding to one row address of 108-255 is selected and output, and input to the corresponding memory cell array 23. On the other hand, the control circuit 2
From 0, the "L" level block write mode determination signal 109, column addresses YA ₀ , YA ₁ , ..., Y
A ₇ and column mask signals MA ₀ , MA ₀ , ..., M
A _{7 is} also output and input to the corresponding column address selection circuit 24. The column address selection circuit 24 receives these signals and addresses,
Digit line selection signals 111-0, 111-1, ..., 1
A digit line selection signal corresponding to one column address of 11-255 is selected and output, and input to the corresponding memory cell array 23.

At the time of writing a data signal, a data input signal 105 from the outside is input to the read / write amplifier 22 and is level-controlled by a data input / output level control signal 106 output from the control circuit 20,
The data is input to the memory cell array 23 via the read / write bus 112 and written in the memory cells in the memory cell array 23 selected by the row address selection circuit 21 and the column address selection circuit 24. In reading the data signal, the row address selection circuit 21 and the column address selection circuit 24 described above are used.
The data held in the memory cells in the memory cell array 23 selected by the read / write bus 1
Read / write amplifier 22 read via 12
The level is controlled at and is output to the outside as the data output signal 113.

Further, in the block write operation, the row address strobe signal 101 from the outside to the control circuit 20 is supplied to the control circuit 20, as in the normal operation.
The column address strobe signal 102, the write enable signal 103, the special function enable signal 104, and the addresses A ₀ , A ₁ , ..., A
_In response to the input of _7, the control circuit 20 outputs the row address selection control signal 107, the row addresses XA ₀ , XA
₁ , ..., XA ₇ , active block write mode determination signal 109, column addresses YA ₀ , YA ₁ , ...
, YA ₇ and column mask signals MA ₀ , MA ₀ , ...
, MA ₇ are output and input to the corresponding row address selection circuit 21 and column address selection circuit 24 as shown in FIG. However, during block write operation, as described above, block write
The mode determination signal 109 is input to the column address selection circuit 24 as an active level signal.

From the row address selection circuit 21, word line selection signals 108-0, 108-1, 108-2, ...
, 108-255, the word line selection signal corresponding to one address is selected and output, and input to the memory cell array 23. In addition, the digit line selection signal corresponding to the 8 column address is collectively received as the digit line selection signal that is output upon receiving the “H” level block write mode determination signal 109 from the column address selection circuit 24. And are simultaneously output and input to the memory cell array 23. That is, in the column address selection circuit 24, the digit line selection signals 111-0 to 111-255 correspond to the respective 8 column addresses in response to the input of the block write mode determination signal 109 of the "H" level. Digit line selection signal "111-0, 1
11-1, ..., 111-7 "," 111-8, 111
-9, ..., 111-15 ", ...," 111-2
48, 111-249, ..., 111-256 "are individually and simultaneously output and input to the corresponding memory cell array 23. Therefore, at the time of block write writing, a data input signal from the outside is input. 105 is input to the read / write amplifier 22, and the control circuit 20
A word line selection signal which is level-controlled by the data input / output level control signal 106 output from the row address selection circuit 21 and is input to the memory cell array 23 via the read / write bus 112. ,
And 8 output by the column address selection circuit 24
Data is simultaneously written into a plurality of memory cells selected by a plurality of digit line selection signals corresponding to column addresses. That is, the present as the conventional column address control function corresponding to the memory cell array 23, the address A _0, A ₁ to the control circuit 20 from the outside, ..., in response to the input of A _7, these addresses , Only one address input is selected from among the memory cell array, while eight address inputs are selected at one time in the block write cycle, and the memory cell array corresponding to these addresses is selected. Eight data from 23 are written simultaneously. Therefore, the time required for writing data is 1/8 the time required for normal operation. That is, the data writing speed to the memory cell array 23 is increased as compared with the normal operation.

A so-called mask function is used when the data in a certain memory area in the memory cell array 23 is held as it is and all the data in the other memory areas is deleted. In this case, the mask function is used. Mask data exists for each of the eight column addresses, and the correspondence relationship between the mask data and the column address is as shown in the correspondence table of FIG. In other words, the column address [8 _j +0,8 _j +1,8 _j +2,
_{8 j +3,8 j +4,8 j +5,8 j} +6,8 j +7
(J = 0, 1, 2, ..., 31)], the mask data is [0, 1, 2, 3, 4, 5, 6, 7] corresponding to each 8 column address. ] Is used. That is, use "0" as the mask data to the column address 8 _j, until the mask data "7" to the column address 8 _j +7 is used, corresponding to each column address, respectively Figure As shown in the correspondence table of No. 8, 1 bit of mask data is used.

In FIG. 7, the column address selection circuit 2
4, the block write mode determination signal 109 of "H" level is received, and the digit line selection signals 111-0 to 111-255 are set to the same as in the case of the block write operation described above. Digit line selection signals “111-0, 111-1,
……, 111-7 ”,“ 111-8, 111-9, ...
…, 111-15 ”, …………,“ 111-248, 1
11-249, ..., 111-256 ″ are simultaneously output individually corresponding to the mask areas,
Input to the array 23. Therefore, as in the case of the block write operation, the row address selection circuit 21 described above is used.
Data held by the plurality of memory cells selected by the plurality of digit line selection signals corresponding to the eight column addresses output by the column address selection circuit 24 and the word line selection signal -Deleted by data. Even in this case, the mask processing speed is improved by collectively inputting the plurality of digit line selection signals corresponding to the 8-column address.

[0010]

In the above-described conventional semiconductor memory device having the block write function, the number of digit line selection signals simultaneously output from the column address selection circuit during the block write operation is set in advance. It is defined by the number of column address divisions that have been set. In the case of the above-mentioned conventional example, the number of digit line selection signals that are simultaneously selected for eight column addresses is eight.
1 bit of the mask data corresponds to each column address defined in the book. As a result, during the block write operation, batch data writing is performed in units of 8 column addresses, and the improvement rate of the block write operation speed and the operation speed of mask processing is 8 in the case of the conventional example. It is limited by the digit line selection signal of the book, and there is a drawback that further improvement is impossible.

[0011]

A semiconductor memory device of the present invention comprises a row address strobe signal, a column address strobe signal, a write enable signal,
Receives special function enable signals and address signals, and outputs row address signals, column address signals, column mask signals, row address selection control signals, block write mode determination signals, segment mode determination signals, etc. And a row address selection circuit that receives the row address signal and the row address selection control signal and generates and outputs a word line selection signal, the column address signal, the column mask signal, and the block write signal. A column address selection circuit that generates and outputs a digit line selection signal in response to the input of a mode determination signal and a segment mode determination signal, and the word line selection signal and digit line selection signal when writing or reading data Multiple specified by signal A memory cell array formed by including memory cells, and in normal operation, by deactivating the block write mode determination signal and the segment mode determination signal, the word When the column address is designated by the column address division during the block write operation, the memory cell designated by the line selection signal and the digit line selection signal functions as a single memory cell. A digit line selection signal for simultaneously selecting the word line selection signal and a plurality of digit lines set during a block write operation by activating a write mode determination signal and deactivating the segment mode determination signal Memory cell specified by is set by block write When the column address is designated by the segment division, the function of the block write mode determination signal and the segment mode determination signal is activated and the word A memory cell specified by a line selection signal and a digit line selection signal for simultaneously selecting a plurality of digit lines set as one segment is defined as a plurality of memory cells set in one segment. I am trying.

The column address selection circuit is N
(= 2 ⁿ ) column address / block write operation, and N
Corresponding to ² column address segment write operation,
The column address selection circuit outputs the column address signal Y
The least significant n bits (YA ₀ , YA ₁ , ..., YA) corresponding to the input of A _i (i = 0, 1, 2, ..., M)
_n-1 ) and (YA _n, YA _{n + 1} , …………, Y
A _2n-1 ), ............, (…………, YA _m ), and a plurality of column predecoders that decode and output the column address signals as input, and the segment mode determination signal input and The column mask signal MA
Corresponding to the input of _i (i = 0,1,2, ........., N-1), jN is input during the block write operation.
(J = 0, 1, 2, ..., 2 ^m / N) A first selector (A) group that outputs a column mask signal MA ₀ corresponding to a digit line of a column address, and (jN + 1) column address Column mask signal MA ₁ corresponding to the digit line of
A second selector (A) group that outputs
[(J + 1) N-1] column mask signal MA _(N-1) corresponding to the digit line of the column address is output (N-
1) Selector (A) group, each of which has a predetermined segment
A first selector (B) group for outputting a column mask signal MA ₀ corresponding to a digit line of an N-bit column address starting from the value of j that is an integer multiple of N via a mode determination signal; A second group of selectors (B) that outputs a column mask signal MA ₁ corresponding to a digit line of an N-bit column address starting from the value of j that is an integral multiple of N + 1 + ₁ , and ... A (N-1) th selector (B) that outputs a column mask signal MA _(N-1) corresponding to a digit line of an N-bit column address starting from the value of j that is an integer multiple of N-1. The first, second, and so on ...
At the (2 ⁿ -1) ^th selector and the block write operation, all the outputs of the column address input column predecoder of the least significant n bits are set to the selected state, and the N-bit column mask signal corresponding to each digit line is set. A plurality of column decoders for decoding enabled signals, column predecoder outputs for higher addresses than the output of the least significant n-bit column predecoder, and column address input during segment block write operation All of the least significant 2n-bit predecoder outputs are selected, and a column pre-coder output for an address higher than the least significant 2n bits is decoded. The column decoder may be provided.

[0013]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. As shown in FIG. 1, in the present embodiment, a row address strobe signal 101, a column address strobe signal 102, a write enable signal 103,
The special function enable signal 104 and the addresses A ₀ , A ₁ , ..., A ₇ are input to the control circuit 1, and the row address selection control signal 107 and the row addresses XA ₀ and XA ₁ output from the control circuit _1. , ...
..., XA ₇ is input, and the word line selection signal 108-0,
108-2, ..., 108-255 are output, and the block write mode determination signal 109, the segment mode determination signal 110, the column addresses YA ₀ and YA ₁ , which are also output from the control circuit 1.
..., YA ₇ and column mask signals MA ₀ , M
Digit line selection signal 1 by inputting A ₀ , ..., MA ₇
Column address selection circuit 5 for outputting 11-0 to 111-255, input of word line selection signals 108-0, 108-2, ..., 108-255, and digit line selection signals 111-0 to 111-255. In response, the memory cell array 4 for writing / reading data to / from the corresponding memory cell is connected to the memory cell 4 by the read / write bus 112, and the data input signal 105 is amplified at the time of data writing (writing). The read / write amplifier 3 that outputs and amplifies the data output from the memory cell array 4 and outputs it as the data output signal 113 at the time of data reading (reading)
This is an example of the configuration in which the color register data is simultaneously written in correspondence with the 8 column address during the block write operation. The present embodiment is different from the above-described conventional example in that in the present embodiment, the control circuit 1 newly outputs the segment mode determination signal 110 and inputs it to the column address selection circuit 5.

In FIG. 1, at the time of writing / reading data in the normal operation, a row address strobe signal 101, a column address strobe signal 102, a write enable signal 103, a special function enable signal 104, and an address. A ₀ , A ₁ , ..., A ₇ are input to the control circuit 1, and from the control circuit 1, the row address selection control signal 107 and the row addresses XA ₀ , XA ₁ ,.
₇ is output and input to the row address selection circuit 2, and the block write mode determination signal 10 of "L" level is output.
9. Similarly, "L" level segment mode determination signal 110, column addresses YA ₀ , YA ₁ , ..., YA ₇
And column mask signals MA ₀ , MA ₀ , ..., MA ₇
Is also output, and the corresponding column address selection circuit 5
Is input to

In this state, the word line selection signals 108-0, 108-1, 108-2, ..., 108 are output from the row address selection circuit 2 as in the case of the normal operation in the above-mentioned conventional example. -255, a word line selection signal corresponding to one row address is selected and output, and input to the corresponding memory cell array 4.
In addition, the column address selection circuit 5 corresponds to the input of the “L” level block write mode determination signal 109 and the “L” level segment mode determination signal 110.
From digit line selection signals 111-0, 111-1,
The digit line selection signal corresponding to one column address of 111-255 is selected and output, and input to the corresponding memory cell array 23. Therefore, writing / writing of data corresponding to the memory cell selected by these word line selection signal and digit line selection signal is performed.
The read operation is performed, but the content of the operation is the same as in the case of the conventional example described above.

Next, during the block write operation in this embodiment, the block write mode determination signal 109 output from the control circuit 1 becomes "H" level and the segment mode determination signal 110 becomes "L". It is output at the "level" and input to the column address selection circuit 5. Addresses and signals output from the control circuit 1 other than the above are the same as those in the conventional example. A row address / strobe signal 101, a column address / strobe signal 102 to the control circuit 1 from the outside,
Write enable signal 103, special function enable signal 104 and addresses A ₀ , A
_1, ..., in response to the input of A _7, from the control circuit 1, a row address selection control signal 107, a row address X
_{A 0, XA 1, ......,} XA 7, "H" level block write mode determination signal 109, "H" level of the segment mode determination signal 110, a column address YA _0,
YA ₁ , ..., YA ₇ and the column mask signal MA ₀ ,
MA ₀ , ..., MA ₇ are output and input to the corresponding row address selection circuit 2 and column address selection circuit 5, respectively. Further, from the row address selection circuit 2, word line selection signals 108-0, 108-1, 108 are output.
, ..., 108-255, a word line selection signal corresponding to one address is selected and output, and input to the memory cell array 4.

Next, the internal operation of the column address selection circuit 5 will be described with reference to FIGS. 2, 3, 4, 5, and 6. FIG. 2 shows a column address selection circuit 1
It is a block diagram which shows the structure of embodiment, The column predecoder 6-8 and the column decoder 9-0-9-25.
5 and selectors 10-1 to 10-255. 3 and 4 are circuit diagrams showing the internal configurations of the column decoders 9-0 and 9-1, respectively, both of which include an inverter 11 and NAND gates 12 and 13.
And 14, an OR gate 15, and an AND gate 16. FIG. 5 is a circuit diagram showing the internal structure of the selector 10-1, which comprises an inverter 17 and transfer gates 18 and 19.
The column decoders 9-0, 9-9, ... 9-25
No corresponding selector exists for No. 5, so that the column mask signal output from the selector is not input. FIG. 6 is a diagram showing a column address / mask data comparison table in this embodiment.

In FIG. 2, column addresses YA ₀ , YA ₁ , ..., YA ₇ inputted from the control circuit 1 are divided and inputted to the column predecoders 6, 7 and 8, respectively. For the column predecoder 6,
From the least significant bit of the column address, the number of column addresses that allows selection of digit lines corresponding to the number of column addresses to be written at one time during the block write operation is input. In this embodiment, since data for eight column addresses is written at once,
The column address input to the column predecoder 6 is a 3-bit column address including YA ₀ , YA ₁ and YA ₂ , and the column predecoder 6 receives the column address input. , Predecode addresses PYA ₀₀ , PYA ₀₁ , ..., PYA ₀₇ are output. The column addresses input to the column predecoder 7 are YA ₃ , YA ₄ and Y.
This is a 3-bit column address including A ₅ , and the column predecoder 7 receives this column address input.
From the pre-dedicated address PYA ₁₀ , PYA ₁₁ , ...
........., PYA ₁₇ is output. Further, in the column predecoder 8, the column predecoders 6 and 7 are
In, the decoding is performed for the upper column address input which is not decoded. In the present embodiment, since the memory cell array has a 256-digit configuration, a 2-bit column address including column addresses YA ₆ and YA ₇ is input to the column predecoder 8. From the column predecoder 8, the bride decode addresses PYA ₂₀ , PYA ₂₁ , PY
A ₂₂ and PYA ₂₃ are output.

Next, the column decoder 9 included in FIG.
-0 will be described. FIG. 3 shows a column decoder 9-0
3 is a circuit diagram showing the configuration of FIG. In FIG. 3, the control circuit 1
The column mask signal MA ₀ inputted by the column mask signal MA ₀ is a column mask signal used both in the block write operation and in the segment / block write operation. In the normal operation, the block write mode determination signal 109 and The segment mode determination signals 110 are both input at "L" level, the output of the NAND gate 12 is fixed at "H" level, and the column mask signal MA ₀
Input level becomes "Don't Care" and NAN
The outputs of the D gate 13 and the OR gate 15 are the levels of the predecode addresses PYA ₀₀ and PYA ₁₀ , and the output of the AND gate 16 is the digit line selection signal 111-that "cares" all the input addresses.
0 is output. Next, in the block write operation, the block write mode determination signal 109 becomes "H" level and the segment mode determination signal 110 becomes "L" level, whereby the output of the NAND gate 12 becomes the column mask signal. The level of MA ₀ is enabled, the level of the least significant bit of the predecode address PYA ₀₀ becomes “Don't Care”, and the NAND gate 13
Output is fixed at "H" level, and the predecode address PYA ₁₀ input to the OR gate 15 is "Care".
Then, the digit line selection signal 111-0 corresponding to the column mask signal MA ₀ and the predecode addresses PYA ₁₀ and PYA ₂₀ is output. In the segment block write operation, the block write mode is selected. Judgment signal 109 and segment mode judgment signal 1
10 becomes "H" level, the output of the NAND gate 14 is enabled by the level of the column mask signal MA ₀ , and the output of the OR gate 15 is also fixed at "H" level, and the predecode address PYA ₀₀ and P
The level of YA ₁₀ becomes “Don't Care”, and the digit line selection signal 111-0 corresponding to the column mask signal MA ₀ and the predecode address PYA ₂₀ is output.

In addition, like the column decoders 9-1 to 9-8, digit lines that use different column mask signals are selected corresponding to the block write mode / segment block write mode. The internal structure of the column decoder is shown in FIG. The operation of the column decoder in this case is that the column mask signal MS ₁ (to MS ₈ ) is a column mask signal output from the selectors 10-1 to 10-8 as shown in FIG. For operations other than
This is exactly the same as the case of the column decoder 9-0 in FIG.

Next, the selector 10-1 will be described with reference to FIG. In FIG. 5, the segment mode determination signal 110 input from the control circuit 1 is transmitted to the PMOS side of the transfer gate 18 and the transfer gate 19
Is input to the NMOS side of the
Inverted outputs of the mode determination signal 110 by the inverter 17 are transferred to the NMOS side of the transfer gate 18,
It is input to the PMOS side of the transfer gate 19. Therefore, when the segment mode determination signal 110 is input at the "L" level, the column mask signal MA ₁ for the block write operation is selected and the column mask signal M is selected.
Is output as S _1, also in the case where the segment mode determination signal 110 is input at "H" level, is selected column mask signal MA ₀ for segment write operation output as a column mask signal MS ₁ To be done. This column mask No. MS ₁ is sent to the corresponding column decoder. This also applies to other selectors. The column mask signal for segment write / block write in this case will be described with reference to FIGS. 6 and 8.

FIG. 6 is a comparison table showing the relationship between the column mask signals MA _{0 to} MA ₇ and the column address corresponding to each digit line during the segment write operation. In FIG. 6, the column mask signal MA ₀ is used for 8 bits starting from k = ₀ , 8, 16, 24. The specific column address using the column mask signal MA ₀ is 0 to 7 when k = 0, and k =
64 to 71 when 8, and 128 to 13 when k = 16
5, when k = 24, it is 192-199. Further, specific column addresses using the column mask signal MA ₁ are 8 to 15 when k = 1, 72 to 79 when k = 9, 136 to 143 when k = 17, and k =
When it is 25, it is 200 to 207. In this way, the column mask signals MA ₀ to MA ₇ are sequentially associated with the column addresses. FIG. 8 is a comparison table showing the relationship between the column mask signals MA _{0 to} MA ₇ in the block write operation and the column address corresponding to each digit line. In this case, the column mask signal M
The specific column address using A ₀ is ₀ , 8,
16, 24, ..., 248, and the specific column address using the column mask signal MA ₁ is
1,9,17,25, ..., 249.

[0024] Thus, the plurality of column decoder shown in FIG. 2, the predecode address PYA ₀₀ to P
YA ₀₇ , PYA _{10 to} PYA ₁₇ , PYA _{20 to} PYA ₂₃ , and column mask signals MA ₀ to commonly used in the block write mode / segment write mode.
MA ₇ , Block write mode / Segment write
In the case of digit lines using column mask signals MA _{0 to} MA ₇ which are used as different column mask signals in different modes, the column mask signal M passing through the selector is used.
S ₁ , ..., MS ₇ , MS ₈ , ..., MS ₁₅ are input, and the digit line selection signal 11 corresponding to each digit line is input.
1-0, 111-1, ..., 111-7, 111-
8, ..., 111-17 are output.

[0025]

As described above, according to the present invention, by switching the level of the segment write mode during the block write operation in the semiconductor memory device, the column address selection circuit can be provided with the lower n bits of the column address input, or By configuring the lower 2n bits of the column address input to be "Don't Care", the address length for block writing at the same time can be varied by 2n or 2n, and the segment write mode can be used. At times, there is an effect that the block write operation speed can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a block diagram showing a column address selection circuit according to the present embodiment.

FIG. 3 is a circuit diagram (1) showing a column decoder in the present embodiment.

FIG. 4 is a circuit diagram (2) showing a column decoder in the present embodiment.

FIG. 5 is a circuit diagram showing a selector according to the present embodiment.

FIG. 6 is a column address / mask according to the present embodiment.
It is a figure which shows a data control table.

FIG. 7 is a block diagram showing a conventional example.

FIG. 8 is a diagram showing a column address / mask data comparison table in a conventional example.

[Explanation of Codes] 1, 20 Control circuit 2, 21 Row address selection circuit 3, 22 Read / write amplifier 4, 23 Memory cell array 5, 24 Column address selection circuit 6-8 Column predecoder 9-0 9-255 column decoder 10-1 to 10-255 11,17 inverter 12-14 NAND gate 15 OR gate 16 AND gate 18 and 19 transfer gate 101 row address strobe signal 102 column address strobe signal 103 write Enable signal 104 Special function enable signal 105 Data input signal 106 Data input / output level control signal 107 Row address selection control signal 108-0 to 108-255 Word line selection signal 109 Block write mode determination signal 1 0 Segment mode determination signal 111 over 0-111 over 255 digit line selection signal 112 read write bus 113 data output signal A ₀ to A ₇ addresses XA ₀ ~XA ₇ row address YA ₀ ~YA ₇ column address PYA ₀₀ ~ PYA ₂₃ pre-decode address MA _{0 to} MA ₇ , MS _{1 to} MS _{9 to} MS _{15 to} MS ₂₄₈
MS ₂₅₄ column mask signal

Claims (2)

[Claims] 1. A row address signal, a column address signal, a column in response to an external input of a row address strobe signal, a column address strobe signal, a write enable signal, a special function enable signal, an address signal, and the like. A control circuit that outputs a mask signal, a row address selection control signal, a block write mode determination signal, a segment mode determination signal, and the like, and a word line selection signal that receives the row address signal and the row address selection control signal And a row address selection circuit that generates and outputs a column address signal, a column mask signal, a block write mode determination signal, and a segment mode determination signal, and generates and outputs a digit line selection signal. A column address selection circuit, A memory cell array formed of a plurality of memory cells designated by the word line selection signal and the digit line selection signal at the time of writing data or reading data, and at the time of normal operation In the above, by deactivating the block write mode determination signal and the segment mode determination signal, the memory cell specified by the word line selection signal and the digit line selection signal is defined as a single memory cell. When specifying a column address by column address division during block write operation,
A digit line that simultaneously selects the word line selection signal and a plurality of digit lines set during a block write operation by activating the block write mode determination signal and deactivating the segment mode determination signal. The memory cell designated by the selection signal functions to define a plurality of memory cells set by block write, and when the column address is designated by the segment division, the block write mode determination signal And, the memory cell designated by the digit line selection signal for activating the function of the segment mode determination signal and simultaneously selecting the plurality of digit lines set as one segment is set in one segment. Function to define multiple memory cells The semiconductor memory device according to claim and. 2. The column address selection circuit is N (=
2 ⁿ ) Corresponding to the column address / block write operation and the N ² column address / segment write operation, the column address selection circuit outputs the column address signal YA _i.
The least significant n bits (YA ₀ , YA ₁ , ..., YA _n-1 ) corresponding to the input of (i = 0, 1, 2, ..., _M )
And (YA _n, YA _{n + 1} , …………, YA _2n−1 ), ……
.., (........, YA _m ) divided column address signals as inputs, and a plurality of column predecoders for decoding and outputting, and the segment mode determination signal input and the column mask signal MA _i (i = 0,1,2, ..., N-1) corresponding to jN (j = 0,1,2, ..., 2 ^m /) during the block write operation.
N) a first selector (A) group which outputs a column mask signal MA ₀ corresponding to the digit line of the column address,
A second selector (A) that outputs a column mask signal MA ₁ corresponding to the digit line of the (jN + 1) column address.
, And the (N-1) th selector (A) group that outputs the column mask signal MA _(N-1) corresponding to the digit line of the [(j + 1) N-1] column address. In the segment / block write operation, each digit line corresponding to the digit line of the N-bit column address starting from the value of j that is an integer multiple of N is used as a starting point through a predetermined segment mode determination signal. Column mask signal MA _{1 corresponding} to a first selector (B) group that outputs a column mask signal MA ₀ as a column and a digit line of an N-bit column address starting from the value of j that is an integer multiple of N + ₁ Second to output
Column mask signal MA _(N-1) corresponding to the digit line of the N-bit column address starting from the value of j that is an integer multiple of _N-1. , The (2 ⁿ -1) ^th selector, which is divided into the (N-1) th selector (B) group, and the column address input during the block write operation. All the outputs of the least significant n bits of the column predecoder are selected, and the N bits of the column mask signal corresponding to each digit line are enabled, and the output of the least significant n bits of the column predecoder is higher. Multiple columns to decode the column predecoder output for
In the decoder and the segment / block write operation, all the least significant 2n bits of the predecoder output of the column address input are selected, and the column mask signal corresponding to each digit line is enabled, and the least significant 2n bits. 2. The semiconductor memory device according to claim 1, further comprising a plurality of column decoders for decoding column pre-tecoder outputs for higher-order addresses.