JPS61211742A - Buffer register - Google Patents

Abstract

PURPOSE:To simplify a construction of a circuit and execute a reading and a writing simultaneously by providing a shift register for inputting data by a first signal, a selecting means controlled by the first signal and the second signal and a means for selecting an optional bit and outputting the contents thereof. CONSTITUTION:A shift register S inputs data of a data input terminal I, synchronizes with a QWR to shift. By connecting outputs of transfer gates of respective groups, a multiplexer is constructed, and the output thereof becomes outputs O0-O3 of the QBR. The transfer gates O00-O03 output input data from I0-I3 to the outputs O0-O3 of QBR respectively by a queue pointer P0. Similarly, transfer gates O10-O40 output outputs of shift registers S10-S10 respectively to the outputs O0-O3 of QBR through queue pointers P1-P4.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical field to which the invention pertains] The present invention relates to a buffer register used in a microcomputer, and more particularly to a buffer register having a queue function.

[Prior art]

In order to prevent a decrease in operating speed due to a slow instruction fetch cycle in microcomputers, etc., an instruction queue buffer register (hereinafter referred to as QBR) is provided, and instructions are prefetched into the QBH using a cycle counter when the bus is free. has been adopted.

The instruction QBR is primarily used as a means to adjust the timing of instruction fetch and decoding, and may be functionally the same as a first-in-first-out (FIFO) memory. FIFO memory is a shift register or R
It can be configured with AM.

Conventional QBR using a shift register has Q
Input data is shifted so that the BR is empty and data is packed and stored from the innermost stage (output stage) in the QBR, while when reading, necessary data is shifted out and taken out. In this method, it is difficult to create the timing to shift the data input during writing to the required position, and the control circuit is therefore very complex. Another drawback is that reading and writing cannot be performed simultaneously. Therefore, this catch queue memory is not used much.

On the other hand, the RAM' type (1'-) QBR is realized by a circuit as shown in FIG. When making a pledge, this QBR activates the write control signal (QWR), commits the data (QIN) input to the input buffer 1 to the address of RAM 3 specified by the pledge pointer 2, and sets the write pointer 2 to Increment +2. When reading, the read control (QRD) is activated and the contents of the RAM 3 specified by the read pointer 4 are transferred to the output buffer 5? It is taken out as output data (QOUT) and the read pointer is incremented by +1. To determine whether the RAM is ready or full, compare the contents of the write pointer with the contents of the read pointer and then in storage 6. Based on the results, if the RAM is ready, signal QRDY is output, and if full, QFULL is output.
Generate a signal.

[Problems to be solved]

In QBR using RAM, QBR using shift register
Although timing control is simpler than in BR, means for precharging the input/output buffers 1 and 5 and RAM 3 and means for controlling their timing are required. In general, two pointers, a write pointer 2 and a read pointer 4, are required, and their decoders 7.8 are also required.

In addition, an arithmetic comparison circuit 6 is required to generate the QRDY signal and the QF U i,L signal. On top of that,
There is no way to solve the problem of not being able to read and write at the same time.

[Purpose of invention]

An object of the present invention is to provide a buffer register that has a simple circuit configuration and can perform reading and writing simultaneously.

[Means for solving problems]

The buffer register of the present invention has a shift register that inputs the first signal and data, and a buffer register that receives the first signal and the second signal. DIIJ# selection means, and means for selecting arbitrary bits of the shift register based on the selection means and outputting the contents thereof.

[Explanation of Examples]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing an embodiment of the present invention.

In this embodiment, a 4-bit×4-stage instruction queue buffer register (QBR) is illustrated. Here, the QWR signal is a data write control signal to QBR, and the QRD signal is QBR
00 to 03 are data output terminals of QBH, and Rg8ET' is an initialization signal of QBR.

Further, QRDY is a signal indicating that the QBR is in a ready state (empty state), and when this signal is inactive, the central processing unit (hereinafter referred to as CPU) does not generate the QRD signal. The QFULL' signal indicates that the QBR is full, and when this signal is active, the CPU does not generate the QWR signal.

PO to P4 are key pointers using shift registers that can be shifted up and down.

INC is a two-man power AND gate which inputs the inverted signal of the Q'RD signal and the QWR signal, and its output becomes the INC (increment) signal. DEC is a two-man power AND gate which inputs the inverted signal of the QWR signal and the QRD signal, and its output becomes a DEC (decrement) signal. QRDYB
is an inverter that receives the output of the queue pointer PO as an input, and its output becomes the QRDY signal. Poo is a transfer gate and inputs a "0" level when the INC signal is active. Also, the transfer gate PIO is DEC
The output of the cue pointer P1 is inputted in response to the signal.

The outputs of the two transfer gates POO and PLO are connected in common, and one of the outputs is connected to the queue pointer PO.
Configure the multiplexer so that it is input to Similarly, POl and P21 are transfer gates, and the former is an INC
The output of the cue pointer PO is input by the signal, the output of the cue pointer P2 is input by the latter uDEC signal, and the outputs of both are commonly connected to the key pointer P1.
Configure a multiplexer that will be the input to. Further PI
3 and P32 are transfer gates, the former inputs the output of the key pointer P1 by the 6-INC signal, and the latter inputs the output of the cue pointer P3 by the 1) EC signal, and connects the outputs of both to form the cue pointer. Configure a multiplexer that becomes the input to P2. P23
and P43 are transfer gates, the former inputs the output of the cue pointer P2 by the INC signal, and the latter inputs the output of the cue pointer P2.
In response to the EC signal, the output of the queue pointer P4 is input, and the outputs of both are connected to form a multiplexer that is input to the queue pointer P3. P34 and P44 are transfer gates, and the former inputs the output of cue pointer P3 by the INC signal, and the latter inputs ``0'' level by the DEC signal, and connects the outputs of both to input the +knee point to P4. Configure a multiplexer.

810-820-830-840, 811-821-8
31-841.812-822-832-842,81
3. -823-833-843 1d data input terminal I
O, 11, I2. This is a shift register that manually inputs data from I3 and shifts it in synchronization with QWR. 000-010
-020-030-〇40.001-011-021-
031-041.002-012-022-032-0
42, 003-013-Q23-033-043
Each U is a group of transfer gates, and the outputs of the transfer gates in each group are connected to form a multiplexer,
Its output becomes QBR output 00.01, 02, 03.

Transfer gates 000.001, 002, 003 are set to IO, II, I2 . Input data from I3 to QBM output 09, 01゜02 respectively
．． Output to 03. Similarly, transfer gate 010.
011, 012, and 013 output the outputs of the shift registers 810, 811, 812, and 813 to QBR outputs 00, 01, 02, and 03, respectively, by the queue pointer P1. Transfer gate 020. Q21,022゜02
3 outputs the outputs of cue pointers S20.821, 822, and 823 to QBR outputs 00.01, 02, and 03, respectively. Transformer 7 agates 030, 031, 032, 033 output the outputs of shift registers 830, 831, 832, 833 to QBR outputs 00, 01, 02, 03, respectively, by cue pointer P3. Transferate 04
0,041,042,043 output the outputs of shift registers 840, 841, 842, and 843 to QBR outputs 00, 01, 02, and 03, respectively, by queue pointer P4.

Next, the operation of this embodiment will be explained according to the timing chart of FIG. In FIG. 2, T1 to T12 indicate each timing. Also, both the QWR and QRD signals are
The QBR shown in FIG. 2 is set appropriately so that it can be in various states.

T1 is the cue pointer P after RgSj4T is applied.
4~PO, QBR output 03-00, QRDY.

All output signals such as QFULL are undefined ("X" in the figure). RE8BT becomes active at I2, cue pointer P4-POiiPO-'1", Pi~P4-'"
0”. As a result, QBR output 03
-00, the input data of IO, ie, lpH" is output to T3, and QRDY-QFULL becomes inactive. RE8BT becomes inactive at I3. Also, QRD and QWRfl both become inactive. Therefore, both the INC and DWC signals become inactive and maintain the state of I2.

When T4T::QWR becomes active, the INC signal becomes active and the queue pointer increments and becomes active. Also, the first stage of the shift register is 1s.
The input data "IFH" of I3-IO is input to 13-810 and shifted. Also, the QBR output is the first stage 813- of the shift register indicated by the queue pointer P1.
Data "FH" of 810 is output. Also, since the queue pointer PO becomes inactive, QRDY becomes active.

When QRD becomes active in I5, the cue pointer is decremented and PO becomes active, the input data of I3-IO, ie, EH'' is output to QBR output 03-03, and QRDY becomes inactive. QW
When R becomes active, the input data of I3-10, ie, "IIEH", is input to the first stage 813-810 of the shift register, and the shift register is shifted in the same way as I4. Also, the queue pointer is incremented, Pl becomes active, and QBR Output 03-00 has shift register 813-s
io data OH" is output. Also, Q and RDY become active. QWR is active and active at T7,
The shift register shifts when the input data of 13-IO, ie, DH'' is input to the first stage 813-810. Also, the key pointer is incremented and P2 becomes active, and the shift register is input to the QBR output 03-00. Data flEH'' of 823-820 is output. T8
Since both QRD and QWR become active, the shift register shifts when the input data of 13-IO, ie "Cal", is input to the first stage 813-810, but the key pointer's INC signal and DEC signal are both inactive. Therefore, the previous state of T7 is maintained and P2 remains active. Therefore, QBR output 03-〇〇 has shift register 823-8 pointed by queue pointer P2.
Data "DH" of 20 is output. When the QWR becomes active at T9, the shift register shifts to the first stage 813-810.
Input data of T3-TO input data, that is, IIBH''
is input and shifted. Also, the queue pointer is incremented and P3 becomes active, and the data "+DH" of shift registers 833-830 is output to QBR outputs 03-00.QWR is also active at T10, and the shift register outputs T3 to the first stage 513-810. - The input data of process 0, "AH", is input and shifted. Also, the queue pointer is incremented and P4 becomes active, and the data "DH" of shift registers 843-840 is sent to QBR outputs 03-00. is output.

Also, key pointer P4 becomes active, so Q F'
ULL becomes active. In Tll, QWI(-
Since both QRDs are inactive, all outputs maintain the same state as 'f'lO, similar to T3. T1
When QRD becomes active at 2, the key pointer decrements and P3 becomes active.

QBR outputs 03-00 have shift registers 533-83
Data "CH" of 0 is output. Also cue pointer P
4 becomes inactive, so QF'ULiL.

also becomes inactive.

In this embodiment, the cue pointer is configured with a shift register capable of shifting up and down, but it may also be configured with a counter such as a binary counter, and the decoded output thereof may be used as the cue pointer signal.

Furthermore, although the configuration of the QBH has been explained as 4 bits x 4 stages, it may be made into an arbitrary m-pitch 1-Xn stage QBR. [Effect of the Invention] As explained above, according to the present invention, the conventional Not only does it require only one key-read pointer, which was required with a RAM-based QBR, but it can also be used by simply taking out the key-pointer output.
A status signal such as DY-QFULL can be generated. Therefore, the configuration becomes very simple, and the number of elements required to configure the circuit can be reduced.

Moreover, complicated timing control, which was a disadvantage of both the conventional shift register system and RAM system, is no longer necessary, and the advantages such as reading and writing can be performed simultaneously are very large.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an embodiment of the QBH of the present invention, FIG. 2 is a timing chart thereof, and FIG. 3 is a conventional circuit diagram. QWR: Write signal to queue buffer register, QRD: Read signal of queue buffer register, T3-IO: Input data to queue buffer register, 03-00・・・・・・
Output data from queue buffer register, QRDY
... Signal indicating that the key-buffer register is ready, QF'ULL ... Signal indicating that the queue buffer register is full, Rg8E
T... Initialization signal of queue buffer register, INC, DEC... Two-man AND gate, Q RD Y B --- Inverter, P
OO, Plo, POL. P21. PI3. P32. P23. P43. P34. P
d2゜000-003,010-013,020-02
3.030-033゜040-043...Transfer gate, PO-P4...Queue pointer with shift register configuration, 5IO-820-830-8
40,811-821-831-841゜812-82
2-832-842, 813-823-833-843
...Shift register, Tl-T12...
・Timing signal.

Claims (1)

[Claims] a shift register into which data is input by a first signal;
The shift register is characterized by comprising a selection means controlled by the first signal and the second signal, and means for selecting and outputting the contents of arbitrary bits of the shift register based on the output of the selection means. buffer register.