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WO1992001260A1 - Selectable power of two coefficient signal combining circuits - Google Patents

Selectable power of two coefficient signal combining circuits

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Publication number
WO1992001260A1
WO1992001260A1 PCT/US1991/004589 US9104589W WO1992001260A1 WO 1992001260 A1 WO1992001260 A1 WO 1992001260A1 US 9104589 W US9104589 W US 9104589W WO 1992001260 A1 WO1992001260 A1 WO 1992001260A1
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WO
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Patent type
Prior art keywords
circuit
multiplexer
connected
adder
fig
Prior art date
Application number
PCT/US1991/004589
Other languages
French (fr)
Inventor
Kenneth Alan Parulski
Original Assignee
Eastman Kodak Company
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06TIMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T3/00Geometric image transformation in the plane of the image, e.g. from bit-mapped to bit-mapped creating a different image
    • G06T3/40Scaling the whole image or part thereof
    • G06T3/4007Interpolation-based scaling, e.g. bilinear interpolation
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10Complex mathematical operations
    • G06F17/17Function evaluation by approximation methods, e.g. inter- or extrapolation, smoothing, least mean square method
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10Complex mathematical operations
    • G06F17/17Function evaluation by approximation methods, e.g. inter- or extrapolation, smoothing, least mean square method
    • G06F17/175Function evaluation by approximation methods, e.g. inter- or extrapolation, smoothing, least mean square method of multidimensional data

Abstract

The present invention is an interpolation circuit that multiplexes inputs prior to one or more additions during the interpolation operation, thereby reducing the number of components implementing the interpolation circuit. The multiplexers apply shifted inputs to adders in a sequence that produces the desired binary based interpolated values. The interpolation circuit can be used to programmably produce filter coefficients.

Description

SELECTABLE POWER OF TWO COEFFICIENT SIGNAL COMBINING CIRCUIT S CROSS REFERENCE TO RELATED APPLICATION This application is related to U.S. application Serial No. 310,419, filed February 13, 1989 entitled Real Time Digital Signal Processor For Producing Full Resolution Color Signals From A Multi-Color Image Sensor by Paruls i et al., incorporated by reference herein.

-BACKGROUND OF THE INVENTION Field of the Invention

The present invention is directed to a circuit which selectably combines power of two coefficients for interpolation and filter control and, more particularly, to a circuit capable of producing a linear interpolation commonly used in digital signal processing of color signals where the invention reduces the integrated circuit chip area used by the interpolation circuit. Description of the Related Art Linear interpolation circuits are commonly used in digital signal processing systems, and particularly in image processing systems. The simplest form of linear interpolation is 1 to 2 interpolation. For example, an original image from a CCD camera might have 500 lines of pixels, while the printer or display may require 1,000 lines. The simplest way to obtain a 1000 line image is to simply replicate each camera line twice when displaying or printing. However, a preferred technique is to set the values of every second

SUBSTITUT output line equal to the values of the original lines from the camera, and to set the values of "interpolated" lines in between the original lines equal to the average of the values from the two vertically adjacent original lines from the camera. This technique, referred to as 1 to 2 linear interpolation, can be implemented in hardware very easily using an adder, a hardwired bit shift to divide by 2, and a multiplexer, as illustrated in Fig. 1. In this figure the original pixel values from two adjacent original lines (line n and line n+1) from the camera are loaded into registers 10 and 12. Each register outputs 1/2 the original value by hardwired shifting. For example, if the input signal is a ten bit signal then the most significant nine bits are passed to the adder as the least significant bits of the 10 bit adder input and the most significant bit of the adder input is set to zero. In this divide by shifting type operation, if a 1/4 value is needed, the two most significant bits of the next stage are set to zero and the eight most significant bits are supplied to the least significant bits of the next stage, if a 1/8 value is needed, the three most significant bits of the next stage are set to zero and only the seven most significant bits are supplied to the least significant bits of the next stage, and so on for other binary divisions. The adder 14 stores the result of the addition in a register 16. A multiplexer 18 then alternately stores either the original pixel values or the linearly interpolated values into an output register 20 depending on whether the output line number is even or odd. In this operation, the addition of the shifted original pixel values is performed before the multiplex operation.

A 1 to 4 linear interpolation is a common operation in many image processing applications. Two such circuits are used in a digital signal processor chip produced by Eastman Kodak Company as described in the U.S. Application previously mentioned. The general operation of a 1 to 4 interpolation technique is illustrated in figure 2. For each original pixel 30 in the input image, the circuit computes four "output" pixel values. One of the output pixel values 30 equals the original pixel 30. The other three output pixel values 32, 34 and 36 are linearly weighted combinations of the values of the nearest original pixels on the left and the right, if horizontal interpolation is being performed or top and bottom if vertical interpolation is being performed. The weights are 3/4 times the left pixel plus 1/4 times the right pixel for the first produced pixel 32, 1/2 times the left pixel plus 1/2 times the right pixel for the second produced pixel 34, and 1/4 times the left plus 3/4 times the right for the third produced pixel 36.

Figure 3A shows one of the two identical "horizontal chroma interpolator" circuits shown as Fig. 7 of the application mentioned above. The two "original" pixel values are loaded into the top two registers 40 and 42 every fourth master clock cycle (See Fig. 3B) . A 4 to 1 multiplexer 44 which is actually composed of three 2 to 1 multiplexers, is used to set the output equal to one of four values (See Fig. 3C) . When CHR0MAPIX(2) * 00, the value in register 42 is used. When CHROMAPIX(2) = 01, the output is set equal to 3/4 of the register 42 pixel value plus 1/4 of the register 40 pixel value. When CHR0MAPIX(2) = 10, the output equals 1/2 of the register 42 pixel value plus 1/2 of the register 40 pixel value. When CHR0MAPIX(2) - 11, the output equals 3/4 of the register 40 pixel value plus 1/4 of the register 42 pixel value. The implementation shown in Fig. 3A is the simplest prior art l to 4 interpolation circuit known and includes seven registers 40, 42, 46, 48, 50, 52 and 54, five adders 56, 58, 60, 62 and 64, and a 4 to 1 multiplexer or three 2 to 1 multiplexers. Another method of performing a linear interpolation is to use multipliers and interpolation coefficients stored in registers. This approach uses even more chip area than the approach discussed above. SUMMARY OF THE INVENTION

It is an object of the present invention to reduce the number of circuit components necessary to produce an interpolation circuit.

It is another object of the present invention to reduce the integrated circuit chip space used by the interpolation circuit.

It is also an object of the present invention to minimize the number of adders/subtracters used in an interpolation circuit. It is a further object of the piesent invention to reduce the space used on an integrated circuit for an interpolation circuit by substituting multiplexers for adders.

It is an additional object of the present invention to provide an improved interpolation circuit capable of interpolation, filter coefficient programming and programmable interpolation circuit setting.

It is still another object of the present invention to produce a signal or coefficient combining circuit which is capable of producing binary combinations while reducing the necessary number of circuit components to a minimum.

The above objects can be attained by an interpolation circuit that multiplexes inputs prior to one or more additions during the interpolation operation. The multiplexers select among different divide shifted inputs and apply the shifted inputs to adders in a sequence that produces the desired binary based combined or interpolated values.

These together with other objects and advantages which will be subsequently apparent, reside in the details of construction and operation as more fully hereinafter described and claimed, reference being had to the accompanying drawings forming a part hereof, wherein like numerals reference to like parts throughout. BRIEF DESCRIPTION OF THE DRAWINGS

Fig. 1 illustrates a conventional 1 to 2 interpolation circuit,*

Fig. 2 illustrates a 1 to 4 interpolation operation; Fig. 3A depicts a conventional 1 to 4 interpolation circuit;

Fig. 3B is a timing diagram of the control signals for the circuit of Fig. 3A;

Fig. 3C is a control signal state diagram showing the interpolation coefficients of the circuit of Fig. 3A;

Fig. 4 depicts a 1 to 2 interpolation or signal combining circuit in accordance with the present invention; Fig. 5A illustrates a 1 to 4 interpolation circuit in accordance with the present invention;

Fig. 5B is a timing diagram of the control signals for the circuit of Fig. 5A;

Fig. 5C is a control signal state diagram showing the interpolation coefficients of the circuit of Fig. 5A;

Fig. 6A depicts a 1 to 8 interpolation circuit in accordance with the present invention;

Fig. 6B is a state diagram of the control signals and interpolation coefficients for the circuit of Fig.6A;

Fig. 7A is a spline interpolation circuit in accordance with the present invention; Pig. 7B is a control signal state diagram for the circuit of Fig. 7A;

Fig. 8A illustrates a linear signal mixer in accordance with the present invention; and Fig. 8B illustrates the control signal state diagram for the circuit of Fig. 8A.

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention is based on the observation that each adder shown in the circuit of Fig. 3A is used only once every four master clock cycles, even though the adders are designed to complete an operation every master clock cycle. Therefore, the adders are essentially sitting idle 75% of the time. Furthermore, at most two adders are required to compute any of the interpolated output values. One adder is needed to sum 1/2 and 1/4 of a first original pixel value and a second adder is needed" to sum this result with 1/4 of the second original pixel value. The principle behind the present invention is to select different divide shifted signals using multiplexers before the addition operation is performed. As a result, the key to the present invention is in determining how to properly multiplex the inputs to the adders. The principle of the present invention is illustrated in Fig. 4 where two registers 80 and 82 feed a multiplexer 84 which selects one of the two registers. In a first master clock cycle, multiplexer 84 selects register 80 and stores that value in register 86. The contents of register 86 are shift divided by two and added to a shift divided output from register 82 and stored in register 90 producing the interpolated value. In the next master clock cycle multiplexer 84 selects the contents of register 82 and, as a result, register 90 receives the sum of 1/2 of the value in register 82 from multiplexer 84 and 1/2 of the value in register 82. This circuit performs the multiplex operations prior to the addition operation, which is in contrast to the sequence illustrated in Fig. 1. A comparison of Fig. 1 with Fig. 4 indicates that the number of circuit components for a one to two interpolation circuit in accordance with the present invention is the same as in the conventional circuit. However, the number of circuit components necessary in the present invention begins dropping with respect to the number of circuit components required in the conventional circuit, when the number of interpolated values increases, as illustrated in Fig. 5A.

A 1 to 4 interpolation circuit in accordance with the present invention shown in Fig. 5A requires only two adders, compared to five for the conventional circuit of Fig. 3A, and only five rather than six registers. The circuit needs four, rather than three, 2 to 1 multiplexers, one OR gate, and one invertor. Since the adders require by far the most chip area, this new circuit takes less than one-half of the area of the conventional circuit of Fig. 3A. Yet the present invention takes the same amount of time to perform the interpolation as the conventional circuit. The circuit of Fig. 5A operates using the same clocking signals required by the conventional circuit of Fig. 3A and is a drop-in replacement for the prior art circuit. The original pixels are latched into the left and right registers 100 and 102 every four master clock (CK) cycles and four pixels are produced for every clock cycle of CK43. The A and B multiplexers 104 and 106 determine whether the left or right inputs are routed to the A and B adder inputs. The 0 and 1 values next to the inputs of the multiplexers indicate which input is selected based on the value of the select signal, for example, when select A is 1 the content of register 102 is selected and when select A is 0 the content of register 100 is selected. To set the output equal to the register 102 (right) pixel value, multiplexers A and B (104 and 106) both select (select A=l and select B=l) the right register 100 output. Multiplexer C, 108 selects (select C=0) zero as one of the adder A (110) inputs, so that the adder A (110) output to register C(112) equals 1/2 the right register (100) value, while multiplexer D(114) selects (select D=l) 1/2 the right register (100) value. Thus, adder B (118) outputs to output register 120 a value which equals 1/2 the value in the right register 102 plus 1/2 the value in the right register 102. Of course, it is possible to just route the right register 102 directly to the output register 120, but this would require an additional multiplexer and a select line decoding circuit.

To obtain the 3/4 left register value plus 1/4 the right register value, multiplexer A (104) selects the left register 100 while multiplexer B (106) selects the right register 102. At the same time multiplexer C (108) selects the 1/4 input, so that the register C (112) value equals 3/4 left, while Multiplexer D (114) selects the 1/4 input, so that the register D (116) value equals 1/4 right. This gives the proper output. To obtain 1/4 left plus 3/4 right, the multiplexer A (104) and multiplexer B (106) selection is simply reversed. To obtain 1/2 left plus 1/2 right, multiplexer A (104) selects right 102 while multiplexer B (106) selects left 100. Multiplexer C (108) sets one adder A input to 0, so the output equals 1/2 right, while multiplexer D (114) selects 1/2, so the second adder B (118) input equals 1/2 left. Fig. 5B illustrates the clock signals applied to the circuit of Fig. 5A to accomplish the above-described operation. However, as can be seen by comparing the timing signal diagrams of Fig. 3B with the corresponding diagrams in Fig. 5B, the phases of the chroroapix signals needs to be adjusted, a task within the ordinary skill in the art. By making such an adjustment the output arrives at the same phase relative to CK43 as in the conventional circuit. Fig. 5C illustrates the translation of the two control signals chromapix 1 and chromapix 0 into the multiplexer selection signals A, B, C and D. As shown in Fig. 5A the present invention includes an invertor 122 along with an OR gate 124 which produces the select A signal from the control signals chromapix (2). The remaining selection signals B, C and D are unmodified control signals. The map illustrated in Fig. 5C also depicts the interpolation coefficients produced as a result of the particular state of the control signals where X is the location in the pixel stream of the produced pixel, for example, when chromapix (2) « 00 the pixel adjacent to the original right pixel is produced.

As can be seen from the above discussion, the present invention can be used to advantage any time a hardware implementation of a 1 to 4 interpolation is required. The basis of the present invention is to count the minimum number of adders needed to obtain the roost adder intensive interpolated output value and then develop a circuit using this many adders along with multiplexers to appropriately provide the bit shifted or zero inputs to the adders. This approach can be extended to any other size interpolation circuit. However, a 1 to 3 interpolation circuit does not benefit from the present invention, since the 1/3 plus 2/3 terms are best implemented with multiplexers which have programmable coefficients instead of bit shifted additions. A 1 to 6 or 1 to 8 interpolator benefits considerably from the present invention since these interpolators would normally be implemented with multipliers. Fig. 6A illustrates how the present invention can be applied to a 1 to 8 interpolator.

As illustrated in Fig. 6A, a 1 to 8 interpolator circuit in accordance with the present invention also includes two registers 140 and 142, the contents of which are selected by multiplexers 144 and 146 in a first stage. A set of second stage multiplexers 148, 150, 152 and 154 select from appropriately shifted outputs from the first stage multiplexers, or from zero values, and supply the selected values to adder 156 and adder/subtractor 158. The second stage multiplexer 152 shows a "-1/8" input value. During actual operation only a 1/8 value is transferred through multiplexer 152 and the sign input to the adder/subtractor 158 is set to produce a negative input. Adders 156 and 158 supply stage storage registers 160 and 162 which feed an adder 164 that produces the output stored in register 166. The control signals, the resulting interpolation coefficients and the pixel being produced are illustrated in Fig. 6B. It is possible to produce the control signals using a logic circuit with appropriate AND, OR and inverter gates, however, with a complicated control signal set such as illustrated in Fig. 6B it would also be appropriate to provide these values from a memory storage device such as a ROM or a RAM which can be sequentially addressed by a counter incremented by a master clock signal. With the use of a programmable RAM to control the circuit of Fig. 6 it is of course possible to provide even more complicated signal combination control.

Fig. 7A illustrates the present invention when applied to a spline interpolation circuit which produces four new pixels for each pixel input by using the nearest four pixels for interpolation. The filter coefficients produced by this circuit are approximations of the "Cubic-B Spline" interpolation

STT shown in Fig. 4 of "Comparisons of Interpolating Methods For Image Resampling" by Parker et al., IEEE Transactions on Medical Imaging Vol. MI-2, No. 1, March 1983. As illustrated in Fig. 7A, input storage registers 180, 182, 184 and 186 feed a first stage of multiplexers 188, 190 and 192. The outputs of the first stage of multiplexers are selected, in various divide by shift combinations, by a second stage of multiplexers 194 and 196 to be combined by adders 198 and 200 and stored in corresponding registers 202 and 204. The contents of these registers are added by adder 206 and stored in output register 208. Fig. 7B illustrates the control signal values necessary to produce the filter interpolation coefficients shown therein.

Fig. 8A illustrates the present invention being used as a linear signal mixer which could for example be combining images from two different image sensors or from two different sound or pressure transducers. In this embodiment first stage multiplexers 220 and 222 feed second stage multiplexers 224 and 226 which supply shift divided input signals to adders 228 and 230 which produce/ the linearly mixed output signal. Fig. 8B illustrates the control signal values which produce the indicated linear combinations of the input signals. Once again this can be a programmable set of control signals stored in a ROM or RAM or implemented as an appropriate logic circuit. The many features and advantages of the invention are apparent from the detailed specification and thus it is intended by the appended claims to cover all such features and advantages of the invention which fall within the true spirit and scope of the invention. Further, since numerous modifications and changes will readily occur to those skilled in the art, it is not desired to limit the invention to the exact construction and operation illustrated and described, and accordingly all suitable modifications and equivalents may be resorted to, falling within the scope of the invention. What is claimed is:

SUBSTITUTE SHEET

Claims

1. A combining circuit for combining input signals, comprising: multiplex means for multiplexing the input signals to produce divide shifted outputs; and adder means for adding the divide shifted outputs to produce an output signal.
2. A combining circuit as recited in claim 1, wherein: said circuit further comprises input registers; said adder means comprises adders; and said multiplex means comprises multiplexers connected between said input registers and said adders and at least one of said multiplexers providing a bit shifted output of one of said input registers to one of said adders.
3. A circuit as recited in claim 2, wherein said input registers are connected in series.
4. A circuit as recited in claim 1, wherein: said circuit further comprises first and second input registers; said adder means comprises first and second adders where an output of said first adder is connected to an input of said second adder; and said multiplex means comprises multiplexers connected between said input registers and said adders and at least one of said multiplexers providing a bit shifted output of said input registers to an input of one of said adders.
5. A circuit as recited in claim 1, wherein: said circuit further comprises input registers; said adder means comprises first, second and third adders, outputs of said first and second adders being connected to inputs of said third adder; and said multiplex means comprising multiplexers connected between said input registers and said adders and a first one of said multiplexers providing a first bit shifted output of a first one of said input registers to an input of said first adder, a second one of said multiplexers providing a second bit shifted output of a second one of said input registers to an input of said second adder.
6. A circuit as recited in claim 1, wherein: said adder means comprises adders; and said multiplex means comprises multiplexers connected to said adders and at least one of said multiplexers providing a bit shifted output of one of said input signals to one of said adders.
7. A circuit as recited in claim 1, wherein: said circuit further comprises first and second input registers connected in series, said multiplex means comprises: a 2 to 1 multiplexer connected to said first and second input registers; and a storage register connected to said multiplexer, and said adder means comprises an adder connected to said second input register and said storage register.
8. A circuit as recited in claim 1, wherein: said circuit further comprises first and second input registers connected in series, said multiplex means comprises: first and second multiplexers each connected to both said first and second registers; a third multiplexer connected to said first multiplexer; a fourth multiplexer connected to said second multiplexer, and said adder means comprises: a first adder connected to said first and third multiplexers; and a second adder connected to said fourth multiplexer and said first adder.
9. A circuit as recited in claim 1, wherein: said multiplex means comprises: first and second multiplexers each receiving the input signals; a third multiplexer connected to said first multiplexer; a fourth multiplexer connected to said second multiplexer, and said adder means comprises: a first adder connected to said first and third multiplexers; and a second adder connected to said fourth multiplexer and said first adder.
10. A binary 1 to 4 linear interpolation circuit, comprising: a first register receiving an input signal; a second register connected in series to said first register; a first multiplexer connected to said first and second registers and producing a first output; a second multiplexer connected to said first and second multiplexers and producing a second output; a third multiplexer connected to said first multiplexer, receiving the first output left shifted by two bits and receiving a zero input; a fourth multiplexer connected to said second multiplexer and receiving the second output left shifted by two bits and left shifted by one bit; a first adder connected to said second multiplexer and to said first multiplexer and receiving the first output left shifted by one bit; and a second adder connected to said first adder and said fourth multiplexer.
11. A circuit as recited in claim 1, wherein: said circuit further comprises first and second input registers connected in series, said multiplex means comprises: first and second multiplexers each connected to both said first and second registers; third and fourth multiplexers connected to said first multiplexer; fifth and sixth multiplexers connected to said second multiplexer, and said adder means comprises: a first adder connected to said third and fourth multiplexers; an adder/subtractor connected to said fifth and sixth multiplexers; and a second adder connected to said first adder and said adder/subtractor.
12. A circuit as recited in claim 1, wherein: said circuit further comprises first through fourth registers connected in series, said multiplex means comprises: a first multiplexer connected to said second and third registers; a second multiplexer connected to said second and third registers; a third multiplexer connected to said first and fourth registers; a fourth multiplexer connected to said first multiplexer; a fifth multiplexer connected to said second multiplexer, and said adder means comprises: a first adder connected to said first and fourth multiplexers; a second adder connected to said third and fifth multiplexers; and a third adder connected to said first and second adders.
13. A binary 1 to 8 linear interpolation circuit, comprising: a first register receiving an input signal; a second register connected in series with said first register; a first multiplexer connected to said first and second registers and producing a first output; a second multiplexer connected to said first and second registers and producing a second output; a third multiplexer connected to said first multiplexer, receiving the first output left shifted three bits and one bit, and receiving a zero input; a fourth multiplexer connected to said first multiplexer, receiving the first output left
BSTITUTE SHEET shifted two bits and receiving a zero input; a fifth multiplexer connected to said second multiplexer, receiving the second output left shifted one bit and three bits, and receiving a zero input; a sixth multiplexer connected to said second multiplexer and receiving the second output left shifted two bits and three bits, and receiving a zero input; a first adder connected to said third and fourth multiplexers; an adder/subtractor connected to said fifth and sixth multiplexers; and a second adder connected to said first adder and said adder/subtractor.
14. A binary spline interpolation circuit, comprising: first through fourth register connected in series; a first multiplexer connected to said second and third registers and producing a first output; a second multiplexer connected to said second and third registers and producing a second output; a third multiplexer connected to said first and fourth registers and receiving a zero input; a fourth multiplexer connected to said first multiplexer, receiving the first output left shifted two and three bits, and receiving a zero input; a fifth multiplexer connect to said second multiplexer and receiving the second output left shifted one, two and three bits; a first adder connected to said first and fourth multiplexers and receiving the first output left shifted one bit;
TE SHEET a second adder connected to said third and fifth multiplexers; and a third adder connected to said first and second adders.
15. A binary linear signal mixing circuit, comprising: a first multiplexer connected to receive input signals and producing a first output; a second iuultiplexer connect to receive the input signals and producing a second output; a third multiplexer connected to said first multiplexer, receiving the first output left shifted by two bits, and receiving a zero input; a fourth multiplexer connected to said second multiplexer and receiving the second output left shifted by two bits and one bit; a first adder connected to said second multiplexer and to said first multiplexer and receiving the first output left shifted by one bit; and a second adder connected to said first adder and said fourth multiplexer.
PCT/US1991/004589 1990-07-09 1991-06-27 Selectable power of two coefficient signal combining circuits WO1992001260A1 (en)

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EP0923037A1 (en) * 1997-12-12 1999-06-16 Hewlett-Packard Company Common pruned radial and pruned tetrahedral interpolation hardware implementation
FR2772492A1 (en) * 1997-12-12 1999-06-18 Hewlett Packard Co Dissymmetrical radial and pruned radial interpolation
US6031642A (en) * 1997-12-12 2000-02-29 Hewlett-Packard Company Tetrahedral and pruned tetrahedral interpolation
US6040925A (en) * 1997-12-12 2000-03-21 Hewlett-Packard Company Radial and pruned radial interpolation
US6040926A (en) * 1997-12-12 2000-03-21 Hewlett-Packard Company Common non-symmetric pruned radial and non-symmetric pruned tetrahedral interpolation hardware implementation
US6049400A (en) * 1997-12-12 2000-04-11 Hewlett-Packard Company Non-symmetric tetrahedral and non-symmetric pruned tetrahedral interpolation

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WO1989005082A1 (en) * 1987-11-16 1989-06-01 Intel Corporation Pixel interpolation circuitry as for a video signal processor
EP0426296A2 (en) * 1989-10-30 1991-05-08 Advanced Micro Devices, Inc. Apparatus having modular interpolation architecture

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EP0079542A2 (en) * 1981-11-16 1983-05-25 General Electric Company Two-dimensional digital linear interpolation system
US4783698A (en) * 1987-04-13 1988-11-08 Technology Inc., 64 Interpolator for compressed video data
WO1989005082A1 (en) * 1987-11-16 1989-06-01 Intel Corporation Pixel interpolation circuitry as for a video signal processor
EP0426296A2 (en) * 1989-10-30 1991-05-08 Advanced Micro Devices, Inc. Apparatus having modular interpolation architecture

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0923037A1 (en) * 1997-12-12 1999-06-16 Hewlett-Packard Company Common pruned radial and pruned tetrahedral interpolation hardware implementation
FR2772492A1 (en) * 1997-12-12 1999-06-18 Hewlett Packard Co Dissymmetrical radial and pruned radial interpolation
US5966474A (en) * 1997-12-12 1999-10-12 Hewlett-Packard Company Non-symmetric radial and non-symmetric pruned radial interpolation
US6028683A (en) * 1997-12-12 2000-02-22 Hewlett-Packard Company Common pruned radial and pruned tetrahedral interpolation hardware implementation
US6031642A (en) * 1997-12-12 2000-02-29 Hewlett-Packard Company Tetrahedral and pruned tetrahedral interpolation
US6040925A (en) * 1997-12-12 2000-03-21 Hewlett-Packard Company Radial and pruned radial interpolation
US6040926A (en) * 1997-12-12 2000-03-21 Hewlett-Packard Company Common non-symmetric pruned radial and non-symmetric pruned tetrahedral interpolation hardware implementation
US6049400A (en) * 1997-12-12 2000-04-11 Hewlett-Packard Company Non-symmetric tetrahedral and non-symmetric pruned tetrahedral interpolation

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