JP2577797B2 - Pixel density conversion circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pixel density conversion circuit that converts the number of pixels in one line in an image reading device that reads an image image line by line.

[Conventional technology]

FIG. 5 is a block diagram showing a conventional pixel density conversion circuit. In the figure, reference numeral 1 denotes image data, 2 denotes an image data synchronization clock (hereinafter referred to as a synchronization clock) in which one clock corresponds to one pixel of the image data, Reference numeral 3 denotes a clock thinning circuit for thinning out the synchronous clock 2 according to a predetermined rule, 5 a latch circuit for latching the image data 1 by the thinning clock 4 output from the clock thinning circuit 3, and 6 a converted image data.

Next, the operation will be described with reference to the timing chart shown in FIG. Since each clock of the synchronous clock 2 corresponds to each pixel of the image data 1, first, a clock corresponding to a pixel to be thinned out by the clock thinning circuit 3 is thinned out from the synchronous clock 2 (FIG. 6 (c)). Since the thinning clock 4 output from the clock thinning circuit 3 has the latch timing of the latch circuit 5, the data latched by the latch circuit 5 eventually becomes the thinned image data. This is the converted image data 6. The example shown in FIG. 6 is an example in which one pixel is thinned out every four pixels and the whole is reduced to 3/4, and the fourth nth pixel (n = 1, 2, 3,...) From the head of one line Are thinned out, and the converted image data 6 is composed of first, second, third, fifth... Pixels.

When image data 1 as shown in FIG. 7 is input, thinning is performed according to the rule shown in FIG. 6, and as shown in FIG. Will be. In addition to the rules shown in FIG. 6, no matter how the rules are determined, if the pixel distribution of the image data 1 matches the thinning rule, it is converted to all white tines.

[Problems to be solved by the invention]

Since the conventional pixel density conversion circuit is configured as described above, the thinned pixels are not reflected at all in the image data 6 after conversion, and no matter how the thinning rule is determined, depending on the pixel distribution There has been a problem that a part that becomes all white or all black occurs.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem. When performing conversion of image data, the thinned pixels are reflected in the converted image data, and a conversion closer to the original image data is performed. The purpose is to obtain later image data.

[Means for solving the problem]

A pixel density conversion circuit according to the present invention is provided with a pixel storage means for sequentially inputting one line of image data for each pixel and storing a predetermined number of pixels, and a count means for counting a synchronous clock. The pixel which is input by the data determination unit which receives the stored value of the data and the timing information which is the count value output by the counter means at the time when the value of the timing information is thinned out by the clock thinning circuit (thinned pixel) When the next pixel is input, the stored value of the pixel storage means refers to the thinned pixel, the next pixel to the thinned pixel, and several pixels before the thinned pixel. The determined data is output to the latch circuit.

[Operation] The data determining unit according to the present invention refers to the current input pixel obtained from the pixel storage unit, several pixels before the current input pixel, and the thinned pixels to generate data to be output to the current input pixel. , So that the thinned pixels can be reflected.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, reference numeral 7 denotes a shift register (pixel storage means) for inputting image data 1 one pixel at a time and shifting one pixel at a time by a synchronous clock 2, 8 an address counter (counting means) for counting the synchronous clock 2, Reference numeral 9 denotes a ROM (data determination unit) that outputs data stored in advance by using the 4-bit parallel output of the shift register 7 and the 4-bit count value of the address counter 8 as address inputs. The other components are denoted by the same reference numerals and are the same as those shown in FIG.

Next, the operation will be described with reference to FIG. 2 and FIG. FIG. 2 shows one line of image data 1 as in the conventional example.
6 is a timing chart in a case where is reduced to 3/4. Parallel output of the shift register 7 is inputted most recently entered pixel (current input pixel) in the address A _0, the pixel entered it previously, so as to sequentially input into address A ₁ to A _3, RO
Connected to M9. Further, the count value of the address counter 8 LSB address A ₄ and enter the upper digit than is connected to sequentially input to the address A ₅ to A _7. FIG. 3 is a correspondence diagram showing the correspondence between the value of the address input and the value of the data D output from the ROM 9. This response,
It is also the correspondence between the address of the ROM 9 and the stored data. Note that in FIG. 3, "1" and the value was definite according to the values and the address A ₄ to A ₅ of the address A ₀ to A _3, "0" means a black pixel, a white pixel. Further, the address A ₃ "X" indicates that "1", may be either "0".

As shown in FIG. 2, in the case of 3/4 reduction, the image data 1 is thinned out when the addresses A ₄ and A ₅ both become “1”. Therefore, when the addresses A ₄ and A ₅ are (0, 0) (the left side corresponds to the lower address, the same applies hereinafter), the pixel immediately after the thinning is input to the shift register 7 and the address A ₀ is set. It has appeared. When the addresses A ₄ and A ₅ are (1, 0), the second pixel after the thinning has appeared at the address A ₀ , and when the addresses A ₄ and A ₅ are (0, 1), , so that the third pixel after thinning appeared to address a _0. Therefore, the third
If the corresponding data shown in the figure is stored in the ROM 9, the output data D becomes appropriate according to the pixel distribution. Third
In the figure, when the addresses A ₄ and A ₅ are (1,0) or (0,1) (the second or third pixel after the thinning is the address A ₀
In the was the case) that appear, to output as the current input pixel appearing on address A _0, data stored in ROM9 is
Matched to the current input pixel. On the other hand, when the addresses A ₄ and A ₅ are (0, 0), the data stored in the ROM 9 is stored in the ROM 9 because the address A ₁ corresponds to the thinned pixel and the address A ₀ corresponds to the current input pixel. , it determined from a pixel corresponding to the address a ₀ to a _2. For example, when the addresses A _{0 to} A ₂ are (1, 0, 0) (the order opposite to the order shown in FIG. 3, the left side corresponds to the address A _{0. The} same applies hereinafter). “1” is stored in the ROM 9 so that “1” is output according to the input pixel “1”.
When the addresses A _{0 to} A ₂ are (1, _0, 1), “0” is stored in the ROM 9. Thus, when the image data 1 continues from “1” → “0” → “1”, the converted image data 6 continues from “1” → “0”. In the case of the related art, “1” → “1” continues, and the changing point between “1” and “0” disappears. When the addresses A _{0 to} A ₂ are ( _{0, 1,} 1), “0” is stored in the ROM 9. Thus, when the image data continues from “1” → “1” → “0”, the converted image data 6 continues from “1” → “0”. When the addresses A ₄ and A ₅ are (1, 1), the data stored in the ROM 9 does not need to be defined because the current input pixels are thinned out. Further, in the case of the present embodiment, since up to the pixel immediately before the thinned pixel is targeted for reference, the address
The value of A ₃ is "1", in either case "0", the data stored in ROM9 may be the same. Of course, the pixels before the immediately preceding pixel may be referred to, and this is effective when the thinning interval is wider than in the present embodiment.

Here, a case where image data 1 as shown in FIG. 7 is input will be described. When the fifth pixel is input to the shift register 7, the addresses A ₄ and A ₅ become (0, 0), so that the data D output from the ROM 9 has the addresses A ₄ and A ₅ = Selected from column (0,0). On the other hand, since the addresses A _{0 to} A ₃ are ( _{0, 1, 0, 0} ) (the black pixel is “1”), FIG. 3 shows (A ₃ , A ₂ , A ₁ , A ₀ ) = (X,
"1" stored in the position corresponding to the row (0, 1, 0) is output. Hereinafter, such an operation is repeated, and eventually, at the timing synchronized with the synchronous clock 2, FIG.
Are sequentially output from the ROM 9.

As described above, the data D output from the ROM 9 is
As in the conventional case, the thinning clock 4
And becomes the converted image data 6 shown in FIG. 4 (B).

In the above embodiment, the upper 4 bits are assigned to the output of the address count 8 and the lower 4 bits are assigned to the parallel output of the shift register 7 as the address input of the ROM 9.
The number of bits of each address and the way of assignment may be changed, and the same effects as in the above embodiment can be obtained.

Further, in the above embodiment, the converted image data 6 is output as serial data, but may be output after being converted into parallel data.

〔The invention's effect〕

As described above, according to the present invention, the pixel density conversion circuit determines the value of the pixel following the pixel decimated by referring to the pixel decimated by the data decision unit and several pixels before and the current input pixel. Is determined, so that it is possible to obtain an image which can prevent image quality deterioration of the thinned image data regardless of the pixel distribution.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a pixel density conversion circuit according to an embodiment of the present invention. FIG. 2 is a timing chart for explaining the operation of the pixel density conversion circuit shown in FIG.
FIG. 4 is a correspondence diagram showing correspondence between ROM address input and data, FIG. 4 is a data configuration diagram showing a state of image data after conversion, FIG. 5 is a block diagram showing a conventional pixel density conversion circuit, and FIG. FIG. 7 is a timing chart for explaining the operation of the pixel density conversion circuit shown in FIG. 5, FIG. 7 is a data configuration diagram showing an example of image data, and FIG. It is a data structure figure shown. 1 is image data, 2 is an image data synchronous clock, 3 is a clock thinning circuit, 5 is a latch circuit, 6 is converted image data, 7 is a shift register (pixel storage means), 8 is an address counter (counting means), 9 is a ROM (data determination unit). In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

(57) [Claims] 1. A pixel storage means for sequentially inputting one line of image data composed of a plurality of pixels for each pixel and storing a predetermined number of the pixels, and an image signal synchronization clock synchronized with the pixels. Counting means for counting and outputting timing information indicating the relationship between the point in time when the pixel thinning occurs and the current input pixel; a clock thinning circuit for thinning out the image signal synchronous clock according to a predetermined rule; and When the stored value of the storage unit and the timing information output by the counting unit are input and the timing information indicates that the next pixel of the pixel from which the pixel has been thinned out has been input, the stored value corresponds to the thinning out of the stored value. When the pixel before the pixel and the next pixel after the thinned pixel are the same pixel, the thinned pixel is output, and the pixel before the pixel corresponding to the thinning among the stored values is output. When the pixel next to the pixel that has been decimated is different from the pixel that has been decimated, the pixel next to the pixel that has been decimated is output as it is, and a pixel other than the pixel that is next to the pixel whose timing information has been decimated. Is input, the pixel density conversion unit includes a data determination unit that outputs an input pixel as it is, and a latch circuit that latches an output value of the data determination unit with a thinning clock output by the clock thinning circuit. circuit.