JP3311555B2 - Image memory readout circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image memory (image memory) for reading out serial image data corresponding to an address in a one-to-one correspondence at a high speed, one pixel at a time, without being limited to a designated address. The present invention relates to a read control circuit of a circuit.

[0002]

2. Description of the Related Art In general, when image data is read from an image memory, 2 ⁿ (n ≧ 1) pixels are read as one cell in a reading direction at a time, and the read cell is selected for high-speed reading. To obtain an image of each pixel. FIG. 2 is an explanatory diagram of a cell. The cell address X in FIG. 2 indicates an address that is the first in the cell when viewed from the origin 0, that is, an address represented by a value excluding lower n bits. The cell internal address x is defined as 1, with the cell closest to the origin as 0,
2,..., 2 ⁿ⁻¹ , that is, an address represented by a value of only lower n bits. FIG.
FIG. 9 is a configuration diagram of a conventional image memory reading circuit. FIG. 4 is a configuration diagram of the read control circuit in FIG. FIG.
8 are timing charts of FIG. 3 when n = 3 (8 pixels per cell), the start address in the reading direction is 0h, and the end address is 2Fh.

The operation of FIGS. 3 and 4 will be described below with reference to FIGS. When the start address S1 and the end address S2 are set and the read start signal S3 for one clock CLK is given, the start address S1 is loaded into the address counter 2. On the other hand, in the read control circuit 1, the difference between the address values of the cell address of the start address S1 and the cell address of the end address S2 is obtained from the address subtraction circuit 12 and loaded into the down counter 13. The down counter 13 receives the clock C
Counting down every LK, and when counting down by the difference of the address value, the borrow signal S4 is output to the enable generation circuit 14.
Output to The enable generation circuit 14 uses the read start signal S3 as a trigger to generate the read start signal S3.
3 and a borrow signal S4 to generate an enable signal S5. A counter enable signal S8 obtained by ANDing the enable signal S5 and the enable 2 cell cycle shift signal S6 obtained by shifting the enable signal S5 by 2 ⁿ +2 ⁿ clocks by the shift register 15
Generate The counter 11 has a counter enable signal
While S8 is valid, the cell latch signal S is output every 2 ⁿ clocks.
As 10, the carry signal is output in the last clock of the cell cycle.

[0004] Enable 2 cell cycle shift signal S6
When, an enable 1 cell shift signal S7 obtained by 2 ⁿ clock (1 cell cycle) shift in the shift register 15 an enable signal S5, AND by the AND gate 17
Taken, and outputs the data enable signal S9. While the counter enable signal S8 is valid, the address counter 2 keeps counting up the memory cell address S11 and the memory cell internal address S12 at every 2 ⁿ clocks and at every one clock. The memory cell address S11 is input from the address counter 2 to the image memory 3, and the memory cell address S11 is input to the image memory 3.
At the end of one cell cycle (2 ⁿ clocks) holding 11, one cell (2 ⁿ pixels) of cell data S13 is output. The cell data S13 is latched in the latch 4 by the cell latch signal S10. Since the post-latch cell data S14 latched by the latch 4 is held until the next cell cycle starts, the 1-pixel selector 5 increments the memory cell internal address from 0 to 2 ⁿ -1. In S12, one pixel is selected, and data S15 after one pixel selection is obtained. Finally, in the buffer 6, the read data S16 specified by the start address S1 and the end address S2 by the data enable signal S9 is obtained.

[0005]

However, the conventional circuit for reading an image memory has the following problems. In this image memory read circuit, there is a condition that the memory cell address S11 must be held for one cell cycle in order to guarantee the cell data S13 output from the image memory 3. But,
In the conventional circuit shown in FIG. 3 , since the start address S1 is loaded into the address counter 2 , only the address value whose lower n bits are 0h can be set. If the address counter 2 address value lower n bits are not 0h
In the first cell cycle, the cycle for holding the memory cell address S11 is shortened by the lower address value. However, the latch 4 is for inputting a cell latch signal S10 after cell cycle, since data latch is no longer guaranteed. Further, since only the cell address of the start address S1 and the cell address of the end address S2 are used to generate the data enable signal S9, the lower n bits of the start address S1 are 0h and the end address S2 is (2 ⁿ -1) h. Unless it is set, the read data S16 corresponding to the address at a ratio of 1: 1 cannot be obtained. That is, in the conventional circuit, the value of the start address S1 cannot be set freely in order to guarantee the output cell data S13 from the image memory 3 . Read data S16 corresponding to 1: 1 cannot be obtained from an arbitrary start address S1 to an arbitrary end address S2 .

There was a problem that:

[0007]

In order to solve the above-mentioned problems, the present invention provides a read start signal indicating the start of reading, a start address indicating a first address of a read pixel, and an end address related to a final address of the read pixel. A read control circuit that inputs information and a clock to generate a counter enable signal, a cell latch signal, and a data enable signal; and a memory cell address that inputs the read start signal, the start address, and the counter enable signal. And an address counter for generating a memory cell internal address, an image memory for outputting cell data of 2 ⁿ (n ≧ 1) pixels at one time according to the memory cell address,
A latch for latching the cell data based on the cell latch signal, a one-pixel selector for selecting data indicated by the internal address of the memory cell from the cell data and outputting data after one-pixel selection, and a data enable signal; Accordingly, in an image memory readout circuit having a buffer for holding the data after one pixel selection, the readout control circuit has the following configuration. In other words, the read control circuit is configured to read (from the beginning of the valid period of the read start signal to the last cell indicated by the end address obtained from the end address information from the first cell indicated by the start address) number -1) includes a shift register which is clocked shifts the enable signal to be × 2 ⁿ clocks period effective from 2 ⁿ to 2 ⁿ +2 ^n.

Then, from among the clock-shifted signals, (2 ⁿ + the number of pixels included in the head cell from the head pixel of the head cell indicated by the start address to the pixel indicated by the start address− 1) A start shift selector for selecting a clock-shifted signal, and (2 ⁿ +
An end shift selector for selecting a signal that is clock-shifted (the number of pixels included in the last cell from the head pixel of the last cell indicated by the end address to the pixel indicated by the end address). Further, an AND that takes the AND of the signals selected by the start shift selector and the end shift selector
A D gate, an OR gate for ORing signals selected by the start shift selector and the end shift selector, a comparator for comparing the start cell internal address with the end cell internal address,
One of the output signals of the AND gate and the OR gate based on the comparison result of the comparator such that the beginning of the valid period corresponds to the internal address of the start cell and the end of the valid period corresponds to the internal address of the end cell. And an or-or selector for selecting the above signal and using the selected signal as the data enable signal.

[0009]

FIG. 1 is a block diagram of an image memory readout circuit showing an embodiment of the present invention. Elements common to those in FIG. 3 are denoted by common reference numerals. The difference between the image memory readout circuit of the present embodiment and the conventional image memory readout circuit is that the address counter 2
First, the address of the lower n bits is input as 0h. Second, the read control circuit 31
The shift register in the middle outputs a signal shifted by 2 ⁿ to 2 ⁿ +2 ⁿ clocks. Third, a start shift selector, an end shift selector, a comparator, an AND gate, an OR gate, and an OR selector are further provided in the read control circuit 31 so that the lower n bits of the start cell address and the end cell address are used. That is, even in the case of an arbitrary address, read data corresponding to 1: 1 can be obtained.

As shown in FIG. 1, the image memory read circuit of the present embodiment comprises a read control circuit 31, an address counter 2, a DRAM (Dynamic Random Access Memory).
ry), a latch 4, a one- pixel selector 5, and a buffer 6 such as a FIFO (First In First Out). The read control circuit 31 receives a start address S1, an end address S2, a read start signal S3, and a clock CLK, inputs a counter enable signal S8 to the address counter 2, a cell latch signal S10 to the latch 4, and a data enable signal S3.
3 are output to the buffer 6 respectively. Address counter 2, the start address S1, rie de start signal S
3, the clock CLK and the lower n-bit address 0h are input, and the memory cell address S11 is stored in the image memory 3.
In addition, the memory cell internal address S12 is
Respectively. The image memory 3 inputs the memory cell address S11 and stores the cell data S
13 is output. The latch 4 receives the cell data S13 and the cell latch signal S10, and outputs the latched cell data S14 to the one-pixel selector 5. The one-pixel selector 5 receives the latched cell data S14 and the memory cell internal address S12, and receives the one-pixel selected data S1.
5 is output to the buffer 6. The buffer S16 outputs the read data S16.

FIG. 9 is a configuration diagram of the read control circuit 31 in FIG. As shown in FIG. 9, the read control circuit 31 includes a counter 11, an address subtraction circuit 12, a down counter 13, an enable generation circuit 14, a shift register 41, an AND gate 16, a start shift selector 42, an end shift selector 43, and a comparator. 44,
It comprises an AND gate 45, an OR gate 46, and an AND or selector 47. The counter 11
The clock CLK is input, and the cell latch signal S10 is output to the latch 4. The address subtraction circuit 12 inputs the start cell address S1a in the start address S1 and the end cell address S2a in the end address S2, and outputs an address difference to the down counter 13. The down counter 13 outputs the borrow signal S4 to the enable generation circuit 14. The enable generation circuit 14 includes a read start signal S3, a borrow signal S4, and a clock CL.
K, and input the enable signal S5 to the shift register 41.
Output to The shift register 41 has an enable signal S
5 and the clock CLK, and the enable signal S
5 is shifted by 2 ⁿ +2 ⁿ clocks, the enable 2 cell cycle shift signal S 6 is shifted to the AND gate 16, the enable signal S 5 is shifted by 2 ⁿ to 2 ⁿ +2 ⁿ -1 clocks to the start shift selector 42, and the enable signal S 5 is shifted to the start shift selector 42. A signal shifted by 2 ⁿ +1 to 2 ⁿ +2 ⁿ clocks is output to the end shift selector 43.

The start shift selector 42 receives a signal obtained by shifting the enable signal S5 by 2 ⁿ ２2 ⁿ +2 ⁿ -1 clocks, and receives a 2 ⁿ + start cell internal address S1.
The enable start shift signal S31 clock-shifted by the value of b is supplied to the AND gate 45 and the OR gate 46.
Output to The end shift selector 43 inputs a signal obtained by shifting the enable signal S5 by 2 ⁿ +1 to 2 ⁿ +2 ⁿ clocks, and converts the enable end shift signal S32 obtained by clock shifting by 2 ⁿ + the value of the end cell internal address S2b + 1 to the AND gate 45. , And OR gate 46 . AND gate 45 and OR gate 46
The enable start shift signal S31 and the enable end shift signal S32 are input and output to the AND-OR selector 47, respectively.
Output to 10 to 13 are timing diagrams of FIG. 1 when n = 3, start address = 2h, and end address = 2Ch.

Hereinafter, FIG. 1 will be described with reference to FIGS.
The operation of FIG. 9 will be described. A start address S1 and an end address S2 are set to indicate 1 to start reading.
When the read start signal S3 for the clock CLK is given, 0h is set to the lower n bits of the address counter 2;
An address obtained by removing the lower n bits from the start address S1 is loaded into the address excluding the lower n bits. On the other hand, in the read control circuit 31, the address difference between the start cell address S1a of the start address S1 and the end cell address S2a of the end address S2 is obtained from the address subtraction circuit 12, and the down counter 1
Load 3 The down counter 13 receives the clock CL
It goes down every K and counts down by the difference of the address value, and outputs a borrow signal S4 to the enable generation circuit 14. The enable generation circuit 14 generates the read start signal S
3, the enable signal S5 is generated by the read start signal S3 and the borrow signal S4. In this example, since the start cell address S1a is 0h and the end cell address S2a is 28h, the enable signal S5
Is a period of 28h clock CLK from the rise of the read start signal S3.

The enable signal S5 is supplied to the shift register 41.
Enable (2 ⁿ ２2 ⁿ +2 ⁿ ) clock CLK shift and (2 ⁿ +2 ⁿ ) clock shift enable 2
(2 ⁿ to 2 ⁿ +2 ^{n) is} added to the cell cycle shift signal S16.
-1) The signal shifted by the clock CLK is sent to the start shift selector 42, and the signal shifted by (2 ⁿ +1 to 2 ⁿ +2 ⁿ ) clock CLK is sent to the end shift selector 43.
Respectively. The AND gate 16 performs an AND operation between the enable signal S5 and the enable 2 cell cycle shift signal S6 to generate a counter enable signal S8.
Generate The period during which the counter enable signal S8 is valid is from the rise of the read start signal S3 to (end cell address−start cell address + 2 ⁿ +
2 ⁿ ) clock period, and in this example, 28h + 2
³ + 2 ³ clock periods. The start shift register 42 decodes the start cell internal address S1b, uses the decoded signal as a selection signal, and sets the lower n bits of the start cell internal address S1 of the start address S1.
A signal shifted by the value indicated by 1b + 2 ⁿ clocks CLK is selected from the output signals of the shift register 41, and an enable start shift signal S31 is output.

In this example, since the start cell internal address S1b is 2h as shown in FIG. 12, (2 ³ +2)
The signal shifted by the clock becomes the enable start shift signal S31. The end shift selector 43 decodes the end cell internal address S2b and uses the decoded signal as a selection signal to shift the signal shifted by the value +2 ⁿ +1 clock CLK indicated by the end cell internal address S2b into the output signal of the shift register 41. And outputs the enable end shift signal S32. In this example, as shown in FIG.
Since 2b is 4h, a signal shifted by (2 ³ +5) clocks becomes the enable end shift signal S32.
An AND operation between the enable start shift signal S31 and the enable end shift signal S32 is performed by the AND gate 45.
D is taken and output to the AND or selector 47. When the value of the start cell internal address S1b ≦ the value of the end cell internal address S2b, the valid period of the output signal of the AND gate 45 starts at the beginning of the valid period of the enable start shift signal S31.
The end of the valid period of the output signal is the end of the valid period of the enable end shift signal S32.

The OR gate 46 enables the enable start shift signal S31 and the enable end shift signal S3.
2 and outputs the result to the AND OR selector 47. When the value of the start cell internal address S1b> the value of the end cell internal address S2b, this OR gate 4
The start of the valid period of the enable start shift signal S31 starts at the beginning of the valid period of the output signal of No. 6, and the end of the valid period of the output signal of the OR gate 46 ends at the end of the valid period of the enable end shift signal S32. The comparator 44 compares the value of the start cell internal address S1b with the value of the end cell internal address S2b, and outputs the comparison result to the AND OR selector 47. When the value of the start cell internal address S1b ≦ the value of the end cell internal address S2b is used as a selection signal based on the comparison result of the comparator 44, the AND OR selector 47 outputs an AND gate 45.
Is selected as the data enable signal S33. If the value of the start cell internal address S1b > the value of the end cell internal address S2b, the output signal of the OR gate 46 is selected and set as the data enable signal S33. Thus, the beginning of the valid period of the data enable signal S33 corresponds to the start cell internal address S1b, and the end of the valid period is the end cell internal address S2b.
Corresponding to

In this example, as shown in FIG. 12, the valid period of the data enable signal S33 starts at the rising edge of two cell clocks CLK and corresponds to the start cell internal address 1b (= 2h). In addition, as shown in FIG. 13, the end of the valid period is the rising edge of the cell cycle after five clocks CLK, and corresponds to the value of the end cell internal address S2b + 1 (= 4 + 1). The counter 11 outputs the carry signal as the cell latch signal S10 every 2 ⁿ clocks in the last one clock of the cell cycle while the counter enable signal S8 is valid. The address counter 2 has a counter enable signal S
8 is valid, the memory cell address S11 and the memory cell internal address S12 are changed every 2 ⁿ clocks,
Continue counting up every clock. The memory cell address S11 is input to the image memory 3, and the memory cell address S11 is held in one cell cycle (2
^In the last clock CLK of ( ⁿ clocks), one cell (2 clocks)
⁽ⁿ pixels) of cell data S13. In this example, n
Therefore, eight pixels are output at one time as the cell data S13, as shown in FIGS. Cell data S13 output from image memory 3 is latched in latch 4 by cell latch signal S10. Latched cell data S14 latched by latch 4
Is selected one pixel at a time by the memory cell internal address S12 which counts up from 0 to 2 ⁿ -1 (0 to 7 in this example) in the one-pixel selector 5, and data S15 after one-pixel selection is obtained.

[0018] Finally, in the buffer 6, from the start address S1 to the end address S2 1: the data enable signal S33 that period becomes effective period corresponding to 1, the start address S1 and end address S2,
The read data S16 for the amount specified by is obtained. In this example, the start address S1 is 2h and the end address S2
Is 2 Ch, the address in the buffer 6 is 02
Data from address h to data at address 2Ch are output. The data output to the buffer 6 is sequentially extracted as read data S16 by FIFO from the data indicated by the start address S1 to the data indicated by the end address S2.

As described above, the present embodiment has the following advantages. (A) Regardless of the value of the lower n bits of the start address S1, the address counter 2 that forcibly loads 0h to the lower n bits is provided, so that the memory cell address S11 can be always held for one cell cycle. since the output data from the memory 3 is ensured, there is an advantage that can freely set the value of the start address S1.
(B) To generate the data enable signal S33,
A shift register 41 for shifting the enable signal S5 by (2 ^{n to} 2 ⁿ +2 ⁿ -1) clocks and a start for selecting an output of the shift register 41 based on a value of a start cell internal address S1b which is a cell internal address of the start address S1. By providing the shift selector 42, the read data S16 from the pixel specified by the start address S1 (including the specified pixel) can be obtained without limitation to the value of the lower n bits of the start address S1 to be set.

(C) To generate the data enable signal S33, the enable signal S5 is changed to (2 ⁿ +1 to 2 ⁿ +
2 ⁿ ) An end address to be set is provided by providing a shift register 41 for performing a clock shift and an end shift selector 43 for selecting an output of the shift register 41 based on a value of an end cell internal address S2b which is a cell internal address of the end address S2. without limitation of the value of the lower n bits of S2, it is possible to obtain the read data S16 in up to the specified pixel (including a specified pixel) in the end address S1. (D) To generate the data enable signal S33,
A shift register 41 for clock-shifting the enable signal S5 by (2 ⁿ to 2 ⁿ +2 ⁿ );
The start shift selector 42 selects the output of the shift register 41 in accordance with the value of the start cell internal address S1b which is the cell internal address of 1 and the shift register 41 in accordance with the value of the end cell internal address S2b which is the cell internal address of the end address S1. , An comparator 44 for comparing the value of the start cell internal address S1b with the value of the end cell internal address S2b, and an enable start shift signal S3 of the output of the start shift selector 42.
1 and the enable end shift signal S32 output from the end shift selector 43 An AND OR selector 47 for selecting whether to take an AND or an OR is provided, so that the value of the lower n bits of the start address S1 to be set and the end to be set without limitation to the lower bits of the address S2, it is possible to obtain the read data S16 in the pixel specified by the start address S1 to up to pixel specified by the end address S2 (each containing the specified pixel).

Note that the present invention is not limited to the above embodiment, and various modifications are possible. For example, there are the following modifications. (1) In implementation form, to secure the image memory 3 vertical address on has been described an example of applying the horizontal direction of the read-out to set the horizontal direction address, to secure the horizontal address, a vertical By setting the address in the direction, it is also applicable to reading in the vertical direction. (2) The example in which the start address S1 and the end address S2 are set has been described, but the number of pixels to be read can be set instead of the end address S2 . In this case, a circuit for generating the end address S2 from the start address S1 and the number of pixels to be read is added.

[0022]

As described above in detail, according to the first aspect, since the address counter for loading 0h is provided, the lower address of the start address can be set arbitrarily. According to the second and fourth inventions, the shift register for shifting the enable signal by (2 ⁿ to 2 ⁿ +2 ⁿ -1) clocks and the start shift selector are provided.
The read data from the pixel specified by the start address (including the specified pixel) can be obtained without limitation to the value of the lower n bits of the start address. According to the third aspect, since the shift register for shifting the enable signal by (2 ⁿ +1 to 2 ⁿ +2 ⁿ ) clocks and the end shift selector are provided, the end address is not limited to the lower n bits of the end address. The read data up to the pixel specified (including the specified pixel) can be obtained.
According to the fourth aspect, the enable signal is set to (2 ⁿ to 2 ⁿ +
2 ⁿ ) Since a shift register for performing clock shift, a start shift register, a comparator, an end shift selector, an AND gate, an OR gate, and an OR selector are provided, the lower n bits of the start address and the lower n bits of the end address can be used. Without limitation, read data from the pixel specified by the start address to the pixel specified by the end address (including the specified pixel) can be obtained.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an image memory read circuit according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram of a cell.

FIG. 3 is a configuration diagram of a conventional image memory reading circuit.

FIG. 4 is a configuration diagram of a read control circuit in FIG. 3;

5 is a timing chart of FIG. 3 when n = 3, start address = 0h, and end address = 2Fh.

FIG. 6 is a timing chart of FIG. 3 when n = 3, start address = 0h, and end address = 2Fh.

FIG. 7 is a timing chart of FIG. 3 when n = 3, start address = 0h, and end address = 2Fh.

FIG. 8 is a timing chart of FIG. 3 when n = 3, start address = 0h, and end address = 2Fh.

FIG. 9 is a configuration diagram of a read control circuit in FIG. 1;

FIG. 10 is a timing chart of FIG. 1 when n = 3, start address = 2h, and end address = 2Ch.

11 is a timing chart of FIG. 1 when n = 3, start address = 2h, and end address = 2Ch.

FIG. 12 is a timing chart of FIG. 1 when n = 3, start address = 2h, and end address = 2Ch.

FIG. 13 is a timing chart of FIG. 1 when n = 3, start address = 2h, and end address = 2Ch.

[Explanation of symbols]

2 Address counter 3 Image memory 4 Latch 5 1 pixel selector 6 Buffer 11 Counter 12 Address subtraction circuit 13 Down counter 14 Enable generation circuit 15 Shift register 16 AND gate 31 Read control circuit 41 Shift register 42 Start shift selector 43 End shift selector 44 Comparator 45 AND gate 46 OR gate 47 AND or selector

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-8-129552 (JP, A) JP-A-2-68672 (JP, A) JP-A-1-217528 (JP, A) JP-A-62-162 160573 (JP, A) JP-A-61-120260 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G06T 1/60 450 G06F 12/00 580 Patent file (PATOLIS) JICST file (JOIS)

Claims (4)

(57) [Claims] 1. A read start signal indicating the start of reading, a start address indicating a first address of a read pixel, end address information relating to a final address of a read pixel, and a clock, and a counter enable signal, a cell latch signal, And a read control circuit for generating a data enable signal; an address counter for receiving the read start signal, the start address, and the counter enable signal to generate a memory cell address and a memory cell internal address; An image memory that outputs cell data of 2 ⁿ (n ≧ 1) pixels at one time according to an address; a latch that latches the cell data based on the cell latch signal; Data shown above An image memory readout circuit, comprising: a one-pixel selector for selecting one of the address counters and outputting one-pixel selected data; and a buffer for holding the one-pixel selected data in accordance with the data enable signal. An image memory read circuit, wherein "0h" is loaded into lower n bits. 2. A counter enable signal, a cell latch signal, a read start signal indicating a start of reading, a start address indicating a first address of a read pixel, end address information on a final address of the read pixel, and a clock are input. And a read control circuit that generates a data enable signal; an address counter that receives the read start signal, the start address, and the counter enable signal to generate a memory cell address and a memory cell internal address; An image memory that outputs cell data of 2 ⁿ (n ≧ 1) pixels at one time according to an address; a latch that latches the cell data based on the cell latch signal; Showing data in the cell An image memory readout circuit comprising: a one-pixel selector for selecting one of the data from the data selector and outputting data after one-pixel selection; and a buffer for holding the one-pixel-selected data in accordance with the data enable signal. From the beginning of the valid period of the read start signal, the circuit includes (the number of cells to be read from the first cell indicated by the start address to the last cell indicated by the end address obtained from the end address information-1) × 2 periods of 2 ⁿ clocks the enable signal is valid from the 2 ^{n n} +
A shift register for clock-shifting to 2 ⁿ -1; and (2 ⁿ + (from the head pixel of the head cell indicated by the start address to the head pixel from the head cell indicated by the start address) among the clock-shifted signals. A start shift selector for selecting a clock-shifted signal that is a start cell internal address which is the number of pixels not to be read contained in the cell minus 1). 3. A counter enable signal, a cell latch signal, a read start signal indicating a start of reading, a start address indicating a first address of a read pixel, end address information regarding a final address of the read pixel, and a clock. And a read control circuit that generates a data enable signal; an address counter that receives the read start signal, the start address, and the counter enable signal to generate a memory cell address and a memory cell internal address; An image memory that outputs cell data of 2 ⁿ (n ≧ 1) pixels at one time according to an address; a latch that latches the cell data based on the cell latch signal; Showing data in the cell An image memory readout circuit comprising: a one-pixel selector for selecting one of the data from the data selector and outputting data after one-pixel selection; and a buffer for holding the one-pixel-selected data in accordance with the data enable signal. From the beginning of the valid period of the read start signal, the circuit includes (the number of cells to be read from the first cell indicated by the start address to the last cell indicated by the end address obtained from the end address information-1) × The enable signal valid for 2 ⁿ clocks is changed from 2 ⁿ +1 to 2
ⁿ and the shift register to the clock shift to +2 ^n, the clock shifted (2 ⁿ + 1 + out of the signal
(End cell internal address which is (the number of pixels to be read included in the last cell from the head pixel of the last cell indicated by the end address to the pixel indicated by the end address -1)) An image memory read circuit, comprising: an end shift selector for selecting. 4. A counter enable signal, a cell latch signal, a read start signal indicating a start of reading, a start address indicating a first address of a read pixel, end address information regarding a final address of the read pixel, and a clock. And a read control circuit that generates a data enable signal; an address counter that receives the read start signal, the start address, and the counter enable signal to generate a memory cell address and a memory cell internal address; An image memory that outputs cell data of 2 ⁿ (n ≧ 1) pixels at one time according to an address; a latch that latches the cell data based on the cell latch signal; Showing data in the cell An image memory readout circuit comprising: a one-pixel selector for selecting one of the data from the data selector and outputting data after one-pixel selection; and a buffer for holding the one-pixel-selected data in accordance with the data enable signal. From the beginning of the valid period of the read start signal, the circuit includes (the number of cells to be read from the first cell indicated by the start address to the last cell indicated by the end address obtained from the end address information-1) × an enable signal which becomes 2 ⁿ clocks period effective from 2 ⁿ 2 ⁿ +2
a shift register which is clocked shift to ^n, included in the first cell from the first pixel of the first cell indicated (2 ⁿ + the start address from said clock shifted signal to the pixel indicated by the start address A start shift selector for selecting a signal shifted by a clock (start cell internal address which is the number of pixels not to be read −1); and (2 ⁿ +1+) from among the clock-shifted signals.
(The end cell internal address which is the number of pixels to be read included in the last cell from the head pixel of the last cell indicated by the end address to the pixel indicated by the end address minus one) An end shift selector for selecting; an AND gate for ANDing a signal selected by the start shift selector and the end shift selector; and an OR for ORing a signal selected by the start shift selector and the end shift selector. A gate for comparing the start cell internal address with the end cell internal address; based on a comparison result of the comparator, a start of a valid period corresponds to the start cell internal address, and an end of the valid period is the end cell. Internal address And an AND-OR selector for selecting one of the output signals of the AND gate and the OR gate and using the selected signal as the data enable signal.