JPH05174144A - Histogram calculation circuit - Google Patents

Abstract

PURPOSE:To realize a histogram calculation circuit with high frame rate by constituting two memories so that their roles may be alternated with each other every continuous frame. CONSTITUTION:When a RAM 12 is again cleared while a histogram value is added to a RAM 10, each B input terminal of multiplexers 10, 26 is selected by switching a control signal SEL to a H level and the upper 10 bits of the histogram value are stored in the RAM 12 after the point of the time. Thus, the picture data for one picture is successively inputted and the histogram is determined. Next, the histogram of the picture data for a second frame is determined in the same way. In this case, the roles of the RAM 10 and RAM 12 are alternated. Therefore, a histogram calculation circuit which does not require almost or entirely time to clear memory can be obtained only by providing a memory having capacity which is equivalent to almost one memory in a conventional manner.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a histogram calculation circuit for calculating a histogram of time series data in a frame of time series data constituting a frame.

[0002]

2. Description of the Related Art For example, a histogram calculation circuit is known in which density data for each pixel is sequentially input in time series to calculate a density histogram for one image. As an example of this histogram calculation circuit, Japanese Patent Laid-Open No. 1-20178
In Japanese Patent Laid-Open No. 2 (1994), image data (density value data) is used as a memory address, and the data stored in the memory area indicated by the address is incremented by 1 to count the number of data (density histogram) of each density value data. A circuit system that does this has been proposed.

[0003]

Here, in the case of calculating a density histogram for each frame which is successively input in succession, a set of time-series density data for one image is regarded as one frame, and the above-mentioned conventional method is used. If the proposed circuit system is adopted as it is, the histogram of a certain frame is stored in the memory and the histogram in the memory is read out.
After that, the calculation of the histogram of the next frame cannot be started until some time has passed until the contents of the memory are all cleared, which causes a problem that the frame rate becomes low.

In order to solve this problem, two memories capable of storing a histogram of one image (one frame) are provided, and while one memory is used to calculate the histogram. It is conceivable to form a sequence of clearing the contents of the other memory. With this configuration, it is not necessary to take time to clear the contents of the memory, and therefore the frame rate can be increased.

However, if this circuit system is adopted, a memory for two frames is required this time, so that there is a problem that the circuit scale increases and the cost increases. In view of the above circumstances, the present invention provides a histogram calculation circuit excellent in cost performance, which secures a high frame rate and does not need to be increased in circuit scale to include a memory for two frames as described above. With the goal.

[0006]

The histogram calculation circuit of the present invention for achieving the above object is designated by an address corresponding to the input time series data each time the time series data is input. By repeating the operation of reading the histogram value recorded in the memory area and adding 1 to the histogram value and recording again in the memory area specified by the address over one frame of the time series data, In the histogram calculation circuit that calculates the histogram of time series data,
Two memories in which one or the other of the low-order bit side and the high-order bit side of the bit string representing the sequentially integrated histogram values, in which the function is alternated for each successive frame of the time series data, are recorded, An initialization circuit is provided for initializing the memory in which the high-order bit side of the integrated histogram value is recorded within a time in which all the high-order bit side is represented in the initial state.

Here, the memory in which the lower bit side is recorded has a flag corresponding to each address of the memory, and the histogram calculation circuit causes each of the memories in which the lower bit side is recorded for the frame. When writing the histogram value 1 to each memory area corresponding to the address for the first time, it is necessary to write the histogram value 1 and write the flag corresponding to the address of the memory area in which the histogram value 1 is written to start the accumulation of the histogram values. A configuration including a write control circuit for setting the state shown may be used.

[0008]

When the histogram is calculated by inputting time-series data from the outside, when one piece of data is input, the contents stored in the memory area specified by the address corresponding to the data are read out and read out. The sequence is such that +1 is added to the contents and the contents obtained by adding +1 again are stored in the memory area specified by the address. At this time, the input of the time-series data and the sequence are performed by one clock. It runs at a speed synchronized with.

Here, the time required to calculate the histogram of the time-series data for one frame and the time required to clear the entire memory by sequentially selecting addresses of the memory and writing 0 are described, for example, as the frame size 512.
For image data composed of × 512 (the number of pixels in one frame is 262144) and gradation 256 (the number of words in the memory is 256), the time required to calculate the histogram of the time-series data for one frame (clock The number of pixels is 2621 because the number of pixels is 262144.
Forty-four clocks are required, while the time (number of clocks) required to clear the entire memory is 256 clocks because the number of words in the memory is 256. Therefore, the time required to clear the entire memory in the histogram calculation circuit is considerably shorter than the time required to input time-series data for one frame.

The present invention has been completed in view of the above points, and one or the other of the lower bit side and the upper bit side of the bit string representing the sequentially integrated histogram values is recorded. Memory, and an initialization circuit for initializing the memory in which the upper bit side of the sequentially integrated histogram values is recorded within the time when the upper bit side is all represented in the initial state. Two memories are provided for each successive frame. Are configured to alternate their roles. In this case, the total memory capacity of the two memories is approximately one frame, which means that it is not necessary to provide a time for clearing the memories by providing only one memory in the conventional example.

Here, when accumulating the time-series data forming the immediately preceding frame, there is a case where a value already stored in each memory area of the memory used for recording on the upper bit side is stored, It is not initialized when you start using this memory as the memory where the lower bit side is recorded,
Therefore, when the histogram value 1 is first stored in each memory area of the memory, it is necessary to store the histogram value 1 regardless of the contents recorded in each memory area. For this reason, a flag for distinguishing whether or not the accumulation of the histogram value is started is required for each memory area of the memory in which the histogram value of the lower bit side is recorded. A flag memory composed of flags corresponding to respective addresses of each of the two memories is provided corresponding to each of the two memories, and when each of the memories is initialized as a memory in which the upper bit side is recorded, The corresponding flag memory is also initialized, and when the histogram value 1 is stored as a memory in which the lower bit side is recorded, the corresponding flag memory is set to a state indicating that the accumulation of histogram values has started. It may be configured to be set, or is provided with only one of the above flag memories, and a histogram of time series data of the immediately preceding frame During and read, or may be initialized immediately before the like to start the calculation of the histogram of the time series data of the frame,
For example, as shown in an embodiment described later, a flag may be provided in the memory in which the lower bit side is recorded. In this case, a flag memory other than the above two memories is unnecessary, and a histogram calculation circuit with a simpler configuration is realized. To be done.

[0012]

EXAMPLES Examples of the present invention will be described below. Figure 1
2 is a circuit block diagram showing a histogram calculation circuit according to an embodiment of the present invention, FIG. 2 is a timing chart of the histogram calculation circuit shown in FIG. 1, and FIG. 3 is a diagram schematically showing each memory area in the RAM. is there.

Table 1 is a table for explaining the symbols shown in FIG. Here, in FIG. 1, the control signal line of each multiplexer is omitted in order to avoid complexity.

[0014]

[Table 1] ───────────────────────────── SEL1LA Control signal of the multiplexer 14 SEL2LA Control signal of the multiplexer 16 OR1IN Input signal of the OR gate 30 Input signal of OR2IN OR gate 32 SEL3LA control signal of multiplexer 18 SEL4LA control signal of multiplexer 20 SEL5LA control signal of multiplexer 22 SEL6-1 control signal of multiplexer 24 SEL6-2 control signal of multiplexer 24 SEL7-1 control signal of multiplexer 26 SEL7- 2 Control signal of the multiplexer 26 ──────────────────────────── SEL1LA to SEL5L among the control signals shown here
A means that when these are at the L level, the input signal on the A side of each multiplexer 14-22 is selected, and when they are at the H level, the input signal on the B side of each multiplexer 14-22 is selected. is doing.

With respect to the multiplexers 24 and 26, their inputs are selected as shown in Table 2.

[0016]

[Table 2] ──────────────────────────── SEL6-1 SEL6-2 Selected input SEL7-1 SEL7-2 LL AL H B H L C H H − ────────────────────────────────────────────────────────────────────
0, 12 are provided, but these RAMs 10, 1
As shown in FIG. 3, 2 has 2 words each having 10 bits and each having 256 words.

Here, it is necessary to clear both of the two RAMs 10 and 12 when the power supply of the histogram calculation circuit shown in FIG. 1 is turned on, and at this time, at time t _{1 of} FIG.
, The control signals SEL1LA and SEL2LA go to L level, which causes the multiplexers 14 and
The 16 inputs are switched to the A side which allows the count value output from the counter 28 to pass. The output terminals 14a and 16a of the multiplexers 14 and 16 are connected to the write address input terminals 10a and 10a of the RAMs 10 and 12, respectively.
12a is connected. In addition, the control signal SEL6-1,
SEL6-2; SEL7-1 and SEL7-2 are all at the L level, and the inputs of the multiplexers 24 and 26 are switched to the A side where all 0s are input to the parallel 10 bits.
These multiplexers 24, 26 have respective output terminals 24
a and 26a are signal input terminals 10 of the RAMs 10 and 12, respectively.
b, 12b, and the RAM 1 is incremented as the count output of the counter 28 is incremented by 1.
0 is written in all areas of 0 and 12, so that RAM
Both 10 and 12 are cleared.

When the RAMs 10 and 12 have been cleared at time t2 shown in FIG.
512 per image that makes up the first frame after 3
Image data consisting of × 512 pixels and 8 bits (256 gradations) for each pixel is sequentially input to the address generation unit 34 in time series for each pixel. At time t3 immediately before the input is started, As shown in FIG. 2, the control signals SEL1LA and SEL2LA are at H level and L level, respectively.
As a result, the multiplexer 14 becomes the address generation unit 34 side and the multiplexer 16 becomes the counter 28 side. Further, the signals OR1IN and OR2IN at one input terminal of each of the OR gate circuits 30 and 31 become L level and H level, respectively.
Outputs a signal having the same logic as that of the signal input from the other input terminal, and the OR gate circuit 32 is in a state where an H level signal is always output. Here, the RAMs are connected to the other input terminals of the OR gate circuits 30 and 32, respectively.
The contents of the most significant bit of the 1-word memory area designated by the addresses input from the read address terminals 10c and 12c of 10 and 12 are read and input. Here, the lower 9 bits of the histogram value are stored in the RAM 10, and the most significant bit (see FIG. 3) of the RAM 10 is stored.
(Refer to) is used as a logical flag described later. Further, the RAM 10 stores the upper 10 bits of the histogram value. Therefore, the same signal as the logic level of the logic flag is output from the OR gate 30. In addition, each control signal SEL3LA, SEL4LA, SE
L5LA becomes H level, L level, and H level, respectively, and the B side of multiplexers 18, 20, 22 respectively, A
Side and B side inputs are selected. Furthermore, each control signal SEL
6-1 and SEL6-2; SEL7-1 and SEL7-2 become H level, L level; L level and L level, respectively, and the C side and A side inputs of the multiplexers 24 and 26 are selected.

As described above, each multiplexer 14-26
When the image data corresponding to one pixel is input to the address generation unit 34 after the switching of the, the address generation unit 34 generates an address signal with the density value represented by the image data as an address, and first, both Read address input terminals 10 of RAMs 10 and 12
c, 12c. At this time, 1 word (10 bits) of data is output from the RAM 10 from the memory area corresponding to the designated address. The lower 9 bits of these 10 bits of data are the AND gate circuit 3.
6 is directly input from one of the input terminals, and the most significant bit (logical flag) is input to the AND gate circuit 36 from the other input terminal via the OR gate circuit 30. Therefore, if the most significant bit (logical flag) is "0" (here, all are 0 because they are all cleared between times t1 and t2), the AND gate circuit 3
All 6's output "0", and the all "0" signals are input to the adder 42. The RAM 12 outputs 10-bit data recorded at the address input from the read address terminal 12c, and the lower 9 bits of the 10-bit data are the AND gate circuit 38.
Is input from one of the input terminals. The OR gate circuit 32 has an OR2IN of "1" at one of its input terminals.
Since this is input, the OR gate circuit 32 always outputs "1". Therefore, the lower 9-bit signal input to the AND gate circuit 38 read from the RAM 12 passes through the AND gate circuit 38. Further, it is input to the adder 42 via the multiplexer 20. The most significant bit of the 10-bit signal read from the RAM 12 is input to the OR gate circuit 32 from the input terminal of the OR gate circuit 32.

In the adder 42, 1 is added to the input 18-bit signal, the most significant bit (logical flag) of logic '1' is added to the lower 9 bits of the signal, and the address is generated via the multiplexer 24. The data is stored in the memory area specified by the address generated by the unit 34 and input from the write address terminal 10a of the RAM 10 via the multiplexer 14. Here, the address input from the write address terminal 10a is the same address as the address input from the read address terminal 10c.

In addition, a total of 10 bits of the upper 9 bits of the value obtained by adding 1 to the 18 bits input to the adder 42 and the most significant bit representing the carry are output from the adder 42 and are multiplexed. It is input to its input terminal 26 from its B input terminal, but since the multiplexer 26 has its A input terminal selected as described above, a 10-bit signal of all "0" is input to the RAM 12, and the counter 2
'0' is written in the address generated in 8 and input to the write address terminal 12a via the multiplexer 16. That is, the RAM 12 is cleared again between the times t3 and t4 shown in FIG. Also, while the RAM 12 is being cleared again, the image data is input to the address generation unit 34, and this address generation unit causes RA
The address of M10 is specified, but if this specified address is the same as the address already specified in this first frame, the most significant bit (logical flag) is "1". , The lower 9 bits of the low-order 9 bits pass through the AND gate circuit 36 as they are, and are further input to the adder 42 via the multiplexer 18.
1 is added to the histogram value already stored in the bit, and the histogram value is stored again in the memory area of the RAM 10 at the same address.

When the RAM 12 is cleared again while the histogram values are being added to the RAM 10 as described above, at time t4 shown in FIG. 2, SEL2LA,
The SEL 7-2 is switched to the H level and the B input terminals of the multiplexers 16 and 26 are selected by this, whereby the RAM 10 stores the upper 10 bits of the histogram value after that point.

As described above, the image 1 is displayed by the time t5.
The image data for one sheet is sequentially input and the histogram is obtained. After this time t5, the reading mode is entered,
A signal designating an address for reading the histograms stored in the RAMs 10 and 12 instead of the image data is input to the address generation unit 34, and R is read in the same manner as above.
Histogram values are read from the AMs 10 and 12 and taken out via the output buffer circuit 40.

Next, after the time t6, the histogram of the image data for the second frame is obtained in the same manner as described above, but the sequence is the case of the first frame except that the roles of the RAM 10 and the RAM 12 are switched. The description is omitted because it is the same as. Note that here, as a result of calculating the histogram for the first frame, RA
The most significant bit of the upper bits of the histogram value recorded in M becomes '1', so that the lower bit side of the histogram value is stored for this second frame from the beginning when the integration of the histogram value is started for the second frame. It is conceivable that the logical flag of the RAM 2 that has been set is "1". However, as described above, since an image composed of 512 × 512 pixels is handled here, the most significant bit of the 10 bits on the high-order bit side becomes “1” when all 512 × 512 pixels are processed. This corresponds to the case where the density values are the same, and in this case, the lower 9 bits of the upper 10 bits are all "0", so that the most significant bit of a memory area of the RAM 12 is "0" for the first frame. When the histogram of the second frame is obtained next, the most significant bit, which has become "1", is used as a logical flag, and histogram values have already been accumulated for that memory area from the beginning of histogram calculation. Even if the lower 9 bits of the 10-bit signal read from the RAM 12 pass through the AND gate circuit 38 as they are, 9-bit signal is that the integration of the histogram value without any problem because it is all "0" is performed.

Next, at time t7, the RAM 10 and the RAM
The 12 roles are replaced again, and the histogram is similarly calculated for the third frame.

[0026]

As described above, the histogram calculation circuit of the present invention includes two memories in which one or the other of the high-order bit side and the low-order bit side of the bit string representing the sequentially integrated histogram values is recorded. , An initialization circuit for initializing a memory in which the high-order bit side of the sequentially integrated histogram values is recorded within a time when all the high-order bit side is expressed in an initial state, and two memories play the role in each successive frame. Since it is configured so as to alternate, a histogram calculation circuit with a high frame rate is realized by providing a memory having a capacity almost equal to one memory in the conventional example and requiring little or no time to clear the memory. ..

[Brief description of drawings]

FIG. 1 is a circuit block diagram showing a histogram calculation circuit according to an embodiment of the present invention.

FIG. 2 is a timing chart of the histogram calculation circuit shown in FIG.

FIG. 3 is a diagram schematically showing each memory area in a RAM.

[Explanation of symbols]

 10, 12 RAM 14, 16, 18, 20, 22, 26 Multiplexer 28 Counter 30, 32 OR gate circuit 34 Address generation unit 36, 38 AND gate circuit 42 Adder

Claims (2)

[Claims] 1. Each time each piece of time-series data is input, a histogram value recorded in a memory area designated by an address corresponding to the input time-series data is read out and 1 is added to the histogram value. In the histogram calculation circuit for calculating the histogram of the time series data in the frame by repeating the operation of recording again in the memory area designated by the address over one frame of the time series data, 2 memories in which one or the other of the low-order bit side and the high-order bit side of the bit string representing the histogram value that is sequentially accumulated, in which the function is changed for each frame, and the histogram value that is sequentially accumulated The upper bit side is recorded within the time when all of the upper bit side is expressed in the initial state. Histogram calculation circuit, characterized in that it includes a initialization circuit for initializing the directory. 2. The memory in which the lower bit side is recorded has a flag corresponding to each address of the memory, and the histogram calculation circuit causes each of the memories in which the lower bit side is recorded for the frame. When writing the histogram value 1 to each memory area corresponding to the address for the first time, the histogram value 1 is written, and the flag corresponding to the address of the memory area in which the histogram value 1 is written is started. 2. The histogram calculation circuit according to claim 1, further comprising a write control circuit for setting the state to be represented.