JPH0678017A - Frame conversion circuit - Google Patents

Abstract

PURPOSE:To allow the frame conversion circuit to easily correspond to data speed or data length. CONSTITUTION:A CPU 6 generates the timing data D3 of a timing pulse S1 in accordance with the data speed information D1 and data length information D2 of a previously inputted input signal Si. A RAM circuit 3 stores timing data D3 through a buffer 2 and then generates and sends the timing pulse S1 to a frame conversion part 1 in accordance with an address signal S2 synchronized with the signal Si. The conversion part 1 extracts the data of each frame in the signal Si in accordance with the signal S1 and executes frame conversion.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame conversion circuit, and more particularly to a frame conversion circuit for converting a data string repeated in a frame at a constant cycle into another cycle or data length.

[0002]

2. Description of the Related Art FIG. 2 is a block diagram showing an example of a conventional frame conversion circuit. In this frame conversion circuit, as shown in FIG. 3, the input signal Si has two data strings A and B (each m bit, m is m ≦ m) in one frame (2n bits).
3 shows a circuit configuration including n).

The frame conversion unit 1 is composed of a memory circuit 1
1 and 12 and a signal processing circuit 13. The memory circuits 11 and 12 have write timing pulses S11 and S, respectively.
After writing the data trains A and B of the input signal Si in accordance with 12, the data trains are separated by reading out according to the read timing pulse S13.
It is sent out as So2. The signal processing circuit 13 outputs the signal So
1 and So2 are received and sent as an output signal So having a predetermined cycle or data length.

When the number of data in one frame increases, the number of memory circuits is increased according to the number of data.

By the way, if the input data string always has the same speed and the same data length, it is not necessary to change the write and read timing pulses, but if the data speed changes or the data length changes. , The write and read timing pulse period and pulse width must be changed. Therefore, in advance, the ROM circuit 2
The timing data of the writing and reading timing pulse is recorded in 1 and the R is set by the switching signal C21.
It corresponds by switching the data table of the OM circuit 21. The ROM circuit 22 includes a timing counter 22
It operates in response to the address signal C22 from.

[0006]

As described above, in the conventional frame conversion circuit, when the data rate or the data length changes, the data table of the ROM circuit is switched and dealt with. However, the number of tables in the ROM circuit is limited, and there is a problem in that the scale of the peripheral circuit increases as the number of tables increases.

A control method using a CPU instead of the ROM circuit is also conceivable, but it is difficult to realize because of problems such as synchronization with data and operation speed.

An object of the present invention is to provide a frame conversion circuit which can easily cope with changes in data rate and data length.

[0009]

A frame conversion circuit of the present invention is a frame conversion circuit for converting an input data string repeated at a constant cycle into another cycle or data length,
Means for extracting a predetermined data sequence from the input data sequence according to a timing pulse and performing frame conversion, and timing data for generating the timing pulse based on the data speed information and the data length information of the input data sequence. It comprises a generating means and a storage means for storing the timing data generated by the timing data generating means and generating the timing pulse.
Further, it comprises a unit for storing the timing data of the timing pulse in the storage unit before the frame conversion is started.

[0010]

The present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. As shown in FIG. 3, the input signal Si has two data strings A and B (each m) in one frame (2n bits). The bit and m indicate the circuit configuration in the case of including m ≦ n).

Here, a frame conversion unit 1 which has two storage circuits and extracts a data string to perform frame conversion, and a CPU
6, the buffer 2 for temporarily recording the timing data D3 generated by the circuit 6, the RAM circuit 3 for storing the timing data and generating the timing pulse S1, the selector 4 for selecting the address signal to be sent to the RAM circuit 3, and the input signal S.
A timing counter 5 for generating an address signal S4 in synchronism with i, a CPU 6 for generating timing data D3 and an address signal S3 designating a storage area of the timing data, and sending control signals C1 to C3 are provided. There is.

Now, as an initial setting before starting the frame conversion, the data speed information D1 and the data length information D2 of the input signal Si are inputted into the CPU 6 in advance. CPU6
Is a timing pulse S1 to be sent to the frame conversion unit 1 based on the data rate information D1 and the data length information D2.
Timing data D3 is generated and stored in the RAM circuit 3 via the buffer 2.

Now, when the input signal Si is a signal as shown in FIG. 3, for example, the write timing pulse S11 for the memory circuit of the frame conversion section 1 is:
A pulse of logic "1" is used during the period from address 1 to m, and a pulse of logic "0" during the period from address m + 1 to 2n. Therefore, the CPU 6 is input with a program for generating timing data such that such a write timing pulse S11 is obtained. By the way, RAM
The circuit 3 receives the address signal S2 via the selector 4 and stores the timing data D3. In this case, the CPU
6 controls the selector 4 by the selector control signal C1, selects either the address signal S3 or S4, and sends it to the RAM circuit 3 as the address signal S2. Here, the timing counter 5 counts up in synchronization with the input signal Si and outputs it as the address signal S4.

At the same time, the CPU 6 sends the RAM control signal C2 to the RAM circuit 3 to set the write mode,
Further, the buffer control signal C3 is sent to the buffer 2 to output the timing data D3.

Next, the CPU 6 sends out the address signal S3 and the timing data D3. Address signal S3
Input to the RAM circuit 3 through the selector 4, and
The timing data D3 is sent to the RAM circuit 3 via the buffer 2. At this time, since the RAM circuit 3 is in the write mode, the timing data D3 is written in the RAM circuit 3 according to the address signal S2. After that, the CPU 6 causes the selector 4 to select the address signal S4 from the timing counter 5 by the selector control signal C1. In addition, the RAM control signal C2 causes R
The AM circuit 3 is switched to the read mode. Further, the output of the buffer 2 is stopped by the buffer control signal C3. In such a state, the RAM circuit 3 generates the timing pulse S1 based on the timing data corresponding to the address signal S2 sent in synchronization with the input signal Si and outputs it to the frame conversion unit 1. The frame conversion unit 1 extracts the data of each frame of the input signal Si according to the timing pulse signal S1 (write timing pulses S11, S12 and read timing pulse S13) and performs frame conversion. By the way, the input signal Si
When changing the cycle and data length of the
6 has new data rate information D1 and data length information D2
Enter.

[0017]

As described above, according to the present invention, the data rate information and the data length information of the input signal are input to the CPU to generate the timing data of the timing pulse necessary for frame conversion, and the timing pulse is generated. Even if the data speed or the data length of the input signal is changed, it is possible to easily cope with it by storing the timing data of 1) in the RAM circuit and then generating the timing pulse in the RAM circuit.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing an example of a conventional frame conversion circuit.

FIG. 3 is a timing chart for explaining the operation of the frame conversion circuit.

[Explanation of symbols]

 1 Frame Converter 2 Buffer 3 RAM Circuit 4 Selector 5 Timing Counter 6 CPU Si Input Signal S1 Timing Pulse S2 to S4 Address Signal C1 to C3 Control Signal D1 Data Speed Information D2 Data Length Information D3 Timing Data

Claims (2)

[Claims] 1. A frame conversion circuit for converting an input data string repeated at a constant cycle into another cycle or data length, and performing a frame conversion by extracting a predetermined data string from the input data string according to a timing pulse. When,
A unit for generating timing data for generating the timing pulse based on the data speed information and the data length information of the input data string, and the timing data generated by the timing data generating unit are stored to store the timing pulse. A frame conversion circuit comprising: a storage unit that generates the frame conversion circuit. 2. The frame conversion circuit according to claim 1, further comprising means for storing the timing data of the timing pulse in the storage means before the frame conversion is started.