JP2636834B2 - Image processing device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus, and more particularly to an image processing apparatus suitable for bidirectionally processing image data in a dual bus configuration device.

2. Description of the Related Art Conventionally, in an image processing apparatus, a system bus for processing image data is divided into a system bus for low pixel density image data processing at a low pixel density and a system bus for high pixel density image data mainly processing at a high pixel density. In addition, a dual bus configuration that can perform processing independently of each other is used to improve the processing capability of the entire apparatus. However, when data is transferred from the high-pixel-density image data system bus to the low-pixel-density image data system bus and displayed on a CRT display, the high-pixel-density image data on the high-pixel-density image data Is converted to image data having a low pixel density, the image data is transferred to a system bus for low pixel density image data via a dual port memory connecting the two system buses. There is a problem that it takes time until is displayed.

In order to solve this problem, the present inventor has proposed an image processing apparatus in which a dual bus configuration connects two system buses with a dual port memory. A method has been proposed in which, when image data is transferred from the high-pixel-density image data system bus to the low-pixel-density image data system bus with a conversion function, density conversion is performed in the dual-port memory. (Japanese Patent Application No. 59-21)
9481). This makes it possible to reduce the time for occupying the system bus and the data transfer time for performing the density conversion.

As described above, in the conventional method, since the density conversion is “one-way”, the image data of the low pixel density image data system bus is transferred to the high pixel density image data system bus only at the low pixel density. Cannot transfer. For this reason, CR
Even if an attempt is made to use the image data created on the display buffer memory in the control device of the T display on the system bus for high pixel density image data, it cannot be used as it is. In fact, such a demand is high because the control device of the CRT display includes a high-performance graphic controller and the image data in the display buffer memory is very useful.

An object of the present invention is to provide a dual-bus processing system that processes image data having different pixel densities in response to such a conventional demand. An object of the present invention is to provide an image processing apparatus that can be used mutually.

In order to achieve the above object, the image processing apparatus of the present invention includes a system bus for high pixel density image data including a unit for processing high pixel density image data, and a unit for processing low pixel density image data. A system bus for low pixel density image data including a system bus for low pixel density image data, and a system bus for high pixel density image data and a system bus for low pixel density image data which can be processed independently of each other; A storage unit that can be written and read from both a bus and the low pixel density image data system bus; and a high-level memory provided in the storage unit and written to the storage unit from the high pixel density image data system bus. The pixel density image data is converted to the low pixel density image data by the pixel density and read into the low pixel density image data system bus. The low pixel density image data written in the storage means from the low pixel density image data system bus is converted into the high pixel density image data in pixel density and read out to the high pixel density image data system bus. This is an image processing device having a pixel density conversion circuit.

Hereinafter, the configuration of the present invention will be described in detail with reference to an embodiment.

FIG. 1 is a schematic configuration diagram of an image processing apparatus showing one embodiment of the present invention.

In FIG. 1, reference numeral 1 denotes a system bus for high pixel density image data for processing image data of high pixel density, 2 denotes a system bus for low pixel density image data for processing image data of low pixel density, and 3 and 4 denote central buses. Processing device, 5 is an image processing unit, 6 and 7 are image memories, 8 is a CRT display, 9
Is a CRT display controller, and 10 is a dual port memory with a bidirectional pixel density conversion function.

A data transfer operation between the high pixel density image data system bus 1 for processing high pixel density image data and the low pixel density image data system bus 2 for processing low pixel density image data will be described below.

The high pixel density image data that has been subjected to various processes using the central processing unit 3, the image processing unit 5, the image memory 6, and the like on the high pixel density image data system bus 1 side is
When transferring data to the system bus 2 for low pixel density image data, the data is first written to the dual port memory 10 having a bidirectional pixel density conversion function.

On the other hand, on the low pixel density image data system bus 2 side,
At the same time that the image data written in the dual port memory with bidirectional pixel density conversion function 10 is read, the image data is density-converted and read as low pixel density image data. Therefore, since the image data can be immediately displayed on the CRT display 8, the image data having the low pixel density converted by the dual-port memory 10 with the bidirectional pixel density conversion function is directly transferred to the CRT display control device 9. Is done.

The CRT display control device 9 outputs this image data to the CRT display 8 and displays the data on the screen. Further, the graphics processing can be performed by using a high-performance graphic controller built in the CRT display control device 9. Also, contrary to the above operation, CR
The low-pixel-density image data processed in the T-display control device 9 is further processed by the central processing unit 4 and the image memory 7 via the low-pixel-density image data system bus 2 as necessary.
Is written into the dual-port memory 10 with the bidirectional pixel density conversion function, the density is converted to a high pixel density simultaneously with the writing. Therefore, since the image data read from the dual-port memory 10 with the bidirectional pixel density conversion function has already been converted to the high pixel density image data, it is used immediately on the high pixel density image data system bus 1 as it is. Can be.

FIG. 2 is a detailed configuration diagram of the dual-port memory 10 with a bidirectional pixel density conversion function of the present invention, and FIG. 3 is a diagram showing the principle of density conversion according to the present embodiment.

Hereinafter, the pixel density conversion will be described with reference to FIGS.

In FIG. 2, reference numeral 20 denotes an image memory capable of storing one page of high-pixel-density image data, 21 an image memory address control circuit for controlling the address of a memory area in the image memory 20, and 22 a high-resolution image in the image memory 20. A low-pixel-density read control circuit for converting pixel-density image data into low-pixel-density image data and reading low-pixel-density image data; 23
Is a low pixel density write control circuit for converting the low pixel density image data on the low pixel density image data system bus 2 side into high pixel density image data and writing it to the image memory 20; A data bus for transferring the
27 to 29 are address buses for transferring address data, and 30 and 31 are control buses for transferring control signals for controlling each circuit in the dual port memory 10 with a bidirectional pixel density conversion function.

First, when address data is input to the image memory address control circuit 21 through the address bus 27 under the control of the control bus 30 in the system bus 1 for high pixel density image data, the image specified by the image memory address control circuit 21 is displayed. The memory address is output to the image memory 20.
Next, image data having a high pixel density is stored in the image memory 20 through the data bus 24. Here, image data with a high pixel density is assumed to be 12 dots / mm, and image data with a low pixel density is assumed to be 6 dots / mm.

High pixel density image data (12 dots / m
m) is read out as image data (6 dots / mm) having a low pixel density, as shown in FIG. 3 (a), the dots are read out one by one in the main scanning direction, and the sub-scanning is performed. In the direction, it is necessary to read out data one line at a time. For this reason, the content of the address bus 28 provided together with the control of the control bus 31 is converted into an address required for density conversion by the low pixel density read control circuit 22 and output to the address bus 29. When the converted address data in the address bus 29 is input to the image memory address control circuit 21, the designated image memory address is output to the image memory 20, and the reading of the high pixel density image data is performed. This takes place through bus 26. The high pixel density image data read through the data bus 26 is thinned out by the low pixel density read control
Is output as low pixel density image data. With the above operation, the pixel density conversion from the high pixel density image data to the low pixel density image data is performed.

When the low pixel density image data (6 dots / mm) on the system bus 2 for low pixel density image data is converted into high pixel density image data (12 dots / mm) and written into the image memory 20 As shown in FIG. 3 (b), two dots are created by overlapping one dot in the main scanning direction, and two lines are created by further overlapping one line in the sub-scanning direction. I do. For this reason, the contents in the address bus 28 provided together with the control of the control bus 31 are subjected to necessary address conversion by the low pixel density writing control circuit 23, and are output to the address bus 29. An address conversion operation is performed such that the same data is written to adjacent addresses. Such address-converted address data is transferred to the image memory address control circuit 21.
, The low pixel density image data in the data bus 25 on the low pixel density image data system bus 2 is subjected to dot overlap processing by the low pixel density write control circuit 23. Are output to the data bus 26 as high pixel density data. The high-pixel-density data output at the address of the image memory 20 is stored. By the above operation, when one page of low-pixel-density image data is written from the low-pixel-density image data system bus 2 into the dual-port memory 10 with the bidirectional pixel density conversion function, one page is stored in the image memory 20. Minute high pixel density image data appears, and the high pixel density image data can be arbitrarily read from the high pixel density image data system bus 1.

As described above, in this embodiment, since the system bus 1 for high pixel density image data and the system bus 2 for low pixel density image data are connected by the dual port memory 10 with the bidirectional pixel density conversion function, The high-density image data on the pixel-density image data system bus 1 is converted into low-pixel-density image data by a pixel-density conversion circuit provided in a dual-port memory 10 with a bidirectional pixel-density conversion function. System bus 2 for low pixel density image data
The low-density image data on the low-pixel-density image data system bus 2 is converted to a high-pixel-density image by a pixel-density conversion circuit provided in a dual-port memory 10 with a bidirectional pixel-density conversion function. The pixel density is converted into data and can be used on the system bus 1 for high pixel density image data. Further, since the system bus 1 for high pixel density image data and the system bus 2 for low pixel density image data are integrated by the dual port memory 10 having a bidirectional pixel density conversion function provided with a pixel density conversion circuit, The system bus 1 for high-density image data and the system bus 2 for low-pixel-density image data can write and read each other, that is, can mutually use image data.

Effects As described above, according to the present invention, the system bus 1 for high-pixel-density image data and the system bus 2 for low-pixel-density image data include a dual port with a bidirectional pixel density conversion function provided with a pixel density conversion circuit. By being connected by the memory 10, the system bus 1 for high pixel density image data and the system bus 2 for low pixel density image data which can be processed independently are integrated. Therefore, independent parallel processing can be performed by the system bus 1 for low pixel density image data and the system bus 2 for low pixel density image data, and the image data processed by the system bus 1 for high pixel density image data is Dual port memory 10 with bidirectional pixel density conversion function
The image data processed by the low pixel density image data system bus 2 can be used on the low pixel density image data system bus 2 by the pixel density conversion circuit provided therein. The pixel density conversion circuit provided in the memory 10 can be used on the high pixel density image data system bus 1, that is, image data having different pixel densities can be used mutually.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a configuration diagram of an image processing apparatus according to an embodiment of the present invention. FIG. 2 is a detailed configuration diagram of the dual port memory 10 with a bidirectional pixel density conversion function. FIG. 3 is a diagram showing the principle of density conversion according to the present embodiment. Description of symbols 1: System bus for high pixel density image data 2: System bus for low pixel density image data 3, 4: Central processing unit 5: Image processing unit 6, 7: Image memory 8: CRT display 9: CRT display control Device 10: Dual port memory with bidirectional pixel density conversion function 20: Image memory 21: Image memory address control circuit 22: Low pixel density read control circuit 23: Low pixel density write control circuit 24-26: Data bus 27-29: Address bus 30, 31: Control bus.

 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-60-33669 (JP, A) JP-A-58-3058 (JP, A) JP-A-59-10066 (JP, A) JP-A-60-60 96060 (JP, A) JP-A-59-79672 (JP, A)

Claims (1)

(57) [Claims] 1. A high-pixel-density image data system bus connected to at least a central processing unit and an image memory for processing high-pixel-density image data, comprising a data bus, an address bus, and a control bus. , An address bus and a control bus, at least image processing peripheral devices (8, 9) and an image memory are connected to process low pixel density image data.
A low-pixel-density image data system bus connected to the high-pixel-density image data system bus and the low-pixel-density image data system bus, each of which can independently process image data; Storage means (10) that can be written and read from both the system bus for low pixel density image data and the system bus for low pixel density image data; and the storage means provided in the storage means and from the system bus for high pixel density image data to the storage means. The high-density image data written to the low-pixel-density image data is converted to the low-pixel-density image data and read out to the low-pixel-density image data system bus, and the low-pixel-density image data system bus is transferred to the storage unit. The high pixel density is obtained by converting the written low pixel density image data into the high pixel density image data. An image processing apparatus comprising: a pixel density conversion circuit (21, 22, 23) for reading out to a system bus for image data.