JPH03116264A - Picture display memory device - Google Patents

Abstract

PURPOSE:To reduce the deterioration of the processing speed of a picture display memory device by providing a read/write interface and a ROM interface which gives a command to each read/write interface via a CPU to disable the write to a picture display memory. CONSTITUTION:The read/write interfaces 5a and 5b are provided between a communication memory 4 and a picture display memory 3 and the CPU 1a and 1b respectively. Thus the read/write is possible between both CPU 1a and 1b and the memory 4, and the read and the write are impossible and possible respectively between both CPU 1a and 1b and the memory 3. A ROM interface 6 is provided between the memory 3 and a display device 2 to enabled the read to the device 2 from the memory 3 and also to disable the write to the memory 3 from both CPU 1a and 1b during the reading mode to the device 2 with a command S1 applied to both interfaces 5a and 5b respectively. As result, the deterioration of the processing speed can be reduced for a picture display memory device.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention includes a plurality of CPUs, a display device for displaying data from each CPU, and a storage device for storing data to be displayed on the display device. The present invention relates to an improvement of an image display memory device including an image display memory.

[Conventional technology]

2. Description of the Related Art Conventionally, for example, in an image processing apparatus, the apparatus is sometimes configured with two or more CPUs in order to improve the processing speed of the entire apparatus. In this case, in order to simplify the apparatus, data from each CPU may be displayed on one display device.

In such a case, conventionally, when trying to display data of each CPU using one display device, one image display memory connected to each CPU and display device is prepared, and one display device is displayed. In response to repeated read signals, the CPU on the side that is not being read (usually the side that is read less frequently)
This causes the CPU on the side that is not being read to access the data in between readings from the display device.

[Problem to be solved by the invention]

The above conventional technology has the following problems.

In other words, in the conventional technology, data displayed on a common display device is displayed by a certain CPU on one display device for the operator to recognize, and at the same time, data is also displayed on a common display device for other CPUs to recognize. There are many. Examples of such data include the current processing status of the CPU and various error statuses.

In such a case, in the conventional technology, each CPU uses a complicated program that requires a large amount of waiting time and transfer time to transmit data to other CPUs one by one, which poses the problem of slowing down the processing speed. Ta.

The object of the present invention is to use data for display and at the same time
It is an object of the present invention to provide an image display memory device that can minimize a decrease in processing speed even when used for communication with another CPU.

[Means to solve the problem]

The above object is to provide an image display memory device comprising a plurality of CPUs, one display device for displaying data from each CPU, and an image display memory storing data to be displayed on the display device. , a communication memory provided for mutual communication between the CPUs and into which data having the same content as at least the image display memory can be written, and a communication memory between the communication memory, the image display memory, and each CPU; A read/write interface is provided between the CPUs and allows each CPU to read from and write to the communication memory, but not to read from and only write to the image display memory.

Provided between the image display memory and the display device, it enables reading from the image display memory to the display device, and disables writing from each CPU to the image display memory during this read operation. This is accomplished by providing a read-only interface that provides a command to each of the read/write interfaces.

[Effect]

The communication memory can write the same data as the image display memory. The read/write interface allows each CPU to write to and from both the communication memory and the image display memory. Therefore, when desired.

Data from each CPU can be written into both the one-image display memory and the communication memory at the same time (usually written to the same address). Further, the read/write interface cannot read data from each CPU to the image display memory, but can read data from the 5 communication memory.

Therefore, if data from a specific CPU is written to both the 5-image display memory and the communication memory at the same time,
Even when stored data in the image display memory is read out via the read-only interface and displayed on the display device, the same stored data can be read out from the communication memory by another desired CPU. . This results in
For example, when a CPU other than the CPU that is supplying the image display memory with data to be displayed on the display device wants to obtain the same data, the CPU that is supplying the data to the image display memory
[Embodiment] The present invention will be described in detail below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of an image display memory device according to the present invention, in which 1a and lb are CPUs. When the present invention is applied to an image processing device for an XIIACT device, for example, 1a is a CPU for image processing, and lb is a CPU for system control.

2 is a display device for displaying data from each of the CPUs 1a and lb; 3 is an image display memory for storing data to be displayed on the display device 2; and 4 is provided for mutual communication between the CPUs 1a and lb. , is a communication memory into which at least the same data as the image display memory 3 can be written.

Reference numerals 5a and 5b are read/write interfaces, which are provided between the communication memory 4 and the image display memory 3 and each of the CPUs 1a and 1b.
, lb can be read and written from and to the communication memory 4,
Reading between the memory 3 and the image display memory 3 is impossible, and only writing is possible. These read/write interfaces 5a and 5b are used for writing from the CPU 1a (or lb) to the communication memory 4, and for writing from the CPU 1b (or lb) to the communication memory 4.
The read timing from a) to the communication memory 4 is also adjusted.

A read-only interface 6 is provided between the image display memory 3 and the display device 2.

It enables readout from the image display memory 3 to the display device 2, and during this readout operation, each of the CPUs 1a and l
A command S1 to disable writing to the image display memory 3 from the read/write interface la, lb
It is given to

Next, the operation will be explained.

The CPU 1a or 1b, here 1a, continuously writes data to be displayed on the display device 2 into the image display memory 3 via the read/write interface 5a, and displays the data on the display device 2. do. At this time, the read/write interface 5a controls the data so that it is written into the communication memory 4 at the same time.

Further, the read/write interface 5a performs writing to the image display memory 3 in between reading data from the image display memory 3 of the display device 2 according to the signal S1 sent from the read-only interface 6. It also performs control.

The data written in the communication memory 4 is read out to the CPU 1b via the read/write interface 5b every time it is necessary, and used as appropriate.

That is, the CPU 1b writes the same data to the image display memory 3 from the CPU 1a via the read/write ink face 5a.
can be obtained without accessing . In other words, the readout process by the CPU 1b is performed independently of data readout from the image display memory 3 to the display device 2;
In PU1b, there is no waiting time for reading, and the processing time is reduced accordingly compared to the conventional device.

The operation of writing from the CPU 1a to the image display memory 3 is performed when the command S1 is written to the read-only interface 6 while reading from the image display memory 3 to the display device 2.
This operation is the same as that of the conventional device, although the data is sent to the read/write interface 5a and the data is sent to the read/write interface 5a.

Note that by making the storage capacity of the communication memory 4 larger than the storage capacity of the image display memory 3, data not displayed on one display device 2 can be exchanged between the CPUs 1a and 1b. CPU1a at this time.

An example of the memory map when viewed from 1b is shown in FIG. 2. Regarding the image display communication area 7 of the memory map shown in FIG.
PU1a and lb are communication memory 4 and image display memory 3
As for the 1 communication dedicated area 8, the CPU 1a accesses both the CPU 1a and the 1 communication dedicated area 8.

1b accesses only the communication memory 4.

In this case, the CPU 1a for the image display communication area 7,
Reading and writing from lb is performed in the same manner as described above.Writing from the CPU 1a to the 1 communication dedicated area 8 does not require access to the 1 image display memory 3 at this time, so it is written to the display bag M2. This is performed independently of data reading from the image display memory 3. Further, reading from the CPU Ib to the communication dedicated area 8 is similarly performed by the display device 2.
This is performed independently of data reading from the image display memory 3.

〔Effect of the invention〕

According to the invention, while using the data for display,
Even when used for communication with other CPUs, the reduction in processing speed can be minimized and the processing speed can be improved compared to conventional devices.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the device of the present invention, and FIG.
The figure shows an example of a memory map having two areas: an image display communication area and a communication dedicated area. la, lb...CPU, 2...Display device, 3...
Image display memory, 4... Communication memory, 5a, 5b
. . . Read/write interface, 6. Read-only interface, 7. Image display communication area, 8. Communication-only area. Kayakuchi Kaya 2 hard

Claims (1)

[Claims] 1. An image display memory device comprising a plurality of CPUs, one display device for displaying data from each of the CPUs, and an image display memory for storing data to be displayed on this display device. A communication memory provided for mutual communication between the CPUs and capable of writing at least the same data as the image display memory, and a communication memory between the communication memory, the image display memory, and each CPU. a read/write interface that allows each CPU to read and write data from and to the communication memory and only write data to and from the image display memory; and the image display memory and the display device. is provided between the image display memory and the display device, and enables reading from the image display memory to the display device, and during this read operation, each of the CPs
An image display memory device characterized by comprising: a read-only interface that gives a command to each of the read/write interfaces to disable writing from U to the image display memory.