JPH04291433A - Frame memory simultaneous reading system - Google Patents

Abstract

PURPOSE:To quickly grasp the writing states of plural frame memories in a frame memory simultaneous reading system by transmitting the OR data included in the data received from the frame memory with the state of the data received from the frame memory kept as it is. CONSTITUTION:Plural frame memories 1 are provided together with a frame memory control register 5 which holds the information on the memories 1, end a memory control part 2 which gives the access control to the memory 1. The part 2 sends the OR data obtained by applying the OR to the data read out of the memories 1 to a requester and at the same time decides whether the data received from the memories 1 are identical with the zero data or not. These decided data are temporarily held in the register 5 and then sent to the requester.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame memory simultaneous read method for simultaneously reading data from a plurality of frame memories. A color display device has a frame memory to express a plurality of colors, and a device that displays a plurality of colors simultaneously requires a larger number of frame memories. Therefore, there is a demand for faster access to the frame memory.

0002

2. Description of the Related Art Generally, frame memories are accessed from a CPU by mapping consecutive addresses from the main memory, as shown in FIG. There is. For this reason, normally one address is accessed in one access. In the write operation, the same data is simultaneously written to a plurality of frame memories 0 to 3 under the control of the RAS signal (in the case of D-RAM) or the chip select signal (in the case of S-RAM) of the memory. On the other hand, for read operations, since the data bus to the CPU is only for one frame, depending on the hardware configuration, data read from any one frame memory must be sent to the CPU, or
Alternatively, OR data obtained by ORing data read from all frame memories is sent to the CPU. The operation of the configuration shown in FIG. 4 will be briefly explained below.

[0003] At the time of simultaneous writing: the CPU
Control registers not shown in the frame memory (
After writing whether to write simultaneously to 0) to (3) and selecting multiple frame memories, simultaneously write data to the frame memories selected by the mapped memory address and write zero data to the unselected frame memories. Write .

[0004] At the time of reading: The CPU selects which frame memory (0) in a control register (not shown) in the memory control unit 21.
After writing and specifying whether to read from frame memory (0) to (3) or read the OR data of data from all frame memories (0) to (3), either frame memory (0) to (3), Or O from everything
I am trying to read R data.

[0005]

[Problem to be Solved by the Invention] Therefore, when reading from multiple frame memories, it is necessary to read data from any one frame memory, or read OR data obtained by ORing data read from all frame memories. There was a problem that only one of the following could be done, and the writing status of all frames could not be understood at once.

[0006] The present invention is capable of transmitting OR data of data from a frame memory at the time of reading, and transmitting the data while retaining the state of the data from the frame memory, thereby making it possible to quickly understand the write state of a plurality of frame memories. The purpose is

[0007]

[Means for Solving the Problems] Means for solving the problems will be explained with reference to FIG. In FIG. 1, a frame memory 1 is a memory into which data for multicolor display on the screen is written. The memory control unit 2 controls access to the frame memory 1.

The frame memory control register 5 holds the status of read data from the frame memory.

[0009]

[Operation] As shown in FIG. 1, the present invention performs an OR operation in which data read from a specified frame memory 1 is ORed by the memory control unit 2 in response to a simultaneous read request from a host.
The data is sent to the host, and it is determined whether or not the data from the designated frame memory 1 is zero data, which is temporarily held in the frame memory control register 5, and then sent to the host.

Therefore, by sending out the OR data from frame memory 1 at the time of reading, or by determining whether the data from frame memory 1 is zero data, holding it once, and sending it out, multiple frames can be read. The host can quickly understand the write state of the memory 1.

[0011]

Embodiment Next, the structure and operation of an embodiment of the present invention will be explained in detail with reference to FIGS. 1 and 2. Hereinafter, a case where a D-RAM is used as the frame memory 1 will be described as an example. In FIG. 1, frame memory 1 is a memory in which data for displaying multiple colors on the screen is written, and here, four frame memories (0) to (3) are used to display 16 colors. .

The memory control unit 2 controls access to the frame memory 1, and includes a timing control unit 3,
It is composed of a frame memory control register 5, a RAS control section 6, and the like. The frame memory control register 5 is used to set various information for controlling the frame memory 1, and to set information as to whether read data read from the frame memory 1 is zero data (the frame memory shown in FIG. 2). (See memory control register 5).

[0013] The RAS control unit 6 has a frame memory (D-
It controls access to RAM) 1. Furthermore, S-
In the case of RAM, access is controlled by chip select instead of RAS. The data control unit 7 controls writing and reading of data into and from the frame memories (0) to (3) in response to signals (RAS, CAS, R/D, etc.) from the memory control unit 2. There it is,
It is composed of a write data control circuit 71, an OR data control circuit, a zero data determination circuit 73, and the like.

The write data control circuit 71 supplies data to all frame memories (0) to (3) for simultaneous writing at the time of readout, and supplies data to all frame memories (0) to (3) for simultaneous writing.
It supplies data to the frame memory designated by 3 and also supplies zero data for writing. These write simultaneously based on instructions from the host (CPU), write data to the instructed frame memory, and write zero data to other frame memories.

The OR data control circuit 72 notifies the frame memory 2 of the result of an OR operation (one or more) of data in the frame memory indicated by FSO-0 to FSO-3. This results in
The OR data from one or more frame memories is notified to the memory control unit 2 and transferred to the host (CPU).

The zero data determination circuit 73 determines whether the data read from the frame memories (0) to (3) is zero data. This determined information is
It is notified to the memory control register 2 as FSI-0 to FSI-3 and is held in the frame memory control register 5. The host can know whether or not the frame memory 1 contains zero data just by reading the frame memory control register 5 once.

Next, the operation of the configuration shown in FIG. 1 will be explained in detail in accordance with the order shown in the flowchart shown in FIG. In FIG. 2, in S1, the host (CPU) sets the simultaneous read mode in the frame memory control register 5. This sets the simultaneous access mode bit shown in the frame memory control register 5 on the right side to 1 (simultaneous read), for example. Note that 0 is a normal mode, that is, a mode in which any one frame memory 1 is read.

[0018] S2 sets which frame memory the host will read simultaneously. This is the frame memory 3, 2 shown in the frame memory control register 5 on the right side.
, 1, or 0 is set to 1 (active) to specify the frame memory to be read simultaneously. S3
accepts frame memory read requests from the host.

S4 passes OR data to the CPU and holds data in each frame memory. This is an OR data control circuit that outputs a signal that sets only FSO-0 to FSO-3, which corresponds to the simultaneous read frame memory specified in S2, to 1 among the data read from frame memories (0) to (3). The OR circuit performs an OR operation on the signals input and taken out from the AND gates in the memory controller 2.
pass (forward) it to the host via. At this time, at the same time,
The zero data determination circuit 73 determines whether or not the data read from each frame memory 1 is zero data, and notifies the memory control unit 2 of this determination result as FSI-0 to FSI-3 and sends the result to the frame memory control register 5. hold it.

In S5, the host reads the frame memory control register 5 and passes (transfers) designated frame data (information as to whether the frame data is zero data). As described above, after the host sets the simultaneous read setting and specifies the frame memory to be read simultaneously, in response to a read request, OR data of the specified data read from frame memory 1 is executed. By determining whether the read data from each frame memory is zero data, holding it, and passing it to the host, the host can process the state written in multiple frame memories with a single read request and frame memory. It can be read by reading the memory control register 5.

[0021]

[Effects of the Invention] As explained above, according to the present invention,
At the time of read, OR data from multiple frame memories 1 is sent out, and it is determined whether the read data from the specified frame memory 1 is zero data or not, held, and sent out. 1 write status can be quickly understood by the host. This makes it possible to access (read, write) multiple frame memories 1 simultaneously, and understand the write status of multiple frame memories 1 by reading the frame memory control register once, improving drawing speed and It becomes possible to reduce the CPU load.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of one embodiment of the present invention.

FIG. 2 is an explanatory diagram of the operation of the present invention.

FIG. 3 is an example of memory mapping of a frame memory.

FIG. 4 is an explanatory diagram of the prior art.

[Explanation of symbols]

1: Multiple frame memories 2: Memory control section 3: Timing control section 5: Frame memory control register 6: RAS control section 7: Data control circuit 71: Write data control circuit 72: OR data control circuit 73: Zero data judgment circuit

Claims (1)

[Claims] 1. In a frame memory simultaneous read method in which multiple frame memories are read simultaneously, each frame memory (1) has a plurality of frame memories (1) and a frame memory control register (5) that holds information on the frame memories. ), and in response to a simultaneous read request, the memory control unit (2) performs OR data of the data read from the corresponding frame memory (1) to the request source. It is characterized in that it is configured to determine whether the data sent from the frame memory (1) and the corresponding frame memory (1) is zero data, temporarily hold it in the frame memory control register (5), and send it to the request source. Frame memory simultaneous read method.