JPH04319754A - Data transfer system - Google Patents

Abstract

PURPOSE:To prevent a computer from stopping arithmetic processing during the transfer of data and to transfer data at real time without reducing the arithmetic processing capacity of the computer by independently executing the operation of the computer and that of a direct memory access(DMA) control circuit in the same computer unit. CONSTITUTION:In respective computer units A, B for executing data transfer, respective storage circuits 2a, 2b for temporarily storing transfer data are formed as multi-port circuits, and after processing data to be stored in the circuits 2a, 2b, data writing address buses 4a, 4b, data buses 5a, 5b, transfer data reading address buses 8a, 8b from the circuits 2a, 2b, and data buses 9a, 9b are respectively separated. Thereby the operation of the 1st and 2nd computers 1a, 1b are completely separated from the operation of the 1st and 2nd DMA control circuits 3a, 3b and the 1st and 2nd computers 1a, 1b can continue processing without stopping it even in the control of transfer.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention is directed to each DMA (direct memory access) between multiple computer units.
The present invention relates to a data transfer method for exchanging data via a control circuit.

0002

2. Description of the Related Art FIG. 3 is a diagram showing the configuration of a transfer system that implements a conventional data transfer method.
B is a computer unit that constitutes the transfer system.

[0003]The computer units A and B are first and second computers 1a and 1b that perform various processes, respectively.
, first and second storage circuits 2 that temporarily store the transfer data processed by the first and second computers 1a and 1b.
a, 2b, and first and second DMs that control the transfer of transfer data stored in the first and second storage circuits.
It is composed of A control circuits 3a and 3b.

[0004] Furthermore, in the computer unit A, the first computer 1a, the first storage circuit 2a, and the first DM
The A control circuit 3a is connected by an address bus 4a for specifying data reading and writing addresses and a data bus 5a for reading and writing data.
Similarly, in computer unit B, the second computer 1b, second storage circuit 2b, and second DMA control circuit 3b are also connected by an address bus 4b and a data bus 5b.

[0005] And, between each computer unit A and B, there is a first
and a transfer data bus 6 and first and second D for transmitting transfer data via the second DMA control circuits 3a and 3b.
MA control circuits 3a and 3b are connected by a transfer control signal line 7 for controlling transfer.

Next, the operation will be explained. Here, a case will be described in which data is transferred from computer unit A to computer unit B.

First, in the computer unit A on the sending side, the computer 1a temporarily stores the processed data at an address in the first storage circuit 2a specified via the address bus 4a via the data bus 5a. When the transfer preparation is completed, a transfer instruction is output to the first DMA control circuit 3a. After receiving this instruction, the first DMA control circuit 3a outputs a transfer control signal to the second DMA control circuit 3b on the receiving side via the transfer control signal line 7, performs a handshake, and transfers the transfer control signal to the storage circuit 2a. The temporarily stored transfer data is read out via the address bus 4a and data bus 5a and output to the transfer data bus 6.

On the other hand, in the computer unit B on the receiving side, the second DMA control circuit 3b transfers the received transfer data to
Second storage circuit 2b designated via address bus 4b
The transfer data received via the data bus 5b is temporarily stored in the address within. Then, the second computer 1b reads the designated transfer data in the second storage circuit 2b via the address bus 4b via the data bus 5b, thereby completing the transfer. Note that data transfer in the opposite direction is similarly performed from computer unit B to computer unit A.

[0009]

[Problem to be Solved by the Invention] Since the conventional data transfer method is configured as described above, it is difficult for computers and DMA
Since the control circuit writes data to and reads data from the storage circuit via the same address bus and data bus, the DAM control circuit occupies the address bus and data bus during transfer control, so the computer It is necessary to stop the arithmetic processing and put it in a hold state, and this time becomes a dead time for the computer, resulting in a problem such as a decrease in the arithmetic processing capacity.

[0010] This invention was made in order to solve the above-mentioned problems, and it eliminates the suspension of arithmetic processing of a computer during data transfer, and enables data transfer in real time without reducing the arithmetic processing capacity of the computer. The purpose is to obtain a data transfer method that makes it possible.

[0011]

[Means for Solving the Problems] The data transfer method according to the present invention is such that in each computer unit that performs data transfer, a memory circuit for temporarily storing transferred data is made into a multi-port, and a data transfer method for writing data into the memory circuit after processing is provided. The address bus and data bus for the storage circuit are separated from the address bus and data bus for reading transfer data from the storage circuit.

0012

[Operation] The data transfer method in this invention multi-ports the storage circuit in each computer unit, and provides an address bus, a data bus, and a DMA for control by the computer.
Since the address bus and data bus for controlling transfer by the control circuit are separated, the transfer operations of the computer and the DMA control circuit can be performed independently.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of a transfer system that implements a data transfer method according to an embodiment of the present invention, and the same or equivalent parts as in the conventional transfer system (FIG. 3) are given the same reference numerals and explained. Omitted.

In the figure, the first and second storage circuits 2a and 2b are each multi-ported, with 8
a and 8b are the first and second DMA control circuits 3a, respectively.
, 3b are newly provided address buses exclusively for transfer control, and 9a and 9b are similarly newly provided data buses.

Next, the operation will be explained. Here, a case will be described in which data is transferred from computer unit A to computer unit B.

First, in the computer unit A on the sending side, the computer 1a temporarily stores the processed data at an address in the first storage circuit 2a designated via the address bus 4a via the data bus 5a. When the transfer preparation is completed, a transfer instruction is output to the first DMA control circuit 3a, and the process moves on to other arithmetic processing. After receiving this instruction, the first DMA control circuit 3a outputs a transfer control signal to the second DMA control circuit 3b on the receiving side via the transfer control signal line 7, performs a handshake, and transfers the transfer control signal to the storage circuit 2a. The temporarily stored transfer data is read out via the address bus 8a and data bus 9a and output to the transfer data bus 6.

On the other hand, in the computer unit B on the receiving side, the second DMA control circuit 3b transfers the received transfer data to
Second storage circuit 2b designated via address bus 8b
The transfer data received via the data bus 9b is temporarily stored in the address within. Then, the second computer 1b reads the designated transfer data in the second storage circuit 2b via the address bus 4b via the data bus 5b, thereby completing the transfer.

At this time, the first and second computers 1a, 1b
The operations of the first and second DMA control circuits 3a and 3b are completely separated, and the operations of the first and second DMA control circuits 3a and 3b are completely separated.
A and 1b do not need to stop processing even if transfer control is in progress. In the case of data transfer in the opposite direction, data is transferred from computer unit B to computer unit A in the same manner.

In the above embodiment, the data transfer source computer unit and the data transfer destination computer unit are one
Although the case of one pair has been described, the same effect can be achieved even if there are multiple data transfer destinations, as shown in FIG.

[0020]

As described above, according to the present invention, in each computer unit, the memory circuit for temporarily storing transfer data is made into a multi-port, and the address bus and data bus for writing processed data to the memory circuit are multi-ported. Since the address bus and data bus for reading transfer data from the storage circuit are separated, data can be transferred in real time without stopping the computer's arithmetic processing even during transfer control. There is.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a transfer system that implements a data transfer method according to an embodiment of the present invention.

FIG. 2 is a block diagram showing the configuration of a transfer system that implements a data transfer method according to another embodiment of the present invention.

FIG. 3 is a block diagram showing the configuration of a transfer system that implements a conventional data transfer method.

[Explanation of symbols]

1a, 1b First and second computers

Claims (1)

[Claims] 1. Within one computer unit, a DMA control circuit reads data processed by a computer and written to a storage circuit via an address bus and a data bus via the address bus and a data bus, In a data transfer method in which data is transferred by handshaking with a DMA control circuit in another computer unit, the memory circuit in each computer unit is multi-ported, and the address for writing processed data from the computer to the memory circuit. By separating the bus and data bus from the address bus and data bus through which the DMA control circuit reads data transferred from the storage circuit, the computer and data bus within the same computer unit can be separated.
A data transfer method characterized by making the operation of the MA control circuit independent.