JPH10143429A - Multiport memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily provide a mass dual port memory. SOLUTION: Two memories 1 and 2 are physically provided, and a port 4 for read and a port 5 for write are provided with switches(SW) 31 and 32 for alternatively switching input/output buses 11 and 21 of these memories 1 and 2. In this case, these SW 31 and 32 are controlled by a bus SW control part 33 so that the mass dual port memory can be provided for simultaneously enabling read and write.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiport memory, and more particularly to a multiport memory suitable for use as a frame memory for storing image information for one screen when digital image data is displayed on a display device such as a television. It concerns port memory.

[0002]

2. Description of the Related Art Generally used SRAM (Static)
Random Access Memory (DRAM) and Dynamic Random Access Memory (DRAM)
Since a memory using a storage element such as an Access Memory has only one input / output port, a multi-port memory having a plurality of input / output (port) functions cannot be configured with the same configuration. .

Therefore, a method of realizing a multi-port function by changing the configuration of a memory element in a memory has been proposed, as disclosed in Japanese Patent Application Laid-Open Nos. 4-85790 and 4-31896. I have.

[0004]

In a method of obtaining a multi-port memory by changing the configuration of a memory element in a memory, a memory having a memory element configuration which has been widely used conventionally cannot be used. It is necessary to manufacture a memory having a memory element structure, making it difficult to increase the density, and eventually reducing the storage capacity. Therefore, the frame memory for storing data equivalent to one screen display used when displaying digital image data on a display device has an insufficient storage capacity and is unsuitable.

Further, the above-mentioned multiport memory has a disadvantage that reading and writing to the same address cannot be performed simultaneously.

SUMMARY OF THE INVENTION An object of the present invention is to provide a multi-port memory which can be used for a frame memory with a large storage capacity and can simultaneously read and write the same address.

[0007]

According to the present invention, first and second memories, a read port to which an external read bus is connected, a write port to which an external write bus is connected, Bus connection control for selectively connecting the input / output buses of the first and second memories to the read port and selectively connecting the input / output buses of the first and second memories to the write port And a multi-port memo is provided.

The bus connection control means includes first switch means for selectively connecting the input / output buses of the first and second memories to the read port, and the first and second memory means for the write port. A second switch for selectively connecting an input / output bus of the second memory; and a second switch for selectively connecting the input / output bus of the first memory to the second switch when the first switch is selectively connected to the input / output bus of the first memory. The switch means has a switch control means for controlling to selectively connect an input / output bus of the second memory.

Further, the bus connection control means further includes memory clear means for clearing all of the stored contents of the first and second memories, and the memory clear means is turned on by the first switch means. It is characterized in that the memory is cleared in response to an external signal indicating that all the stored contents of the memory to which the output bus is selectively connected are completed.

Further, the switch control means is configured to control the switching of the connection selection state of the first and second switch means in response to the completion of the memory clear operation, and the switch control means. Is configured to generate a notification signal for notifying the connection selection state of the first and second switch means to the outside.

Further, the first and second memories are assigned the same address in both address spaces, and each of the first and second memories stores image information corresponding to one display screen. It is a memory capable of storing.

The operation of the present invention will be described. A function of switching address buses, data buses, and control lines connected to these memories so that two memories of one port are used and each becomes a write-only memory and a read-only memory with the same address value (hereinafter referred to as a bus SW). ). There are two independent sets of address buses, data buses, and control line ports. The bus SW switches two independent sets of address, bus, data bus, and control lines by the bus SW at the same time. Make it accessible. This switching timing is performed by a switching command when access to the entire memory area is completed. By doing so, reading and writing can be performed freely without worrying about collision of the same address. Further, a large-capacity memory can be handled.

[0013]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. Referring to FIG. 1, memories 1 and 2 are, for example, DRAMs which are physically independent from each other, for example, and both have a sufficient storage capacity to store image data (color image data) corresponding to one display screen. It is assumed that the same address is assigned to both address spaces.

The bus SW (switch) unit 3 includes memories 1 and
The two input / output buses 11 and 21 are selectively switched to two ports 4 and 5, respectively. Port 4 is a port to which an external read bus X is connected, and port 5 is a port to which an external write bus Y is connected. Each bus X, Y is assumed to be composed of an address / data / control line.

The bus SW unit 3 includes two SWs (switches) 3
1 and 32, a bus SW control unit 33 for controlling these two SWs, and a memory clear control unit 34 for performing memory clear control of the memories 1 and 2.

The SW 31 is a switch for selectively connecting the input / output bus 11 of the memory 1 to the ports 4 and 5 and the clear bus Z of the memory clear controller 34. Also, S
W32 is a switch for selectively connecting the input / output bus 21 of the memory 2 to the ports 4, 5 and the clearing bus Z.

The bus SW control unit 33 controls the SWs 31 and 32 in accordance with an instruction of the control line X1 from the controller 6 connected to the external read bus X.
The control state (connection selection state) of W31 and W32 is changed to the control line Y
1 to the controller 7 connected to the external write bus Y.

The memory clear control unit 34 automatically starts clear control of all the stored contents of the memory 1 or 2 in response to an instruction from the bus SW control unit 33. At this time, the bus SW control unit 33 In response to this, an instruction to control the SWs 31 and 32 is issued so that the clearing bus Z is connected to the input / output bus of the memory to be cleared.

In such a configuration, the operation of the embodiment of the present invention will be described in detail with reference to the flowchart of FIG.
Now, assuming that the memory 1 is in the read state, SW31
Is configured such that the input / output bus 11 of the memory 1 is connected to the read bus X of the port 4, and at this time, the SW 32
Is such that the input / output bus 21 of the memory 2 is connected to the write bus Y of the port 5, and therefore, the memory 2 is in a write state.

The controller 6 monitors the addresses on the address bus of the read bus X. When the highest address is generated, the reading of the memory 1 is completed, that is, all the image data for one screen of the memory 1 is read. Know that it has been read. In response to this (step 201), the controller 6 notifies the bus SW controller 33 of the completion of the reading via the control line X1.

In response to this notification, the bus SW control unit 33 instructs the SW 31 to select the clear bus Z to clear the memory 1 (step 202). At the same time, it instructs the memory clear control unit 34 to start a clear operation. In response, the memory clear control unit 3
4 operates so as to automatically clear all stored contents of the memory 1 (set to "0") (step 20).
3).

When the clear operation is completed (step 2)
04), the memory clear control unit 34 notifies the bus SW control unit 33 of the fact. In response to this, the bus SW control unit 33 sets the SW3 so that the memory 1 becomes the write-side memory.
1 for the input / output bus 11 of the memory 1
(Port 5) (Step 20)
5). At this time, the SW 32 is controlled to connect the input / output bus 21 of the memory 2 to the read bus X (port 4) so that the other memory 2 becomes a read-side memory.

Since the state of this SW is notified from the bus SW control unit 33 to the controller 7 via the write bus Y via the signal line Y1, the controller 7
It is possible to know that 31 and 32 have been switched, and thereby it can be determined that new data can be written.

The memory clear operation control is generally performed by software processing. However, when the memory capacity becomes large as in a frame memory,
In this example, the memory clear control unit 34 is provided in hardware separately from software, so that the memory clear control unit 34 is provided with hardware. Thus, high-speed clear processing is achieved and the processing of software is reduced by realizing it with the hardware of No. 34.

As described above, since the physically separate memories 1 and 2 are provided, reading and writing can be performed simultaneously, and there is no occurrence of collision of the same address.

[0027]

As described above, according to the present invention, a multi-port memory can be constructed by using a large-capacity memory having a one-port input / output function, so that reading and writing can be performed simultaneously, and physically separated. This has the effect of eliminating collisions due to accesses to the same address due to the memory. Furthermore,
By providing the memory clear unit, it is not necessary to clear the memory by the address bus X, the data bus X, and the control line X. That is, when the bus line of the CPU is connected to the bus, software processing is reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a flowchart showing the operation of the embodiment of FIG.

[Explanation of symbols]

 1, 2 Memory 3 Bus SW unit 4, 5 Port 6, 7 Controller 11, 21 I / O bus 31, 32 SW (switch) 33 Bus SW control unit 34 Memory clear control unit

Claims (7)

[Claims] An external read bus connected to the first and second memories; a write port connected to an external write bus; and the first and second memories connected to the read port. And bus connection control means for selectively connecting the input / output buses of the first and second memories to the write port. Port memory. 2. The bus connection control means includes first switch means for selectively connecting an input / output bus of the first and second memories to the read port, and the first and second switch means for connecting the write port to the first and second memories. A second switch for selectively connecting an input / output bus of the second memory; and a second switch for selectively connecting the input / output bus of the first memory to the second switch when the first switch is selectively connected to the input / output bus of the first memory. 2. The multi-port memory according to claim 1, wherein said switch means includes switch control means for controlling connection of said input / output bus of said second memory. 3. The bus connection control unit further includes a memory clear unit that clears all of the stored contents of the first and second memories, and the memory clear unit includes the first and second memories.
Is configured to clear the memory in response to an external signal indicating that all the storage contents of the memory to which the input / output bus is selectively connected by the switch means are completed. The multi-port memory according to claim 2, wherein: 4. The apparatus according to claim 1, wherein said switch control means is configured to control switching of a connection selection state of said first and second switch means in response to completion of said memory clear operation. 3. The multiport memory according to 3. 5. The switch control unit according to claim 2, wherein the switch control unit is configured to generate a notification signal for notifying a connection selection state of the first and second switch units to the outside. Multi-port memory as described. 6. The multiport memory according to claim 1, wherein the first and second memories have the same address assigned to both address spaces. 7. The multiport memory according to claim 1, wherein each of said first and second memories is a memory capable of storing image information corresponding to one display screen.